sys/i4b/layer1/ifpi/i4b_ifpi_isac.c

   1 /*-
   2  * Copyright (c) 1997, 2000 Hellmuth Michaelis. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*---------------------------------------------------------------------------
  27  *
  28  *      i4b_ifpi_isac.c - i4b Fritz PCI ISAC handler
  29  *      --------------------------------------------
  30  *      $Id: i4b_ifpi_isac.c,v 1.3 2000/05/29 15:41:41 hm Exp $
  31  *      last edit-date: [Mon May 29 15:22:52 2000]
  32  *
  33  *---------------------------------------------------------------------------*/
  34
  35 #include <sys/cdefs.h>
  36 __FBSDID("$FreeBSD$");
  37
  38 #include "opt_i4b.h"
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/mbuf.h>
  43 #include <sys/socket.h>
  44
  45 #include <net/if.h>
  46
  47 #include <i4b/include/i4b_debug.h>
  48 #include <i4b/include/i4b_ioctl.h>
  49 #include <i4b/include/i4b_trace.h>
  50
  51 #include <i4b/layer1/i4b_l1.h>
  52
  53 #include <i4b/layer1/isic/i4b_isic.h>
  54 #include <i4b/layer1/isic/i4b_isac.h>
  55 #include <i4b/layer1/isic/i4b_hscx.h>
  56
  57 #include <i4b/layer1/ifpi/i4b_ifpi_ext.h>
  58
  59 #include <i4b/include/i4b_global.h>
  60 #include <i4b/include/i4b_mbuf.h>
  61
  62 static u_char ifpi_isac_exir_hdlr(register struct l1_softc *sc, u_char exir);
  63 static void ifpi_isac_ind_hdlr(register struct l1_softc *sc, int ind);
  64
  65 /*---------------------------------------------------------------------------*
  66  *      ISAC interrupt service routine
  67  *---------------------------------------------------------------------------*/
  68 void
  69 ifpi_isac_irq(struct l1_softc *sc, int ista)
  70 {
  71         register u_char c = 0;
  72         NDBGL1(L1_F_MSG, "unit %d: ista = 0x%02x", sc->sc_unit, ista);
  73
  74         if(ista & ISAC_ISTA_EXI)        /* extended interrupt */
  75         {
  76                 c |= ifpi_isac_exir_hdlr(sc, ISAC_READ(I_EXIR));
  77         }
  78
  79         if(ista & ISAC_ISTA_RME)        /* receive message end */
  80         {
  81                 register int rest;
  82                 u_char rsta;
  83
  84                 /* get rx status register */
  85
  86                 rsta = ISAC_READ(I_RSTA);
  87
  88                 if((rsta & ISAC_RSTA_MASK) != 0x20)
  89                 {
  90                         int error = 0;
  91
  92                         if(!(rsta & ISAC_RSTA_CRC))     /* CRC error */
  93                         {
  94                                 error++;
  95                                 NDBGL1(L1_I_ERR, "unit %d: CRC error", sc->sc_unit);
  96                         }
  97
  98                         if(rsta & ISAC_RSTA_RDO)        /* ReceiveDataOverflow */
  99                         {
 100                                 error++;
 101                                 NDBGL1(L1_I_ERR, "unit %d: Data Overrun error", sc->sc_unit);
 102                         }
 103
 104                         if(rsta & ISAC_RSTA_RAB)        /* ReceiveABorted */
 105                         {
 106                                 error++;
 107                                 NDBGL1(L1_I_ERR, "unit %d: Receive Aborted error", sc->sc_unit);
 108                         }
 109
 110                         if(error == 0)
 111                                 NDBGL1(L1_I_ERR, "unit %d: RME unknown error, RSTA = 0x%02x!", sc->sc_unit, rsta);
 112
 113                         i4b_Dfreembuf(sc->sc_ibuf);
 114
 115                         c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 116
 117                         sc->sc_ibuf = NULL;
 118                         sc->sc_ib = NULL;
 119                         sc->sc_ilen = 0;
 120
 121                         ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES);
 122                         ISACCMDRWRDELAY();
 123
 124                         return;
 125                 }
 126
 127                 rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1));
 128
 129                 if(rest == 0)
 130                         rest = ISAC_FIFO_LEN;
 131
 132                 if(sc->sc_ibuf == NULL)
 133                 {
 134                         if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
 135                                 sc->sc_ib = sc->sc_ibuf->m_data;
 136                         else
 137                                 panic("ifpi_isac_irq: RME, i4b_Dgetmbuf returns NULL!\n");
 138                         sc->sc_ilen = 0;
 139                 }
 140
 141                 if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
 142                 {
 143                         ISAC_RDFIFO(sc->sc_ib, rest);
 144                         sc->sc_ilen += rest;
 145
 146                         sc->sc_ibuf->m_pkthdr.len =
 147                                 sc->sc_ibuf->m_len = sc->sc_ilen;
 148
 149                         if(sc->sc_trace & TRACE_D_RX)
 150                         {
 151                                 i4b_trace_hdr_t hdr;
 152                                 hdr.unit = L0IFPIUNIT(sc->sc_unit);
 153                                 hdr.type = TRC_CH_D;
 154                                 hdr.dir = FROM_NT;
 155                                 hdr.count = ++sc->sc_trace_dcount;
 156                                 MICROTIME(hdr.time);
 157                                 i4b_l1_trace_ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
 158                         }
 159
 160                         c |= ISAC_CMDR_RMC;
 161
 162                         if(sc->sc_enabled &&
 163                            (ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S))
 164                         {
 165                                 i4b_l1_ph_data_ind(L0IFPIUNIT(sc->sc_unit), sc->sc_ibuf);
 166                         }
 167                         else
 168                         {
 169                                 i4b_Dfreembuf(sc->sc_ibuf);
 170                         }
 171                 }
 172                 else
 173                 {
 174                         NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
 175                         i4b_Dfreembuf(sc->sc_ibuf);
 176                         c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 177                 }
 178
 179                 sc->sc_ibuf = NULL;
 180                 sc->sc_ib = NULL;
 181                 sc->sc_ilen = 0;
 182         }
 183
 184         if(ista & ISAC_ISTA_RPF)        /* receive fifo full */
 185         {
 186                 if(sc->sc_ibuf == NULL)
 187                 {
 188                         if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
 189                                 sc->sc_ib= sc->sc_ibuf->m_data;
 190                         else
 191                                 panic("ifpi_isac_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
 192                         sc->sc_ilen = 0;
 193                 }
 194
 195                 if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN))
 196                 {
 197                         ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN);
 198                         sc->sc_ilen += ISAC_FIFO_LEN;
 199                         sc->sc_ib += ISAC_FIFO_LEN;
 200                         c |= ISAC_CMDR_RMC;
 201                 }
 202                 else
 203                 {
 204                         NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
 205                         i4b_Dfreembuf(sc->sc_ibuf);
 206                         sc->sc_ibuf = NULL;
 207                         sc->sc_ib = NULL;
 208                         sc->sc_ilen = 0;
 209                         c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 210                 }
 211         }
 212
 213         if(ista & ISAC_ISTA_XPR)        /* transmit fifo empty (XPR bit set) */
 214         {
 215                 if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
 216                 {
 217                         sc->sc_freeflag = sc->sc_freeflag2;
 218                         sc->sc_obuf = sc->sc_obuf2;
 219                         sc->sc_op = sc->sc_obuf->m_data;
 220                         sc->sc_ol = sc->sc_obuf->m_len;
 221                         sc->sc_obuf2 = NULL;
 222 #ifdef NOTDEF
 223                         printf("ob2=%x, op=%x, ol=%d, f=%d #",
 224                                 sc->sc_obuf,
 225                                 sc->sc_op,
 226                                 sc->sc_ol,
 227                                 sc->sc_state);
 228 #endif
 229                 }
 230                 else
 231                 {
 232 #ifdef NOTDEF
 233                         printf("ob=%x, op=%x, ol=%d, f=%d #",
 234                                 sc->sc_obuf,
 235                                 sc->sc_op,
 236                                 sc->sc_ol,
 237                                 sc->sc_state);
 238 #endif
 239                 }
 240
 241                 if(sc->sc_obuf)
 242                 {
 243                         ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN));
 244
 245                         if(sc->sc_ol > ISAC_FIFO_LEN)   /* length > 32 ? */
 246                         {
 247                                 sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */
 248                                 sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */
 249                                 c |= ISAC_CMDR_XTF;         /* set XTF bit */
 250                         }
 251                         else
 252                         {
 253                                 if(sc->sc_freeflag)
 254                                 {
 255                                         i4b_Dfreembuf(sc->sc_obuf);
 256                                         sc->sc_freeflag = 0;
 257                                 }
 258                                 sc->sc_obuf = NULL;
 259                                 sc->sc_op = NULL;
 260                                 sc->sc_ol = 0;
 261
 262                                 c |= ISAC_CMDR_XTF | ISAC_CMDR_XME;
 263                         }
 264                 }
 265                 else
 266                 {
 267                         sc->sc_state &= ~ISAC_TX_ACTIVE;
 268                 }
 269         }
 270
 271         if(ista & ISAC_ISTA_CISQ)       /* channel status change CISQ */
 272         {
 273                 register u_char ci;
 274
 275                 /* get command/indication rx register*/
 276
 277                 ci = ISAC_READ(I_CIRR);
 278
 279                 /* if S/Q IRQ, read SQC reg to clr SQC IRQ */
 280
 281                 if(ci & ISAC_CIRR_SQC)
 282                         (void) ISAC_READ(I_SQRR);
 283
 284                 /* C/I code change IRQ (flag already cleared by CIRR read) */
 285
 286                 if(ci & ISAC_CIRR_CIC0)
 287                         ifpi_isac_ind_hdlr(sc, (ci >> 2) & 0xf);
 288         }
 289
 290         if(c)
 291         {
 292                 ISAC_WRITE(I_CMDR, c);
 293                 ISACCMDRWRDELAY();
 294         }
 295 }
 296
 297 /*---------------------------------------------------------------------------*
 298  *      ISAC L1 Extended IRQ handler
 299  *---------------------------------------------------------------------------*/
 300 static u_char
 301 ifpi_isac_exir_hdlr(register struct l1_softc *sc, u_char exir)
 302 {
 303         u_char c = 0;
 304
 305         if(exir & ISAC_EXIR_XMR)
 306         {
 307                 NDBGL1(L1_I_ERR, "EXIRQ Tx Message Repeat");
 308
 309                 c |= ISAC_CMDR_XRES;
 310         }
 311
 312         if(exir & ISAC_EXIR_XDU)
 313         {
 314                 NDBGL1(L1_I_ERR, "EXIRQ Tx Data Underrun");
 315
 316                 c |= ISAC_CMDR_XRES;
 317         }
 318
 319         if(exir & ISAC_EXIR_PCE)
 320         {
 321                 NDBGL1(L1_I_ERR, "EXIRQ Protocol Error");
 322         }
 323
 324         if(exir & ISAC_EXIR_RFO)
 325         {
 326                 NDBGL1(L1_I_ERR, "EXIRQ Rx Frame Overflow");
 327
 328                 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 329         }
 330
 331         if(exir & ISAC_EXIR_SOV)
 332         {
 333                 NDBGL1(L1_I_ERR, "EXIRQ Sync Xfer Overflow");
 334         }
 335
 336         if(exir & ISAC_EXIR_MOS)
 337         {
 338                 NDBGL1(L1_I_ERR, "EXIRQ Monitor Status");
 339         }
 340
 341         if(exir & ISAC_EXIR_SAW)
 342         {
 343                 /* cannot happen, STCR:TSF is set to 0 */
 344
 345                 NDBGL1(L1_I_ERR, "EXIRQ Subscriber Awake");
 346         }
 347
 348         if(exir & ISAC_EXIR_WOV)
 349         {
 350                 /* cannot happen, STCR:TSF is set to 0 */
 351
 352                 NDBGL1(L1_I_ERR, "EXIRQ Watchdog Timer Overflow");
 353         }
 354
 355         return(c);
 356 }
 357
 358 /*---------------------------------------------------------------------------*
 359  *      ISAC L1 Indication handler
 360  *---------------------------------------------------------------------------*/
 361 static void
 362 ifpi_isac_ind_hdlr(register struct l1_softc *sc, int ind)
 363 {
 364         register int event;
 365
 366         switch(ind)
 367         {
 368                 case ISAC_CIRR_IAI8:
 369                         NDBGL1(L1_I_CICO, "rx AI8 in state %s", ifpi_printstate(sc));
 370                         if(sc->sc_bustyp == BUS_TYPE_IOM2)
 371                                 ifpi_isac_l1_cmd(sc, CMD_AR8);
 372                         event = EV_INFO48;
 373                         i4b_l1_mph_status_ind(L0IFPIUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
 374                         break;
 375
 376                 case ISAC_CIRR_IAI10:
 377                         NDBGL1(L1_I_CICO, "rx AI10 in state %s", ifpi_printstate(sc));
 378                         if(sc->sc_bustyp == BUS_TYPE_IOM2)
 379                                 ifpi_isac_l1_cmd(sc, CMD_AR10);
 380                         event = EV_INFO410;
 381                         i4b_l1_mph_status_ind(L0IFPIUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
 382                         break;
 383
 384                 case ISAC_CIRR_IRSY:
 385                         NDBGL1(L1_I_CICO, "rx RSY in state %s", ifpi_printstate(sc));
 386                         event = EV_RSY;
 387                         break;
 388
 389                 case ISAC_CIRR_IPU:
 390                         NDBGL1(L1_I_CICO, "rx PU in state %s", ifpi_printstate(sc));
 391                         event = EV_PU;
 392                         break;
 393
 394                 case ISAC_CIRR_IDR:
 395                         NDBGL1(L1_I_CICO, "rx DR in state %s", ifpi_printstate(sc));
 396                         ifpi_isac_l1_cmd(sc, CMD_DIU);
 397                         event = EV_DR;
 398                         break;
 399
 400                 case ISAC_CIRR_IDID:
 401                         NDBGL1(L1_I_CICO, "rx DID in state %s", ifpi_printstate(sc));
 402                         event = EV_INFO0;
 403                         i4b_l1_mph_status_ind(L0IFPIUNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
 404                         break;
 405
 406                 case ISAC_CIRR_IDIS:
 407                         NDBGL1(L1_I_CICO, "rx DIS in state %s", ifpi_printstate(sc));
 408                         event = EV_DIS;
 409                         break;
 410
 411                 case ISAC_CIRR_IEI:
 412                         NDBGL1(L1_I_CICO, "rx EI in state %s", ifpi_printstate(sc));
 413                         ifpi_isac_l1_cmd(sc, CMD_DIU);
 414                         event = EV_EI;
 415                         break;
 416
 417                 case ISAC_CIRR_IARD:
 418                         NDBGL1(L1_I_CICO, "rx ARD in state %s", ifpi_printstate(sc));
 419                         event = EV_INFO2;
 420                         break;
 421
 422                 case ISAC_CIRR_ITI:
 423                         NDBGL1(L1_I_CICO, "rx TI in state %s", ifpi_printstate(sc));
 424                         event = EV_INFO0;
 425                         break;
 426
 427                 case ISAC_CIRR_IATI:
 428                         NDBGL1(L1_I_CICO, "rx ATI in state %s", ifpi_printstate(sc));
 429                         event = EV_INFO0;
 430                         break;
 431
 432                 case ISAC_CIRR_ISD:
 433                         NDBGL1(L1_I_CICO, "rx SD in state %s", ifpi_printstate(sc));
 434                         event = EV_INFO0;
 435                         break;
 436
 437                 default:
 438                         NDBGL1(L1_I_ERR, "UNKNOWN Indication 0x%x in state %s", ind, ifpi_printstate(sc));
 439                         event = EV_INFO0;
 440                         break;
 441         }
 442         ifpi_next_state(sc, event);
 443 }
 444
 445 /*---------------------------------------------------------------------------*
 446  *      execute a layer 1 command
 447  *---------------------------------------------------------------------------*/
 448 void
 449 ifpi_isac_l1_cmd(struct l1_softc *sc, int command)
 450 {
 451         u_char cmd;
 452
 453 #ifdef I4B_SMP_WORKAROUND
 454
 455         /* XXXXXXXXXXXXXXXXXXX */
 456
 457         /*
 458          * patch from Wolfgang Helbig:
 459          *
 460          * Here is a patch that makes i4b work on an SMP:
 461          * The card (TELES 16.3) didn't interrupt on an SMP machine.
 462          * This is a gross workaround, but anyway it works *and* provides
 463          * some information as how to finally fix this problem.
 464          */
 465
 466         HSCX_WRITE(0, H_MASK, 0xff);
 467         HSCX_WRITE(1, H_MASK, 0xff);
 468         ISAC_WRITE(I_MASK, 0xff);
 469         DELAY(100);
 470         HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
 471         HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
 472         ISAC_WRITE(I_MASK, ISAC_IMASK);
 473
 474         /* XXXXXXXXXXXXXXXXXXX */
 475
 476 #endif /* I4B_SMP_WORKAROUND */
 477
 478         if(command < 0 || command > CMD_ILL)
 479         {
 480                 NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, ifpi_printstate(sc));
 481                 return;
 482         }
 483
 484         if(sc->sc_bustyp == BUS_TYPE_IOM2)
 485                 cmd = ISAC_CIX0_LOW;
 486         else
 487                 cmd = 0;
 488
 489         switch(command)
 490         {
 491                 case CMD_TIM:
 492                         NDBGL1(L1_I_CICO, "tx TIM in state %s", ifpi_printstate(sc));
 493                         cmd |= (ISAC_CIXR_CTIM << 2);
 494                         break;
 495
 496                 case CMD_RS:
 497                         NDBGL1(L1_I_CICO, "tx RS in state %s", ifpi_printstate(sc));
 498                         cmd |= (ISAC_CIXR_CRS << 2);
 499                         break;
 500
 501                 case CMD_AR8:
 502                         NDBGL1(L1_I_CICO, "tx AR8 in state %s", ifpi_printstate(sc));
 503                         cmd |= (ISAC_CIXR_CAR8 << 2);
 504                         break;
 505
 506                 case CMD_AR10:
 507                         NDBGL1(L1_I_CICO, "tx AR10 in state %s", ifpi_printstate(sc));
 508                         cmd |= (ISAC_CIXR_CAR10 << 2);
 509                         break;
 510
 511                 case CMD_DIU:
 512                         NDBGL1(L1_I_CICO, "tx DIU in state %s", ifpi_printstate(sc));
 513                         cmd |= (ISAC_CIXR_CDIU << 2);
 514                         break;
 515         }
 516         ISAC_WRITE(I_CIXR, cmd);
 517 }
 518
 519 /*---------------------------------------------------------------------------*
 520  *      L1 ISAC initialization
 521  *---------------------------------------------------------------------------*/
 522 int
 523 ifpi_isac_init(struct l1_softc *sc)
 524 {
 525         ISAC_IMASK = 0xff;              /* disable all irqs */
 526
 527         ISAC_WRITE(I_MASK, ISAC_IMASK);
 528
 529         if(sc->sc_bustyp != BUS_TYPE_IOM2)
 530         {
 531                 NDBGL1(L1_I_SETUP, "configuring for IOM-1 mode");
 532
 533                 /* ADF2: Select mode IOM-1 */
 534                 ISAC_WRITE(I_ADF2, 0x00);
 535
 536                 /* SPCR: serial port control register:
 537                  *      SPU - software power up = 0
 538                  *      SAC - SIP port high Z
 539                  *      SPM - timing mode 0
 540                  *      TLP - test loop = 0
 541                  *      C1C, C2C - B1 and B2 switched to/from SPa
 542                  */
 543                 ISAC_WRITE(I_SPCR, ISAC_SPCR_C1C1|ISAC_SPCR_C2C1);
 544
 545                 /* SQXR: S/Q channel xmit register:
 546                  *      SQIE - S/Q IRQ enable = 0
 547                  *      SQX1-4 - Fa bits = 1
 548                  */
 549                 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
 550
 551                 /* ADF1: additional feature reg 1:
 552                  *      WTC - watchdog = 0
 553                  *      TEM - test mode = 0
 554                  *      PFS - pre-filter = 0
 555                  *      CFS - IOM clock/frame always active
 556                  *      FSC1/2 - polarity of 8kHz strobe
 557                  *      ITF - interframe fill = idle
 558                  */
 559                 ISAC_WRITE(I_ADF1, ISAC_ADF1_FC2);      /* ADF1 */
 560
 561                 /* STCR: sync transfer control reg:
 562                  *      TSF - terminal secific functions = 0
 563                  *      TBA - TIC bus address = 7
 564                  *      STx/SCx = 0
 565                  */
 566                 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
 567
 568                 /* MODE: Mode Register:
 569                  *      MDSx - transparent mode 2
 570                  *      TMD  - timer mode = external
 571                  *      RAC  - Receiver enabled
 572                  *      DIMx - digital i/f mode
 573                  */
 574                 ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
 575         }
 576         else
 577         {
 578                 NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
 579
 580                 /* ADF2: Select mode IOM-2 */
 581                 ISAC_WRITE(I_ADF2, ISAC_ADF2_IMS);
 582
 583                 /* SPCR: serial port control register:
 584                  *      SPU - software power up = 0
 585                  *      SPM - timing mode 0
 586                  *      TLP - test loop = 0
 587                  *      C1C, C2C - B1 + C1 and B2 + IC2 monitoring
 588                  */
 589                 ISAC_WRITE(I_SPCR, 0x00);
 590
 591                 /* SQXR: S/Q channel xmit register:
 592                  *      IDC  - IOM direction = 0 (master)
 593                  *      CFS  - Config Select = 0 (clock always active)
 594                  *      CI1E - C/I channel 1 IRQ enable = 0
 595                  *      SQIE - S/Q IRQ enable = 0
 596                  *      SQX1-4 - Fa bits = 1
 597                  */
 598                 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
 599
 600                 /* ADF1: additional feature reg 1:
 601                  *      WTC - watchdog = 0
 602                  *      TEM - test mode = 0
 603                  *      PFS - pre-filter = 0
 604                  *      IOF - IOM i/f off = 0
 605                  *      ITF - interframe fill = idle
 606                  */
 607                 ISAC_WRITE(I_ADF1, 0x00);
 608
 609                 /* STCR: sync transfer control reg:
 610                  *      TSF - terminal secific functions = 0
 611                  *      TBA - TIC bus address = 7
 612                  *      STx/SCx = 0
 613                  */
 614                 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
 615
 616                 /* MODE: Mode Register:
 617                  *      MDSx - transparent mode 2
 618                  *      TMD  - timer mode = external
 619                  *      RAC  - Receiver enabled
 620                  *      DIMx - digital i/f mode
 621                  */
 622                 ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
 623         }
 624
 625 #ifdef NOTDEF
 626         /*
 627          * XXX a transmitter reset causes an ISAC tx IRQ which will not
 628          * be serviced at attach time under some circumstances leaving
 629          * the associated IRQ line on the ISA bus active. This prevents
 630          * any further interrupts to be serviced because no low -> high
 631          * transition can take place anymore. (-hm)
 632          */
 633
 634         /* command register:
 635          *      RRES - HDLC receiver reset
 636          *      XRES - transmitter reset
 637          */
 638         ISAC_WRITE(I_CMDR, ISAC_CMDR_RRES|ISAC_CMDR_XRES);
 639         ISACCMDRWRDELAY();
 640 #endif
 641
 642         /* enabled interrupts:
 643          * ===================
 644          * RME  - receive message end
 645          * RPF  - receive pool full
 646          * XPR  - transmit pool ready
 647          * CISQ - CI or S/Q channel change
 648          * EXI  - extended interrupt
 649          */
 650
 651         ISAC_IMASK = ISAC_MASK_RSC |    /* auto mode only       */
 652                      ISAC_MASK_TIN |    /* timer irq            */
 653                      ISAC_MASK_SIN;     /* sync xfer irq        */
 654
 655         ISAC_WRITE(I_MASK, ISAC_IMASK);
 656
 657         return(0);
 658 }