2 * Copyright (c) 2001 Gary Jennejohn. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 /*---------------------------------------------------------------------------
37 *---------------------------------------------------------------------------*/
42 #define ISACSX_FIFO_LEN 32 /* 32 bytes FIFO on chip */
44 #define ISACSX_V13 0x01
47 * definitions of registers and bits for the ISAC-SX ISDN chip.
50 typedef struct isacsx_reg {
52 /* 32 byte deep FIFO always first */
54 unsigned char isacsx_fifo [ISACSX_FIFO_LEN];
56 /* most registers can be read/written, but have different names */
57 /* so define a union with read/write names to make that clear */
61 unsigned char isacsx_istad;
62 unsigned char isacsx_stard;
63 unsigned char isacsx_moded;
64 unsigned char isacsx_exmd1;
65 unsigned char isacsx_timr1;
66 unsigned char dummy_25;
67 unsigned char isacsx_rbcld;
68 unsigned char isacsx_rbchd;
69 unsigned char isacsx_rstad;
70 unsigned char isacsx_tmd;
71 unsigned char dummy_2a;
72 unsigned char dummy_2b;
73 unsigned char dummy_2c;
74 unsigned char dummy_2d;
75 unsigned char isacsx_cir0;
76 unsigned char isacsx_codr1;
77 unsigned char isacsx_tr_conf0;
78 unsigned char isacsx_tr_conf1;
79 unsigned char isacsx_tr_conf2;
80 unsigned char isacsx_tr_sta;
81 unsigned char dummy_34;
82 unsigned char isacsx_sqrr1;
83 unsigned char isacsx_sqrr2;
84 unsigned char isacsx_sqrr3;
85 unsigned char isacsx_istatr;
86 unsigned char isacsx_masktr;
87 unsigned char dummy_3a;
88 unsigned char dummy_3b;
89 unsigned char isacsx_acgf2;
90 unsigned char dummy_3d;
91 unsigned char dummy_3e;
92 unsigned char dummy_3f;
93 unsigned char isacsx_cda10;
94 unsigned char isacsx_cda11;
95 unsigned char isacsx_cda20;
96 unsigned char isacsx_cda21;
97 unsigned char isacsx_cda_tsdp10;
98 unsigned char isacsx_cda_tsdp11;
99 unsigned char isacsx_cda_tsdp20;
100 unsigned char isacsx_cda_tsdp21;
101 unsigned char dummy_48;
102 unsigned char dummy_49;
103 unsigned char dummy_4a;
104 unsigned char dummy_4b;
105 unsigned char isacsx_tr_tsdp_bc1;
106 unsigned char isacsx_tr_tsdp_bc2;
107 unsigned char isacsx_cda1_cr;
108 unsigned char isacsx_cda2_cr;
109 unsigned char isacsx_tr_cr;
110 unsigned char dummy_51;
111 unsigned char dummy_52;
112 unsigned char isacsx_dci_cr;
113 unsigned char isacsx_mon_cr;
114 unsigned char isacsx_sds_cr;
115 unsigned char dummy_56;
116 unsigned char isacsx_iom_cr;
117 unsigned char isacsx_sti;
118 unsigned char isacsx_msti;
119 unsigned char isacsx_sds_conf;
120 unsigned char isacsx_mcda;
121 unsigned char isacsx_mor;
122 unsigned char isacsx_mosr;
123 unsigned char isacsx_mocr;
124 unsigned char isacsx_msta;
125 unsigned char isacsx_ista;
126 unsigned char isacsx_auxi;
127 unsigned char isacsx_mode1;
128 unsigned char isacsx_mode2;
129 unsigned char isacsx_id;
130 unsigned char isacsx_timr2;
131 unsigned char dummy_66;
132 unsigned char dummy_67;
133 unsigned char dummy_68;
134 unsigned char dummy_69;
135 unsigned char dummy_6a;
136 unsigned char dummy_6b;
137 unsigned char dummy_6c;
138 unsigned char dummy_6d;
139 unsigned char dummy_6e;
140 unsigned char dummy_6f;
143 unsigned char isacsx_maskd;
144 unsigned char isacsx_cmdrd;
145 unsigned char isacsx_moded;
146 unsigned char isacsx_exmd1;
147 unsigned char isacsx_timr1;
148 unsigned char isacsx_sap1;
149 unsigned char isacsx_sap2;
150 unsigned char isacsx_tei1;
151 unsigned char isacsx_tei2;
152 unsigned char isacsx_tmd;
153 unsigned char dummy_2a;
154 unsigned char dummy_2b;
155 unsigned char dummy_2c;
156 unsigned char dummy_2d;
157 unsigned char isacsx_cix0;
158 unsigned char isacsx_codx1;
159 unsigned char isacsx_tr_conf0;
160 unsigned char isacsx_tr_conf1;
161 unsigned char isacsx_tr_conf2;
162 unsigned char dummy_33;
163 unsigned char dummy_34;
164 unsigned char isacsx_sqrx1;
165 unsigned char dummy_36;
166 unsigned char dummy_37;
167 unsigned char dummy_38;
168 unsigned char isacsx_masktr;
169 unsigned char dummy_3a;
170 unsigned char dummy_3b;
171 unsigned char isacsx_acgf2;
172 unsigned char dummy_3d;
173 unsigned char dummy_3e;
174 unsigned char dummy_3f;
175 unsigned char isacsx_cda10;
176 unsigned char isacsx_cda11;
177 unsigned char isacsx_cda20;
178 unsigned char isacsx_cda21;
179 unsigned char isacsx_cda_tsdp10;
180 unsigned char isacsx_cda_tsdp11;
181 unsigned char isacsx_cda_tsdp20;
182 unsigned char isacsx_cda_tsdp21;
183 unsigned char dummy_48;
184 unsigned char dummy_49;
185 unsigned char dummy_4a;
186 unsigned char dummy_4b;
187 unsigned char isacsx_tr_tsdp_bc1;
188 unsigned char isacsx_tr_tsdp_bc2;
189 unsigned char isacsx_cda1_cr;
190 unsigned char isacsx_cda2_cr;
191 unsigned char isacsx_tr_cr;
192 unsigned char dummy_51;
193 unsigned char dummy_52;
194 unsigned char isacsx_dci_cr;
195 unsigned char isacsx_mon_cr;
196 unsigned char isacsx_sds_cr;
197 unsigned char dummy_56;
198 unsigned char isacsx_iom_cr;
199 unsigned char isacsx_asti;
200 unsigned char isacsx_msti;
201 unsigned char isacsx_sds_conf;
202 unsigned char dummy_5b;
203 unsigned char isacsx_mox;
204 unsigned char dummy_5d;
205 unsigned char isacsx_mocr;
206 unsigned char isacsx_mconf;
207 unsigned char isacsx_mask;
208 unsigned char isacsx_auxm;
209 unsigned char isacsx_mode1;
210 unsigned char isacsx_mode2;
211 unsigned char isacsx_sres;
212 unsigned char isacsx_timr2;
213 unsigned char dummy_66;
214 unsigned char dummy_67;
215 unsigned char dummy_68;
216 unsigned char dummy_69;
217 unsigned char dummy_6a;
218 unsigned char dummy_6b;
219 unsigned char dummy_6c;
220 unsigned char dummy_6d;
221 unsigned char dummy_6e;
222 unsigned char dummy_6f;
227 #define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
229 /* ISACSX read registers */
231 #define i_istad isacsx_rw.isacsx_r.isacsx_istad
232 #define I_ISTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istad)
233 #define i_stard isacsx_rw.isacsx_r.isacsx_stard
234 #define I_STARD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_stard)
235 #define i_rmoded isacsx_rw.isacsx_r.isacsx_moded
236 #define I_RMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_moded)
237 #define i_rexmd1 isacsx_rw.isacsx_r.isacsx_exmd1
238 #define I_REXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_exmd1)
239 #define i_rtimr1 isacsx_rw.isacsx_r.isacsx_timr1
240 #define I_RTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr1)
241 #define i_rbcld isacsx_rw.isacsx_r.isacsx_rbcld
242 #define I_RBCLD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbcld)
243 #define i_rbchd isacsx_rw.isacsx_r.isacsx_rbchd
244 #define I_RBCHD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbchd)
245 #define i_rstad isacsx_rw.isacsx_r.isacsx_rstad
246 #define I_RSTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rstad)
247 #define i_rtmd isacsx_rw.isacsx_r.isacsx_tmd
248 #define I_RTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tmd)
249 #define i_cir0 isacsx_rw.isacsx_r.isacsx_cir0
250 #define I_CIR0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cir0)
251 #define i_codr1 isacsx_rw.isacsx_r.isacsx_codr1
252 #define I_CODR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_codr1)
253 #define i_rtr_conf0 isacsx_rw.isacsx_r.isacsx_tr_conf0
254 #define I_RTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf0)
255 #define i_rtr_conf1 isacsx_rw.isacsx_r.isacsx_tr_conf1
256 #define I_RTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf1)
257 #define i_rtr_conf2 isacsx_rw.isacsx_r.isacsx_tr_conf2
258 #define I_RTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf2)
259 #define i_sta isacsx_rw.isacsx_r.isacsx_sta
260 #define I_STA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sta)
261 #define i_sqrr1 isacsx_rw.isacsx_r.isacsx_sqrr1
262 #define I_SQRR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr1)
263 #define i_sqrr2 isacsx_rw.isacsx_r.isacsx_sqrr2
264 #define I_SQRR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr2)
265 #define i_sqrr3 isacsx_rw.isacsx_r.isacsx_sqrr3
266 #define I_SQRR3 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr3)
267 #define i_istatr isacsx_rw.isacsx_r.isacsx_istatr
268 #define I_ISTATR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istatr)
269 #define i_rmasktr isacsx_rw.isacsx_r.isacsx_masktr
270 #define I_RMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_masktr)
271 #define i_racgf2 isacsx_rw.isacsx_r.isacsx_acgf2
272 #define I_RACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_acgf2)
273 #define i_rcda10 isacsx_rw.isacsx_r.isacsx_cda10
274 #define I_RCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda10)
275 #define i_rcda11 isacsx_rw.isacsx_r.isacsx_cda11
276 #define I_RCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
277 #define i_rcda20 isacsx_rw.isacsx_r.isacsx_cda20
278 #define I_RCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
279 #define i_rcda21 isacsx_rw.isacsx_r.isacsx_cda21
280 #define I_RCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
281 #define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
282 #define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
283 #define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
284 #define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
285 #define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
286 #define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
287 #define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
288 #define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
289 #define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
290 #define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
291 #define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
292 #define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
293 #define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
294 #define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
295 #define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
296 #define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
297 #define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
298 #define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
299 #define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
300 #define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
301 #define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
302 #define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
303 #define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
304 #define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
305 #define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
306 #define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
307 #define i_sti isacsx_rw.isacsx_r.isacsx_sti
308 #define I_STI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sti)
309 #define i_msti isacsx_rw.isacsx_r.isacsx_msti
310 #define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
311 #define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
312 #define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
313 #define i_mcda isacsx_rw.isacsx_r.isacsx_mcda
314 #define I_MCDA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mcda)
315 #define i_mor isacsx_rw.isacsx_r.isacsx_mor
316 #define I_MOR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mor)
317 #define i_mosr isacsx_rw.isacsx_r.isacsx_mosr
318 #define I_MOSR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mosr)
319 #define i_rmocr isacsx_rw.isacsx_r.isacsx_mocr
320 #define I_RMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mocr)
321 #define i_msta isacsx_rw.isacsx_r.isacsx_msta
322 #define I_MSTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msta)
323 #define i_ista isacsx_rw.isacsx_r.isacsx_ista
324 #define I_ISTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_ista)
325 #define i_auxi isacsx_rw.isacsx_r.isacsx_auxi
326 #define I_AUXI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_auxi)
327 #define i_rmode1 isacsx_rw.isacsx_r.isacsx_mode1
328 #define I_RMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode1)
329 #define i_rmode2 isacsx_rw.isacsx_r.isacsx_mode2
330 #define I_RMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode2)
331 #define i_id isacsx_rw.isacsx_r.isacsx_id
332 #define I_ID REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_id)
333 #define i_rtimr2 isacsx_rw.isacsx_r.isacsx_timr2
334 #define I_RTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr2)
336 /* ISAC write registers - isacsx_mode, isacsx_timr, isacsx_star2, isacsx_spcr, */
337 /* isacsx_c1r, isacsx_c2r, isacsx_adf2 see read registers */
339 #define i_maskd isacsx_rw.isacsx_w.isacsx_maskd
340 #define I_MASKD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_maskd)
341 #define i_cmdrd isacsx_rw.isacsx_w.isacsx_cmdrd
342 #define I_CMDRD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cmdrd)
343 #define i_wmoded isacsx_rw.isacsx_w.isacsx_moded
344 #define I_WMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_moded)
345 #define i_wexmd1 isacsx_rw.isacsx_w.isacsx_exmd1
346 #define I_WEXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_exmd1)
347 #define i_wtimr1 isacsx_rw.isacsx_w.isacsx_timr1
348 #define I_WTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr1)
349 #define i_sap1 isacsx_rw.isacsx_w.isacsx_sap1
350 #define I_SAP1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap1)
351 #define i_sap2 isacsx_rw.isacsx_w.isacsx_sap2
352 #define I_SAP2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap2)
353 #define i_tei1 isacsx_rw.isacsx_w.isacsx_tei1
354 #define i_tei2 isacsx_rw.isacsx_w.isacsx_tei2
355 #define i_wtmd isacsx_rw.isacsx_w.isacsx_tmd
356 #define I_WTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tmd)
357 #define i_cix0 isacsx_rw.isacsx_w.isacsx_cix0
358 #define I_CIX0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cix0)
359 #define i_codx1 isacsx_rw.isacsx_w.isacsx_codx1
360 #define I_CODX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_codx1)
361 #define i_wtr_conf0 isacsx_rw.isacsx_w.isacsx_tr_conf0
362 #define I_WTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf0)
363 #define i_wtr_conf1 isacsx_rw.isacsx_w.isacsx_tr_conf1
364 #define I_WTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf1)
365 #define i_wtr_conf2 isacsx_rw.isacsx_w.isacsx_tr_conf2
366 #define I_WTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf2)
367 #define i_sqrx1 isacsx_rw.isacsx_w.isacsx_sqrx1
368 #define I_SQRX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sqrx1)
369 #define i_wmasktr isacsx_rw.isacsx_w.isacsx_masktr
370 #define I_WMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_masktr)
371 #define i_wacgf2 isacsx_rw.isacsx_w.isacsx_acgf2
372 #define I_WACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_acgf2)
373 #define i_wcda10 isacsx_rw.isacsx_w.isacsx_cda10
374 #define I_WCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cda10)
375 #define i_wcda11 isacsx_rw.isacsx_r.isacsx_cda11
376 #define I_WCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
377 #define i_wcda20 isacsx_rw.isacsx_r.isacsx_cda20
378 #define I_WCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
379 #define i_wcda21 isacsx_rw.isacsx_r.isacsx_cda21
380 #define I_WCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
381 #define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
382 #define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
383 #define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
384 #define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
385 #define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
386 #define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
387 #define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
388 #define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
389 #define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
390 #define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
391 #define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
392 #define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
393 #define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
394 #define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
395 #define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
396 #define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
397 #define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
398 #define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
399 #define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
400 #define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
401 #define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
402 #define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
403 #define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
404 #define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
405 #define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
406 #define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
407 #define i_asti isacsx_rw.isacsx_r.isacsx_asti
408 #define I_ASTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_asti)
409 #define i_msti isacsx_rw.isacsx_r.isacsx_msti
410 #define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
411 #define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
412 #define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
413 #define i_mox isacsx_rw.isacsx_w.isacsx_mox
414 #define I_MOX REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mox)
415 #define i_wmocr isacsx_rw.isacsx_w.isacsx_mocr
416 #define I_WMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mocr)
417 #define i_mconf isacsx_rw.isacsx_w.isacsx_mconf
418 #define I_MCONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mconf)
419 #define i_mask isacsx_rw.isacsx_w.isacsx_mask
420 #define I_MASK REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mask)
421 #define i_auxm isacsx_rw.isacsx_w.isacsx_auxm
422 #define I_AUXM REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_auxm)
423 #define i_wmode1 isacsx_rw.isacsx_w.isacsx_mode1
424 #define I_WMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode1)
425 #define i_wmode2 isacsx_rw.isacsx_w.isacsx_mode2
426 #define I_WMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode2)
427 #define i_sres isacsx_rw.isacsx_w.isacsx_sres
428 #define I_SRES REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sres)
429 #define i_wtimr2 isacsx_rw.isacsx_w.isacsx_timr2
430 #define I_WTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr2)
432 #define ISACSX_ISTAD_RME 0x80
433 #define ISACSX_ISTAD_RPF 0x40
434 #define ISACSX_ISTAD_RFO 0x20
435 #define ISACSX_ISTAD_XPR 0x10
436 #define ISACSX_ISTAD_XMR 0x08
437 #define ISACSX_ISTAD_XDU 0x04
439 #define ISACSX_MASKD_RME 0x80
440 #define ISACSX_MASKD_RPF 0x40
441 #define ISACSX_MASKD_RFO 0x20
442 #define ISACSX_MASKD_XPR 0x10
443 #define ISACSX_MASKD_XMR 0x08
444 #define ISACSX_MASKD_XDU 0x04
445 /* these must always be set */
446 #define ISACSX_MASKD_LOW 0x03
447 #define ISACSX_MASKD_ALL 0xff
449 #define ISACSX_STARD_XDOV 0x80
450 #define ISACSX_STARD_XFW 0x40
451 #define ISACSX_STARD_RAC1 0x08
452 #define ISACSX_STARD_XAC1 0x02
454 #define ISACSX_CMDRD_RMC 0x80
455 #define ISACSX_CMDRD_RRES 0x40
456 #define ISACSX_CMDRD_STI 0x10
457 #define ISACSX_CMDRD_XTF 0x08
458 #define ISACSX_CMDRD_XME 0x02
459 #define ISACSX_CMDRD_XRES 0x01
461 #define ISACSX_MODED_MDS2 0x80
462 #define ISACSX_MODED_MDS1 0x40
463 #define ISACSX_MODED_MDS0 0x20
464 #define ISACSX_MODED_RAC 0x08
465 #define ISACSX_MODED_DIM2 0x04
466 #define ISACSX_MODED_DIM1 0x02
467 #define ISACSX_MODED_DIM0 0x01
470 #define ISACSX_EXMD1_XFBS_32 0x00 /* XFIFO is 32 bytes */
471 #define ISACSX_EXMD1_XFBS_16 0x80 /* XFIFO is 16 bytes */
473 #define ISACSX_EXMD1_RFBS_32 0x00 /* XFIFO is 32 bytes */
474 #define ISACSX_EXMD1_RFBS_16 0x20 /* XFIFO is 16 bytes */
475 #define ISACSX_EXMD1_RFBS_08 0x40 /* XFIFO is 8 bytes */
476 #define ISACSX_EXMD1_RFBS_04 0x60 /* XFIFO is 4 bytes */
477 #define ISACSX_EXMD1_SRA 0x10
478 #define ISACSX_EXMD1_XCRC 0x08
479 #define ISACSX_EXMD1_RCRC 0x04
480 #define ISACSX_EXMD1_ITF 0x01
482 #define ISACSX_RSTAD_VFR 0x80
483 #define ISACSX_RSTAD_RDO 0x40
484 #define ISACSX_RSTAD_CRC 0x20
485 #define ISACSX_RSTAD_RAB 0x10
486 #define ISACSX_RSTAD_SA1 0x08
487 #define ISACSX_RSTAD_SA0 0x04
488 #define ISACSX_RSTAD_CR 0x02
489 #define ISACSX_RSTAD_TA 0x01
491 #define ISACSX_RSTAD_MASK 0xf0 /* the interesting bits */
493 #define ISACSX_RBCHD_OV 0x10
494 /* the other 4 bits are the high bits of the receive byte count */
496 #define ISACSX_CIR0_CIC0 0x08
498 #define ISACSX_CIR0_IPU 0x07
499 #define ISACSX_CIR0_IDR 0x00
500 #define ISACSX_CIR0_ISD 0x02
501 #define ISACSX_CIR0_IDIS 0x03
502 #define ISACSX_CIR0_IEI 0x06
503 #define ISACSX_CIR0_IRSY 0x04
504 #define ISACSX_CIR0_IARD 0x08
505 #define ISACSX_CIR0_ITI 0x0a
506 #define ISACSX_CIR0_IATI 0x0b
507 #define ISACSX_CIR0_IAI8 0x0c
508 #define ISACSX_CIR0_IAI10 0x0d
509 #define ISACSX_CIR0_IDID 0x0f
511 #define ISACSX_IOM_CR_SPU 0x80
512 #define ISACSX_IOM_CR_CI_CS 0x20
513 #define ISACSX_IOM_CR_TIC_DIS 0x10
514 #define ISACSX_IOM_CR_EN_BCL 0x08
515 #define ISACSX_IOM_CR_CLKM 0x04
516 #define ISACSX_IOM_CR_DIS_OD 0x02
517 #define ISACSX_IOM_CR_DIS_IOM 0x01
519 #define ISACSX_CI_MASK 0x0f
521 #define ISACSX_CIX0_BAC 0x01
522 /* in IOM-2 mode the low bits are always 1 */
523 #define ISACSX_CIX0_LOW 0x0e
524 /* C/I codes from bits 7-4 (>> 4 & 0xf) */
526 #define ISACSX_CIX0_CTIM 0
527 #define ISACSX_CIX0_CRS 0x01
529 #define ISACSX_CIX0_CSSSP 0x02
531 #define ISACSX_CIX0_CSSCP 0x03
532 #define ISACSX_CIX0_CAR8 0x08
533 #define ISACSX_CIX0_CAR10 0x09
534 #define ISACSX_CIX0_CARL 0x0a
535 #define ISACSX_CIX0_CDIU 0x0f
537 /* Interrupt, General Configuration Registers */
539 #define ISACSX_ISTA_ST 0x20
540 #define ISACSX_ISTA_CIC 0x10
541 #define ISACSX_ISTA_AUX 0x08
542 #define ISACSX_ISTA_TRAN 0x04
543 #define ISACSX_ISTA_MOS 0x02
544 #define ISACSX_ISTA_ICD 0x01
546 #define ISACSX_MASK_ST 0x20
547 #define ISACSX_MASK_CIC 0x10
548 #define ISACSX_MASK_AUX 0x08
549 #define ISACSX_MASK_TRAN 0x04
550 #define ISACSX_MASK_MOS 0x02
551 #define ISACSX_MASK_ICD 0x01
553 #define ISACSX_AUXI_EAW 0x20
554 #define ISACSX_AUXI_WOV 0x10
555 #define ISACSX_AUXI_TIN2 0x08
556 #define ISACSX_AUXI_TIN1 0x04
558 #define ISACSX_AUXM_EAW 0x20
559 #define ISACSX_AUXM_WOV 0x10
560 #define ISACSX_AUXM_TIN2 0x08
561 #define ISACSX_AUXM_TIN1 0x04
563 #define ISACSX_MODE1_WTC1 0x10
564 #define ISACSX_MODE1_WTC2 0x08
565 #define ISACSX_MODE1_CFS 0x04
566 #define ISACSX_MODE1_RSS2 0x02
567 #define ISACSX_MODE1_RSS1 0x01
569 #define ISACSX_MODE2_INT_POL 0x08
570 #define ISACSX_MODE2_PPSDX 0x01
572 #define ISACSX_ID_MASK 0x2F /* 0x01 = Version 1.3 */
574 #endif /* I4B_ISACSX_H_ */