sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c

   1 /*-
   2  *   Copyright (c) 2001 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  */
  31
  32 /*---------------------------------------------------------------------------
  33  *
  34  *      i4b_ifpi2_pci.c: AVM Fritz!Card PCI hardware driver
  35  *      --------------------------------------------------
  36  *      $Id$
  37  *
  38  *---------------------------------------------------------------------------*/
  39
  40 #include <sys/cdefs.h>
  41 __FBSDID("$FreeBSD$");
  42
  43 #include "opt_i4b.h"
  44
  45 #include <sys/param.h>
  46 #include <sys/kernel.h>
  47 #include <sys/systm.h>
  48 #include <sys/mbuf.h>
  49
  50 #include <machine/bus.h>
  51 #include <sys/bus.h>
  52 #include <sys/rman.h>
  53
  54 #include <dev/pci/pcireg.h>
  55 #include <dev/pci/pcivar.h>
  56
  57 #include <sys/socket.h>
  58 #include <net/if.h>
  59
  60 #include <i4b/include/i4b_debug.h>
  61 #include <i4b/include/i4b_ioctl.h>
  62 #include <i4b/include/i4b_trace.h>
  63
  64 #include <i4b/include/i4b_global.h>
  65 #include <i4b/include/i4b_mbuf.h>
  66
  67 #include <i4b/layer1/i4b_l1.h>
  68 #include <i4b/layer1/isic/i4b_isic.h>
  69 /*#include <i4b/layer1/isic/i4b_isac.h>*/
  70 #include <i4b/layer1/isic/i4b_hscx.h>
  71
  72 #include <i4b/layer1/ifpi2/i4b_ifpi2_ext.h>
  73 #include <i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h>
  74
  75 #define PCI_AVMA1_VID 0x1244
  76 #define PCI_AVMA1_V2_DID 0x0e00
  77
  78 /* prototypes */
  79 static void avma1pp2_disable(device_t);
  80 static void avma1pp2_intr(void *);
  81 static void hscx_write_reg(int, u_int, struct l1_softc *);
  82 static u_char hscx_read_reg(int, struct l1_softc *);
  83 static u_int hscx_read_reg_int(int, struct l1_softc *);
  84 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  85 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  86 static void avma1pp2_hscx_int_handler(struct l1_softc *);
  87 static void avma1pp2_hscx_intr(int, u_int, struct l1_softc *);
  88 static void avma1pp2_init_linktab(struct l1_softc *);
  89 static void avma1pp2_bchannel_setup(int, int, int, int);
  90 static void avma1pp2_bchannel_start(int, int);
  91 static void avma1pp2_hscx_init(struct l1_softc *, int, int);
  92 static void avma1pp2_bchannel_stat(int, int, bchan_statistics_t *);
  93 static void avma1pp2_set_linktab(int, int, drvr_link_t *);
  94 static isdn_link_t * avma1pp2_ret_linktab(int, int);
  95 static int avma1pp2_pci_probe(device_t);
  96 static int avma1pp2_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
  97 int avma1pp2_attach_avma1pp(device_t);
  98 static void ifpi2_isacsx_intr(struct l1_softc *sc);
  99
 100 static device_method_t avma1pp2_pci_methods[] = {
 101         /* Device interface */
 102         DEVMETHOD(device_probe,         avma1pp2_pci_probe),
 103         DEVMETHOD(device_attach,        avma1pp2_attach_avma1pp),
 104         DEVMETHOD(device_shutdown,      avma1pp2_disable),
 105
 106         /* bus interface */
 107         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 108         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 109
 110         { 0, 0 }
 111 };
 112
 113 static driver_t avma1pp2_pci_driver = {
 114         "ifpi2-",
 115         avma1pp2_pci_methods,
 116         sizeof(struct l1_softc)
 117 };
 118
 119 static devclass_t avma1pp2_pci_devclass;
 120
 121 DRIVER_MODULE(avma1pp2, pci, avma1pp2_pci_driver, avma1pp2_pci_devclass, 0, 0);
 122
 123 /* jump table for multiplex routines */
 124
 125 struct i4b_l1mux_func avma1pp2_l1mux_func = {
 126         avma1pp2_ret_linktab,
 127         avma1pp2_set_linktab,
 128         ifpi2_mph_command_req,
 129         ifpi2_ph_data_req,
 130         ifpi2_ph_activate_req,
 131 };
 132
 133 struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
 134
 135 /*---------------------------------------------------------------------------*
 136  *      AVM PCI Fritz!Card V. 2 special registers
 137  *---------------------------------------------------------------------------*/
 138
 139 /*
 140  *      AVM PCI Status Latch 0 read only bits
 141  */
 142 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active high */
 143 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active high */
 144 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active high */
 145 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 146 /* actually active high */
 147 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 148
 149 /*
 150  *      AVM PCI Status Latch 0 read only bits
 151  */
 152 #define ASL_RESET               0x01
 153 #define ASL_TIMERRESET          0x04
 154 #define ASL_ENABLE_INT          0x08
 155
 156 /*
 157  * "HSCX" status bits
 158  */
 159 #define  HSCX_STAT_RME          0x01
 160 #define  HSCX_STAT_RDO          0x10
 161 #define  HSCX_STAT_CRCVFRRAB    0x0E
 162 #define  HSCX_STAT_CRCVFR       0x06
 163 #define  HSCX_STAT_RML_MASK     0x3f00
 164
 165 /*
 166  * "HSCX" interrupt bits
 167  */
 168 #define  HSCX_INT_XPR           0x80
 169 #define  HSCX_INT_XDU           0x40
 170 #define  HSCX_INT_RPR           0x20
 171 #define  HSCX_INT_MASK          0xE0
 172
 173 /*
 174  * "HSCX" command bits
 175  */
 176 #define  HSCX_CMD_XRS           0x80
 177 #define  HSCX_CMD_XME           0x01
 178 #define  HSCX_CMD_RRS           0x20
 179 #define  HSCX_CMD_XML_MASK      0x3f00
 180
 181 /* "HSCX" mode bits */
 182 #define HSCX_MODE_ITF_FLG       0x01
 183 #define HSCX_MODE_TRANS         0x02
 184
 185 /* offsets to various registers in the ASIC, evidently */
 186 #define  STAT0_OFFSET           0x02
 187
 188 #define  HSCX_FIFO1             0x10
 189 #define  HSCX_FIFO2             0x18
 190
 191 #define  HSCX_STAT1             0x14
 192 #define  HSCX_STAT2             0x1c
 193
 194 #define  ISACSX_INDEX           0x04
 195 #define  ISACSX_DATA            0x08
 196
 197 /*
 198  * Commands and parameters are sent to the "HSCX" as a long, but the
 199  * fields are handled as bytes.
 200  *
 201  * The long contains:
 202  *      (prot << 16)|(txl << 8)|cmd
 203  *
 204  * where:
 205  *      prot = protocol to use
 206  *      txl = transmit length
 207  *      cmd = the command to be executed
 208  *
 209  * The fields are defined as u_char in struct l1_softc.
 210  *
 211  * Macro to coalesce the byte fields into a u_int
 212  */
 213 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 214                                         | (sc->avma1pp_prot << 16))
 215
 216 /*
 217  * to prevent deactivating the "HSCX" when both channels are active we
 218  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 219  * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
 220  * It is set high to allow room for new flags.
 221  */
 222 #define HSCX_AVMA1PP_ACTIVE     0x1000
 223
 224 /*---------------------------------------------------------------------------*
 225  *      AVM read fifo routines
 226  *---------------------------------------------------------------------------*/
 227
 228 static void
 229 avma1pp2_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 230 {
 231         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 232         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 233         int i;
 234
 235         switch (what) {
 236                 case ISIC_WHAT_ISAC:
 237                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
 238                         /* evidently each byte must be read as a long */
 239                         for (i = 0; i < size; i++)
 240                                 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 241                         break;
 242                 case ISIC_WHAT_HSCXA:
 243                         hscx_read_fifo(0, buf, size, sc);
 244                         break;
 245                 case ISIC_WHAT_HSCXB:
 246                         hscx_read_fifo(1, buf, size, sc);
 247                         break;
 248         }
 249 }
 250
 251 static void
 252 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 253 {
 254         u_int32_t *ip;
 255         size_t cnt;
 256         int dataoff;
 257         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 258         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 259
 260         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 261
 262         ip = (u_int32_t *)buf;
 263         cnt = 0;
 264         /* what if len isn't a multiple of sizeof(int) and buf is */
 265         /* too small ???? */
 266         while (cnt < len)
 267         {
 268                 *ip++ = bus_space_read_4(btag, bhandle, dataoff);
 269                 cnt += 4;
 270         }
 271 }
 272
 273 /*---------------------------------------------------------------------------*
 274  *      AVM write fifo routines
 275  *---------------------------------------------------------------------------*/
 276 static void
 277 avma1pp2_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 278 {
 279         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 280         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 281         int i;
 282
 283         switch (what) {
 284                 case ISIC_WHAT_ISAC:
 285                         bus_space_write_4(btag, bhandle,  ISACSX_INDEX, 0);
 286                         /* evidently each byte must written as a long */
 287                         for (i = 0; i < size; i++)
 288                                 bus_space_write_4(btag, bhandle,  ISACSX_DATA, ((unsigned char *)buf)[i]);
 289                         break;
 290                 case ISIC_WHAT_HSCXA:
 291                         hscx_write_fifo(0, buf, size, sc);
 292                         break;
 293                 case ISIC_WHAT_HSCXB:
 294                         hscx_write_fifo(1, buf, size, sc);
 295                         break;
 296         }
 297 }
 298
 299 static void
 300 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 301 {
 302         u_int32_t *ip;
 303         size_t cnt;
 304         int dataoff;
 305         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 306         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 307         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 308
 309         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 310
 311         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 312         sc->avma1pp_txl = 0;
 313         if (Bchan->out_mbuf_cur == NULL)
 314         {
 315           if (Bchan->bprot != BPROT_NONE)
 316                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 317         }
 318         if (len != sc->sc_bfifolen)
 319                 sc->avma1pp_txl = len;
 320
 321         cnt = 0; /* borrow cnt */
 322         AVMA1PPSETCMDLONG(cnt);
 323         hscx_write_reg(chan, cnt, sc);
 324
 325         ip = (u_int32_t *)buf;
 326         cnt = 0;
 327         while (cnt < len)
 328         {
 329                 bus_space_write_4(btag, bhandle, dataoff, *ip);
 330                 ip++;
 331                 cnt += 4;
 332         }
 333 }
 334
 335 /*---------------------------------------------------------------------------*
 336  *      AVM write register routines
 337  *---------------------------------------------------------------------------*/
 338
 339 static void
 340 avma1pp2_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 341 {
 342         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 343         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 344
 345         switch (what) {
 346                 case ISIC_WHAT_ISAC:
 347                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 348                         bus_space_write_4(btag, bhandle, ISACSX_DATA, data);
 349                         break;
 350                 case ISIC_WHAT_HSCXA:
 351                         hscx_write_reg(0, data, sc);
 352                         break;
 353                 case ISIC_WHAT_HSCXB:
 354                         hscx_write_reg(1, data, sc);
 355                         break;
 356         }
 357 }
 358
 359 static void
 360 hscx_write_reg(int chan, u_int val, struct l1_softc *sc)
 361 {
 362         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 363         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 364         u_int off;
 365
 366         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 367
 368         bus_space_write_4(btag, bhandle, off, val);
 369 }
 370
 371 /*---------------------------------------------------------------------------*
 372  *      AVM read register routines
 373  *---------------------------------------------------------------------------*/
 374 static u_int8_t
 375 avma1pp2_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 376 {
 377         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 378         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 379         u_int8_t val;
 380
 381         switch (what) {
 382                 case ISIC_WHAT_ISAC:
 383                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 384                         val = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 385                         return(val);
 386                 case ISIC_WHAT_HSCXA:
 387                         return hscx_read_reg(0, sc);
 388                 case ISIC_WHAT_HSCXB:
 389                         return hscx_read_reg(1, sc);
 390         }
 391         return 0;
 392 }
 393
 394 static u_char
 395 hscx_read_reg(int chan, struct l1_softc *sc)
 396 {
 397         return(hscx_read_reg_int(chan, sc) & 0xff);
 398 }
 399
 400 /*
 401  * need to be able to return an int because the RBCH is in the 2nd
 402  * byte.
 403  */
 404 static u_int
 405 hscx_read_reg_int(int chan, struct l1_softc *sc)
 406 {
 407         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 408         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 409         u_int off;
 410
 411         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 412         return(bus_space_read_4(btag, bhandle, off));
 413 }
 414
 415 /*---------------------------------------------------------------------------*
 416  *      avma1pp2_probe - probe for a card
 417  *---------------------------------------------------------------------------*/
 418 static int
 419 avma1pp2_pci_probe(dev)
 420         device_t                dev;
 421 {
 422         u_int16_t               did, vid;
 423
 424         vid = pci_get_vendor(dev);
 425         did = pci_get_device(dev);
 426
 427         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_V2_DID)) {
 428                 device_set_desc(dev, "AVM Fritz!Card PCI Version 2");
 429                 return(0);
 430         }
 431
 432         return(ENXIO);
 433 }
 434
 435 /*---------------------------------------------------------------------------*
 436  *      avma1pp2_attach_avma1pp - attach Fritz!Card PCI
 437  *---------------------------------------------------------------------------*/
 438 int
 439 avma1pp2_attach_avma1pp(device_t dev)
 440 {
 441         struct l1_softc *sc;
 442         u_int v;
 443         int unit, error = 0;
 444         int s;
 445         u_int16_t did, vid;
 446         void *ih = 0;
 447         bus_space_handle_t bhandle;
 448         bus_space_tag_t btag;
 449         l1_bchan_state_t *chan;
 450
 451         s = splimp();
 452
 453         vid = pci_get_vendor(dev);
 454         did = pci_get_device(dev);
 455         sc = device_get_softc(dev);
 456         unit = device_get_unit(dev);
 457         bzero(sc, sizeof(struct l1_softc));
 458
 459         /* probably not really required */
 460         if(unit >= IFPI2_MAXUNIT) {
 461                 printf("ifpi2-%d: Error, unit >= IFPI_MAXUNIT!\n", unit);
 462                 splx(s);
 463                 return(ENXIO);
 464         }
 465
 466         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_V2_DID)) {
 467                 printf("ifpi2-%d: unknown device!?\n", unit);
 468                 goto fail;
 469         }
 470
 471         ifpi2_scp[unit] = sc;
 472
 473         sc->sc_resources.io_rid[0] = PCIR_BAR(1);
 474         sc->sc_resources.io_base[0] = bus_alloc_resource_any(dev,
 475                 SYS_RES_IOPORT, &sc->sc_resources.io_rid[0], RF_ACTIVE);
 476
 477         if (sc->sc_resources.io_base[0] == NULL) {
 478                 printf("ifpi2-%d: couldn't map IO port\n", unit);
 479                 error = ENXIO;
 480                 goto fail;
 481         }
 482
 483         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 484         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 485
 486         /* Allocate interrupt */
 487         sc->sc_resources.irq_rid = 0;
 488         sc->sc_resources.irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 489                 &sc->sc_resources.irq_rid, RF_SHAREABLE | RF_ACTIVE);
 490
 491         if (sc->sc_resources.irq == NULL) {
 492                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(1), sc->sc_resources.io_base[0]);
 493                 printf("ifpi2-%d: couldn't map interrupt\n", unit);
 494                 error = ENXIO;
 495                 goto fail;
 496         }
 497
 498         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET, NULL, avma1pp2_intr, sc, &ih);
 499
 500         if (error) {
 501                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 502                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(1), sc->sc_resources.io_base[0]);
 503                 printf("ifpi2-%d: couldn't set up irq\n", unit);
 504                 goto fail;
 505         }
 506
 507         sc->sc_unit = unit;
 508
 509         /* end of new-bus stuff */
 510
 511         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 512
 513         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 514         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 515
 516         /* setup access routines */
 517
 518         sc->clearirq = NULL;
 519         sc->readreg = avma1pp2_read_reg;
 520         sc->writereg = avma1pp2_write_reg;
 521
 522         sc->readfifo = avma1pp2_read_fifo;
 523         sc->writefifo = avma1pp2_write_fifo;
 524
 525         /* setup card type */
 526
 527         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI_V2;
 528
 529         /* setup IOM bus type */
 530
 531         sc->sc_bustyp = BUS_TYPE_IOM2;
 532
 533         /* set up some other miscellaneous things */
 534         sc->sc_ipac = 0;
 535         sc->sc_bfifolen = HSCX_FIFO_LEN;
 536
 537         /* reset the card */
 538         /* the Linux driver does this to clear any pending ISAC interrupts */
 539         v = 0;
 540         v = ISAC_READ(I_RMODED);
 541 #ifdef AVMA1PCI_V2_DEBUG
 542         printf("avma1pp2_attach: I_MODED %x...", v);
 543 #endif
 544         v = ISAC_READ(I_ISTAD);
 545 #ifdef AVMA1PCI_V2_DEBUG
 546         printf("avma1pp2_attach: I_ISTAD %x...", v);
 547 #endif
 548         v = ISAC_READ(I_ISTA);
 549 #ifdef AVMA1PCI_V2_DEBUG
 550         printf("avma1pp2_attach: I_ISTA %x...", v);
 551 #endif
 552         ISAC_WRITE(I_MASKD, 0xff);
 553         ISAC_WRITE(I_MASK, 0xff);
 554         /* the Linux driver does this to clear any pending HSCX interrupts */
 555         v = hscx_read_reg_int(0, sc);
 556 #ifdef AVMA1PCI_V2_DEBUG
 557         printf("avma1pp2_attach: 0 HSCX_STAT %x...", v);
 558 #endif
 559         v = hscx_read_reg_int(1, sc);
 560 #ifdef AVMA1PCI_V2_DEBUG
 561         printf("avma1pp2_attach: 1 HSCX_STAT %x\n", v);
 562 #endif
 563
 564         bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0);
 565         DELAY(SEC_DELAY/100); /* 10 ms */
 566         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET);
 567         DELAY(SEC_DELAY/100); /* 10 ms */
 568         bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0);
 569         DELAY(SEC_DELAY/100); /* 10 ms */
 570
 571         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET);
 572         DELAY(SEC_DELAY/100); /* 10 ms */
 573         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_ENABLE_INT);
 574         DELAY(SEC_DELAY/100); /* 10 ms */
 575
 576    /* from here to the end would normally be done in isic_pciattach */
 577
 578          printf("ifpi2-%d: ISACSX %s\n", unit, "PSB3186");
 579
 580         /* init the ISAC */
 581         ifpi2_isacsx_init(sc);
 582
 583 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 584         /* Init the channel mutexes */
 585         chan = &sc->sc_chan[HSCX_CH_A];
 586         if(!mtx_initialized(&chan->rx_queue.ifq_mtx))
 587                 mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp2_rx", NULL, MTX_DEF);
 588         if(!mtx_initialized(&chan->tx_queue.ifq_mtx))
 589                 mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp2_tx", NULL, MTX_DEF);
 590         chan = &sc->sc_chan[HSCX_CH_B];
 591         if(!mtx_initialized(&chan->rx_queue.ifq_mtx))
 592                 mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp2_rx", NULL, MTX_DEF);
 593         if(!mtx_initialized(&chan->tx_queue.ifq_mtx))
 594                 mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp2_tx", NULL, MTX_DEF);
 595 #endif
 596
 597         /* init the "HSCX" */
 598         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 599
 600         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 601
 602         /* can't use the normal B-Channel stuff */
 603         avma1pp2_init_linktab(sc);
 604
 605         /* set trace level */
 606
 607         sc->sc_trace = TRACE_OFF;
 608
 609         sc->sc_state = ISAC_IDLE;
 610
 611         sc->sc_ibuf = NULL;
 612         sc->sc_ib = NULL;
 613         sc->sc_ilen = 0;
 614
 615         sc->sc_obuf = NULL;
 616         sc->sc_op = NULL;
 617         sc->sc_ol = 0;
 618         sc->sc_freeflag = 0;
 619
 620         sc->sc_obuf2 = NULL;
 621         sc->sc_freeflag2 = 0;
 622
 623 #if defined(__FreeBSD__) && __FreeBSD__ >=3
 624         callout_handle_init(&sc->sc_T3_callout);
 625         callout_handle_init(&sc->sc_T4_callout);
 626 #endif
 627
 628         /* init higher protocol layers */
 629
 630         i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp2_l1mux_func);
 631
 632   fail:
 633         splx(s);
 634         return(error);
 635 }
 636
 637 /*
 638  * this is the real interrupt routine
 639  */
 640 static void
 641 avma1pp2_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 642 {
 643         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 644         int activity = -1;
 645         u_int param = 0;
 646
 647         NDBGL1(L1_H_IRQ, "%#x", stat);
 648
 649         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 650         {
 651                 chan->stat_XDU++;
 652                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 653                 /* abort the transmission */
 654                 sc->avma1pp_txl = 0;
 655                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 656                 AVMA1PPSETCMDLONG(param);
 657                 hscx_write_reg(h_chan, param, sc);
 658                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 659                 AVMA1PPSETCMDLONG(param);
 660                 hscx_write_reg(h_chan, param, sc);
 661
 662                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 663                 {
 664                         i4b_Bfreembuf(chan->out_mbuf_head);
 665                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 666                 }
 667         }
 668
 669         /*
 670          * The following is based on examination of the Linux driver.
 671          *
 672          * The logic here is different than with a "real" HSCX; all kinds
 673          * of information (interrupt/status bits) are in stat.
 674          *              HSCX_INT_RPR indicates a receive interrupt
 675          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 676          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 677          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 678          *                      CRC/framing errors are only reported in this state.
 679          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 680          *                                      CRC/framing error
 681          */
 682
 683         if(stat & HSCX_INT_RPR)
 684         {
 685                 register int fifo_data_len;
 686                 int error = 0;
 687                 /* always have to read the FIFO, so use a scratch buffer */
 688                 u_char scrbuf[HSCX_FIFO_LEN];
 689
 690                 if(stat & HSCX_STAT_RDO)
 691                 {
 692                         chan->stat_RDO++;
 693                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 694                         error++;
 695                 }
 696
 697                 /*
 698                  * check whether we're receiving data for an inactive B-channel
 699                  * and discard it. This appears to happen for telephony when
 700                  * both B-channels are active and one is deactivated. Since
 701                  * it is not really possible to deactivate the channel in that
 702                  * case (the ASIC seems to deactivate _both_ channels), the
 703                  * "deactivated" channel keeps receiving data which can lead
 704                  * to exhaustion of mbufs and a kernel panic.
 705                  *
 706                  * This is a hack, but it's the only solution I can think of
 707                  * without having the documentation for the ASIC.
 708                  * GJ - 28 Nov 1999
 709                  */
 710                  if (chan->state == HSCX_IDLE)
 711                  {
 712                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 713                         error++;
 714                  }
 715
 716                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 717
 718                 if(fifo_data_len == 0)
 719                         fifo_data_len = sc->sc_bfifolen;
 720
 721                 /* ALWAYS read data from HSCX fifo */
 722
 723                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 724                 chan->rxcount += fifo_data_len;
 725
 726                 /* all error conditions checked, now decide and take action */
 727
 728                 if(error == 0)
 729                 {
 730                         if(chan->in_mbuf == NULL)
 731                         {
 732                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 733                                         panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!\n");
 734                                 chan->in_cbptr = chan->in_mbuf->m_data;
 735                                 chan->in_len = 0;
 736                         }
 737
 738                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 739                         {
 740                                 /* OK to copy the data */
 741                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 742                                 chan->in_cbptr += fifo_data_len;
 743                                 chan->in_len += fifo_data_len;
 744
 745                                 /* setup mbuf data length */
 746
 747                                 chan->in_mbuf->m_len = chan->in_len;
 748                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 749
 750                                 if(sc->sc_trace & TRACE_B_RX)
 751                                 {
 752                                         i4b_trace_hdr_t hdr;
 753                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 754                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 755                                         hdr.dir = FROM_NT;
 756                                         hdr.count = ++sc->sc_trace_bcount;
 757                                         MICROTIME(hdr.time);
 758                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 759                                 }
 760
 761                                 if (stat & HSCX_STAT_RME)
 762                                 {
 763                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 764                                   {
 765                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 766                                          activity = ACT_RX;
 767
 768                                          /* mark buffer ptr as unused */
 769
 770                                          chan->in_mbuf = NULL;
 771                                          chan->in_cbptr = NULL;
 772                                          chan->in_len = 0;
 773                                   }
 774                                   else
 775                                   {
 776                                                 chan->stat_CRC++;
 777                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 778                                           if (chan->in_mbuf != NULL)
 779                                           {
 780                                                   i4b_Bfreembuf(chan->in_mbuf);
 781                                                   chan->in_mbuf = NULL;
 782                                                   chan->in_cbptr = NULL;
 783                                                   chan->in_len = 0;
 784                                           }
 785                                   }
 786                                 }
 787                         } /* END enough space in mbuf */
 788                         else
 789                         {
 790                                  if(chan->bprot == BPROT_NONE)
 791                                  {
 792                                           /* setup mbuf data length */
 793
 794                                           chan->in_mbuf->m_len = chan->in_len;
 795                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 796
 797                                           if(sc->sc_trace & TRACE_B_RX)
 798                                           {
 799                                                         i4b_trace_hdr_t hdr;
 800                                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 801                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 802                                                         hdr.dir = FROM_NT;
 803                                                         hdr.count = ++sc->sc_trace_bcount;
 804                                                         MICROTIME(hdr.time);
 805                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 806                                                 }
 807
 808                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 809                                                  activity = ACT_RX;
 810
 811                                           /* move rx'd data to rx queue */
 812
 813 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 814                                           (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
 815 #else
 816                                           if(!(IF_QFULL(&chan->rx_queue)))
 817                                           {
 818                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 819                                           }
 820                                           else
 821                                           {
 822                                                 i4b_Bfreembuf(chan->in_mbuf);
 823                                           }
 824 #endif
 825                                           /* signal upper layer that data are available */
 826                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 827
 828                                           /* alloc new buffer */
 829
 830                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 831                                                  panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!\n");
 832
 833                                           /* setup new data ptr */
 834
 835                                           chan->in_cbptr = chan->in_mbuf->m_data;
 836
 837                                           /* OK to copy the data */
 838                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 839
 840                                           chan->in_cbptr += fifo_data_len;
 841                                           chan->in_len = fifo_data_len;
 842
 843                                           chan->rxcount += fifo_data_len;
 844                                         }
 845                                  else
 846                                         {
 847                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 848                                           chan->in_cbptr = chan->in_mbuf->m_data;
 849                                           chan->in_len = 0;
 850                                         }
 851                           }
 852                 } /* if(error == 0) */
 853                 else
 854                 {
 855                         /* land here for RDO */
 856                         if (chan->in_mbuf != NULL)
 857                         {
 858                                 i4b_Bfreembuf(chan->in_mbuf);
 859                                 chan->in_mbuf = NULL;
 860                                 chan->in_cbptr = NULL;
 861                                 chan->in_len = 0;
 862                         }
 863                         sc->avma1pp_txl = 0;
 864                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 865                         AVMA1PPSETCMDLONG(param);
 866                         hscx_write_reg(h_chan, param, sc);
 867                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 868                         AVMA1PPSETCMDLONG(param);
 869                         hscx_write_reg(h_chan, param, sc);
 870                 }
 871         }
 872
 873
 874         /* transmit fifo empty, new data can be written to fifo */
 875
 876         if(stat & HSCX_INT_XPR)
 877         {
 878                 /*
 879                  * for a description what is going on here, please have
 880                  * a look at isic_bchannel_start() in i4b_bchan.c !
 881                  */
 882
 883                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 884
 885                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 886                 {
 887                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 888
 889                         if(chan->out_mbuf_head == NULL)
 890                         {
 891                                 chan->state &= ~HSCX_TX_ACTIVE;
 892                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 893                         }
 894                         else
 895                         {
 896                                 chan->state |= HSCX_TX_ACTIVE;
 897                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 898                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 899                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 900
 901                                 if(sc->sc_trace & TRACE_B_TX)
 902                                 {
 903                                         i4b_trace_hdr_t hdr;
 904                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 905                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 906                                         hdr.dir = FROM_TE;
 907                                         hdr.count = ++sc->sc_trace_bcount;
 908                                         MICROTIME(hdr.time);
 909                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 910                                 }
 911
 912                                 if(chan->bprot == BPROT_NONE)
 913                                 {
 914                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 915                                                 activity = ACT_TX;
 916                                 }
 917                                 else
 918                                 {
 919                                         activity = ACT_TX;
 920                                 }
 921                         }
 922                 }
 923
 924                 avma1pp2_hscx_fifo(chan, sc);
 925         }
 926
 927         /* call timeout handling routine */
 928
 929         if(activity == ACT_RX || activity == ACT_TX)
 930                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 931 }
 932
 933 /*
 934  * this is the main routine which checks each channel and then calls
 935  * the real interrupt routine as appropriate
 936  */
 937 static void
 938 avma1pp2_hscx_int_handler(struct l1_softc *sc)
 939 {
 940         u_int stat;
 941
 942         /* has to be a u_int because the byte count is in the 2nd byte */
 943         stat = hscx_read_reg_int(0, sc);
 944         if (stat & HSCX_INT_MASK)
 945           avma1pp2_hscx_intr(0, stat, sc);
 946         stat = hscx_read_reg_int(1, sc);
 947         if (stat & HSCX_INT_MASK)
 948           avma1pp2_hscx_intr(1, stat, sc);
 949 }
 950
 951 static void
 952 avma1pp2_disable(device_t dev)
 953 {
 954         struct l1_softc *sc = device_get_softc(dev);
 955         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 956         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 957
 958         /* could be still be wrong, but seems to prevent hangs */
 959         bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0x00);
 960 }
 961
 962 static void
 963 avma1pp2_intr(void *xsc)
 964 {
 965         u_char stat;
 966         struct l1_softc *sc;
 967         bus_space_handle_t bhandle;
 968         bus_space_tag_t btag;
 969
 970         sc = xsc;
 971         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 972         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 973
 974         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 975         NDBGL1(L1_H_IRQ, "stat %x", stat);
 976         /* was there an interrupt from this card ? */
 977         if ((stat & ASL_IRQ_Pending) == 0)
 978                 return; /* no */
 979         /* For slow machines loop as long as an interrupt is active */
 980         for (; ((stat & ASL_IRQ_Pending) != 0) ;)
 981         {
 982                 /* interrupts are high active */
 983                 if (stat & ASL_IRQ_TIMER)
 984                         NDBGL1(L1_H_IRQ, "timer interrupt ???");
 985                 if (stat & ASL_IRQ_HSCX)
 986                 {
 987                         NDBGL1(L1_H_IRQ, "HSCX");
 988                         avma1pp2_hscx_int_handler(sc);
 989                 }
 990                 if (stat & ASL_IRQ_ISAC)
 991                 {
 992                        NDBGL1(L1_H_IRQ, "ISAC");
 993                        ifpi2_isacsx_intr(sc);
 994                 }
 995                 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 996                 NDBGL1(L1_H_IRQ, "stat %x", stat);
 997
 998         }
 999 }
1000
1001 static void
1002 avma1pp2_hscx_init(struct l1_softc *sc, int h_chan, int activate)
1003 {
1004         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1005         u_int param = 0;
1006
1007         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1008                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1009
1010         sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
1011
1012         if (activate == 0)
1013         {
1014                 /* only deactivate if both channels are idle */
1015                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1016                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1017                 {
1018                         return;
1019                 }
1020                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1021                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1022                 AVMA1PPSETCMDLONG(param);
1023                 hscx_write_reg(h_chan, param, sc);
1024                 return;
1025         }
1026         if(chan->bprot == BPROT_RHDLC)
1027         {
1028                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1029
1030                 /* HDLC Frames, transparent mode 0 */
1031                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1032                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1033                 AVMA1PPSETCMDLONG(param);
1034                 hscx_write_reg(h_chan, param, sc);
1035                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1036                 AVMA1PPSETCMDLONG(param);
1037                 hscx_write_reg(h_chan, param, sc);
1038                 sc->avma1pp_cmd = 0;
1039         }
1040         else
1041         {
1042                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1043
1044                 /* Raw Telephony, extended transparent mode 1 */
1045                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1046                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1047                 AVMA1PPSETCMDLONG(param);
1048                 hscx_write_reg(h_chan, param, sc);
1049                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1050                 AVMA1PPSETCMDLONG(param);
1051                 hscx_write_reg(h_chan, param, sc);
1052                 sc->avma1pp_cmd = 0;
1053         }
1054 }
1055
1056 static void
1057 avma1pp2_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1058 {
1059 #ifdef __FreeBSD__
1060         struct l1_softc *sc = ifpi2_scp[unit];
1061 #else
1062         struct l1_softc *sc = isic_find_sc(unit);
1063 #endif
1064         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1065
1066         int s = SPLI4B();
1067
1068         if(activate == 0)
1069         {
1070                 /* deactivation */
1071                 chan->state = HSCX_IDLE;
1072                 avma1pp2_hscx_init(sc, h_chan, activate);
1073         }
1074
1075         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1076                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1077
1078         /* general part */
1079
1080         chan->unit = sc->sc_unit;       /* unit number */
1081         chan->channel = h_chan;         /* B channel */
1082         chan->bprot = bprot;            /* B channel protocol */
1083         chan->state = HSCX_IDLE;        /* B channel state */
1084
1085         /* receiver part */
1086
1087         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1088
1089         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1090
1091         chan->rxcount = 0;              /* reset rx counter */
1092
1093         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1094
1095         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1096         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1097         chan->in_len = 0;               /* reset mbuf data len */
1098
1099         /* transmitter part */
1100
1101         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1102
1103         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1104
1105         chan->txcount = 0;              /* reset tx counter */
1106
1107         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1108
1109         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1110         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1111         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1112         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1113
1114         if(activate != 0)
1115         {
1116                 /* activation */
1117                 avma1pp2_hscx_init(sc, h_chan, activate);
1118                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1119         }
1120
1121         splx(s);
1122 }
1123
1124 static void
1125 avma1pp2_bchannel_start(int unit, int h_chan)
1126 {
1127 #ifdef __FreeBSD__
1128         struct l1_softc *sc = ifpi2_scp[unit];
1129 #else
1130         struct l1_softc *sc = isic_find_sc(unit);
1131 #endif
1132         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1133         int s;
1134         int activity = -1;
1135
1136         s = SPLI4B();                           /* enter critical section */
1137         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1138         {
1139                 splx(s);
1140                 return;                         /* yes, leave */
1141         }
1142
1143         /* get next mbuf from queue */
1144
1145         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1146
1147         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1148         {
1149                 splx(s);                        /* leave critical section */
1150                 return;                         /* yes, exit */
1151         }
1152
1153         /* init current mbuf values */
1154
1155         chan->out_mbuf_cur = chan->out_mbuf_head;
1156         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1157         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1158
1159         /* activity indicator for timeout handling */
1160
1161         if(chan->bprot == BPROT_NONE)
1162         {
1163                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1164                         activity = ACT_TX;
1165         }
1166         else
1167         {
1168                 activity = ACT_TX;
1169         }
1170
1171         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1172
1173         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1174         {
1175                 i4b_trace_hdr_t hdr;
1176                 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1177                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1178                 hdr.dir = FROM_TE;
1179                 hdr.count = ++sc->sc_trace_bcount;
1180                 MICROTIME(hdr.time);
1181                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1182         }
1183
1184         avma1pp2_hscx_fifo(chan, sc);
1185
1186         /* call timeout handling routine */
1187
1188         if(activity == ACT_RX || activity == ACT_TX)
1189                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1190
1191         splx(s);
1192 }
1193
1194 /*---------------------------------------------------------------------------*
1195  *      return the address of isic drivers linktab
1196  *---------------------------------------------------------------------------*/
1197 static isdn_link_t *
1198 avma1pp2_ret_linktab(int unit, int channel)
1199 {
1200 #ifdef __FreeBSD__
1201         struct l1_softc *sc = ifpi2_scp[unit];
1202 #else
1203         struct l1_softc *sc = isic_find_sc(unit);
1204 #endif
1205         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1206
1207         return(&chan->isic_isdn_linktab);
1208 }
1209
1210 /*---------------------------------------------------------------------------*
1211  *      set the driver linktab in the b channel softc
1212  *---------------------------------------------------------------------------*/
1213 static void
1214 avma1pp2_set_linktab(int unit, int channel, drvr_link_t *dlt)
1215 {
1216 #ifdef __FreeBSD__
1217         struct l1_softc *sc = ifpi2_scp[unit];
1218 #else
1219         struct l1_softc *sc = isic_find_sc(unit);
1220 #endif
1221         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1222
1223         chan->isic_drvr_linktab = dlt;
1224 }
1225
1226
1227 /*---------------------------------------------------------------------------*
1228  *      initialize our local linktab
1229  *---------------------------------------------------------------------------*/
1230 static void
1231 avma1pp2_init_linktab(struct l1_softc *sc)
1232 {
1233         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1234         isdn_link_t *lt = &chan->isic_isdn_linktab;
1235
1236         /* make sure the hardware driver is known to layer 4 */
1237         /* avoid overwriting if already set */
1238         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1239         {
1240                 ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
1241                 ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
1242         }
1243
1244         /* local setup */
1245         lt->unit = sc->sc_unit;
1246         lt->channel = HSCX_CH_A;
1247         lt->bch_config = avma1pp2_bchannel_setup;
1248         lt->bch_tx_start = avma1pp2_bchannel_start;
1249         lt->bch_stat = avma1pp2_bchannel_stat;
1250         lt->tx_queue = &chan->tx_queue;
1251
1252         /* used by non-HDLC data transfers, i.e. telephony drivers */
1253         lt->rx_queue = &chan->rx_queue;
1254
1255         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1256         lt->rx_mbuf = &chan->in_mbuf;
1257
1258         chan = &sc->sc_chan[HSCX_CH_B];
1259         lt = &chan->isic_isdn_linktab;
1260
1261         lt->unit = sc->sc_unit;
1262         lt->channel = HSCX_CH_B;
1263         lt->bch_config = avma1pp2_bchannel_setup;
1264         lt->bch_tx_start = avma1pp2_bchannel_start;
1265         lt->bch_stat = avma1pp2_bchannel_stat;
1266         lt->tx_queue = &chan->tx_queue;
1267
1268         /* used by non-HDLC data transfers, i.e. telephony drivers */
1269         lt->rx_queue = &chan->rx_queue;
1270
1271         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1272         lt->rx_mbuf = &chan->in_mbuf;
1273 }
1274
1275 /*
1276  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1277  */
1278 static void
1279 avma1pp2_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1280 {
1281 #ifdef __FreeBSD__
1282         struct l1_softc *sc = ifpi2_scp[unit];
1283 #else
1284         struct l1_softc *sc = isic_find_sc(unit);
1285 #endif
1286         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1287         int s;
1288
1289         s = SPLI4B();
1290
1291         bsp->outbytes = chan->txcount;
1292         bsp->inbytes = chan->rxcount;
1293
1294         chan->txcount = 0;
1295         chan->rxcount = 0;
1296
1297         splx(s);
1298 }
1299
1300 /*---------------------------------------------------------------------------*
1301  *      fill HSCX fifo with data from the current mbuf
1302  *      Put this here until it can go into i4b_hscx.c
1303  *---------------------------------------------------------------------------*/
1304 static int
1305 avma1pp2_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1306 {
1307         int len;
1308         int nextlen;
1309         int i;
1310         int cmd = 0;
1311         /* using a scratch buffer simplifies writing to the FIFO */
1312         u_char scrbuf[HSCX_FIFO_LEN];
1313
1314         len = 0;
1315
1316         /*
1317          * fill the HSCX tx fifo with data from the current mbuf. if
1318          * current mbuf holds less data than HSCX fifo length, try to
1319          * get the next mbuf from (a possible) mbuf chain. if there is
1320          * not enough data in a single mbuf or in a chain, then this
1321          * is the last mbuf and we tell the HSCX that it has to send
1322          * CRC and closing flag
1323          */
1324
1325         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1326         {
1327                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1328
1329 #ifdef NOTDEF
1330                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1331                         chan->out_mbuf_head,
1332                         chan->out_mbuf_cur,
1333                         chan->out_mbuf_cur_ptr,
1334                         chan->out_mbuf_cur_len,
1335                         len,
1336                         nextlen);
1337 #endif
1338
1339                 cmd |= HSCX_CMDR_XTF;
1340                 /* collect the data in the scratch buffer */
1341                 for (i = 0; i < nextlen; i++)
1342                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1343
1344                 len += nextlen;
1345                 chan->txcount += nextlen;
1346
1347                 chan->out_mbuf_cur_ptr += nextlen;
1348                 chan->out_mbuf_cur_len -= nextlen;
1349
1350                 if(chan->out_mbuf_cur_len == 0)
1351                 {
1352                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1353                         {
1354                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1355                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1356
1357                                 if(sc->sc_trace & TRACE_B_TX)
1358                                 {
1359                                         i4b_trace_hdr_t hdr;
1360                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1361                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1362                                         hdr.dir = FROM_TE;
1363                                         hdr.count = ++sc->sc_trace_bcount;
1364                                         MICROTIME(hdr.time);
1365                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1366                                 }
1367                         }
1368                         else
1369                         {
1370                                 if (chan->bprot != BPROT_NONE)
1371                                         cmd |= HSCX_CMDR_XME;
1372                                 i4b_Bfreembuf(chan->out_mbuf_head);
1373                                 chan->out_mbuf_head = NULL;
1374                         }
1375                 }
1376         }
1377         /* write what we have from the scratch buf to the HSCX fifo */
1378         if (len != 0)
1379                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1380         return(cmd);
1381 }
1382
1383 /*---------------------------------------------------------------------------*
1384  *      ifpi2 - ISAC interrupt routine
1385  *---------------------------------------------------------------------------*/
1386 static void
1387 ifpi2_isacsx_intr(struct l1_softc *sc)
1388 {
1389         register u_char isacsx_irq_stat;
1390
1391         for(;;)
1392         {
1393                 /* get isac irq status */
1394                 /* ISTA tells us whether it was a C/I or HDLC int. */
1395                 isacsx_irq_stat = ISAC_READ(I_ISTA);
1396
1397                 if(isacsx_irq_stat)
1398                         ifpi2_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
1399                 else
1400                         break;
1401         }
1402
1403         ISAC_WRITE(I_MASKD, 0xff);
1404         ISAC_WRITE(I_MASK, 0xff);
1405
1406         DELAY(100);
1407
1408         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1409         ISAC_WRITE(I_MASK, isacsx_imask);
1410 }
1411
1412 /*---------------------------------------------------------------------------*
1413  *      ifpi2_recover - try to recover from irq lockup
1414  *---------------------------------------------------------------------------*/
1415 void
1416 ifpi2_recover(struct l1_softc *sc)
1417 {
1418         printf("ifpi2_recover %d\n", sc->sc_unit);
1419 #if 0 /* fix me later */
1420         u_char byte;
1421
1422         /* get isac irq status */
1423
1424         byte = ISAC_READ(I_ISTA);
1425
1426         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1427
1428         if(byte & ISACSX_ISTA_EXI)
1429                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1430
1431         if(byte & ISACSX_ISTA_CISQ)
1432         {
1433                 byte = ISAC_READ(I_CIRR);
1434
1435                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1436
1437                 if(byte & ISACSX_CIRR_SQC)
1438                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1439         }
1440
1441         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISACSX_IMASK);
1442
1443         ISAC_WRITE(I_MASKD, 0xff);
1444         ISAC_WRITE(I_MASK, 0xff);
1445         DELAY(100);
1446         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1447         ISAC_WRITE(I_MASK, isacsx_imask);
1448 #endif
1449 }