sys/i4b/layer1/ifpnp/i4b_ifpnp_avm.c

   1 /*-
   2  *   Copyright (c) 1999, 2000 Udo Schweigert. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  */
  31
  32 /*---------------------------------------------------------------------------
  33  *
  34  *      i4b_ifpnp_avm.c: AVM Fritz!Card PnP hardware driver
  35  *      ---------------------------------------------------
  36  *      last edit-date: [Fri Jan 12 17:05:28 2001]
  37  *
  38  *---------------------------------------------------------------------------*/
  39
  40 #include <sys/cdefs.h>
  41 __FBSDID("$FreeBSD$");
  42
  43 #include "opt_i4b.h"
  44
  45 #include <sys/param.h>
  46 #include <sys/kernel.h>
  47 #include <sys/systm.h>
  48 #include <sys/mbuf.h>
  49
  50 #include <machine/bus.h>
  51 #include <sys/bus.h>
  52 #include <sys/rman.h>
  53
  54 #include <isa/isavar.h>
  55
  56 #include <sys/socket.h>
  57 #include <net/if.h>
  58
  59 #include <i4b/include/i4b_debug.h>
  60 #include <i4b/include/i4b_ioctl.h>
  61 #include <i4b/include/i4b_trace.h>
  62
  63 #include <i4b/include/i4b_global.h>
  64 #include <i4b/include/i4b_mbuf.h>
  65
  66 #include <i4b/layer1/i4b_l1.h>
  67 #include <i4b/layer1/isic/i4b_isic.h>
  68 #include <i4b/layer1/isic/i4b_isac.h>
  69 #include <i4b/layer1/isic/i4b_hscx.h>
  70
  71 #include <i4b/layer1/ifpnp/i4b_ifpnp_ext.h>
  72
  73 /* prototypes */
  74 static void avm_pnp_intr(void *);
  75 static void hscx_write_reg(int, u_int, struct l1_softc *, u_int);
  76 static void hscx_write_reg_val(int, u_int, u_int8_t, struct l1_softc *);
  77 static u_int hscx_read_reg(int, u_int, struct l1_softc *);
  78 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  79 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  80 static void avm_pnp_hscx_int_handler(struct l1_softc *);
  81 static void avm_pnp_hscx_intr(int, u_int, u_int, struct l1_softc *);
  82 static void avm_pnp_init_linktab(struct l1_softc *);
  83 static void avm_pnp_bchannel_setup(int, int, int, int);
  84 static void avm_pnp_bchannel_start(int, int);
  85 static void avm_pnp_hscx_init(struct l1_softc *, int, int);
  86 static void avm_pnp_bchannel_stat(int, int, bchan_statistics_t *);
  87 static void avm_pnp_set_linktab(int, int, drvr_link_t *);
  88 static isdn_link_t * avm_pnp_ret_linktab(int, int);
  89 static int avm_pnp_probe(device_t);
  90 static int avm_pnp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
  91 int avm_pnp_attach(device_t);
  92 static void ifpnp_isac_intr(struct l1_softc *sc);
  93
  94 static device_method_t avm_pnp_methods[] = {
  95         /* Device interface */
  96         DEVMETHOD(device_probe,         avm_pnp_probe),
  97         DEVMETHOD(device_attach,        avm_pnp_attach),
  98         { 0, 0 }
  99 };
 100
 101 static driver_t avm_pnp_driver = {
 102         "ifpnp",
 103         avm_pnp_methods,
 104         sizeof(struct l1_softc)
 105 };
 106
 107 static devclass_t avm_pnp_devclass;
 108
 109 DRIVER_MODULE(avm_pnp, isa, avm_pnp_driver, avm_pnp_devclass, 0, 0);
 110
 111 /* jump table for multiplex routines */
 112
 113 struct i4b_l1mux_func avm_pnp_l1mux_func = {
 114         avm_pnp_ret_linktab,
 115         avm_pnp_set_linktab,
 116         ifpnp_mph_command_req,
 117         ifpnp_ph_data_req,
 118         ifpnp_ph_activate_req,
 119 };
 120
 121 struct l1_softc *ifpnp_scp[IFPNP_MAXUNIT];
 122
 123 /*---------------------------------------------------------------------------*
 124  *      AVM PnP Fritz!Card special registers
 125  *---------------------------------------------------------------------------*/
 126
 127 /*
 128  *      register offsets from i/o base
 129  */
 130 #define CLASS_OFFSET            0x00
 131 #define REVISION_OFFSET         0x01
 132 #define STAT0_OFFSET            0x02
 133 #define STAT1_OFFSET            0x03
 134 #define ADDR_REG_OFFSET         0x04
 135 /*#define MODREG_OFFSET         0x06
 136 #define VERREG_OFFSET           0x07*/
 137
 138 /* these 2 are used to select an ISAC register set */
 139 #define ISAC_LO_REG_OFFSET      0x04
 140 #define ISAC_HI_REG_OFFSET      0x06
 141
 142 /* offset higher than this goes to the HI register set */
 143 #define MAX_LO_REG_OFFSET       0x2f
 144
 145 /* mask for the offset */
 146 #define ISAC_REGSET_MASK        0x0f
 147
 148 /* the offset from the base to the ISAC registers */
 149 #define ISAC_REG_OFFSET         0x10
 150
 151 /* the offset from the base to the ISAC FIFO */
 152 #define ISAC_FIFO               0x02
 153
 154 /* not really the HSCX, but sort of */
 155 #define HSCX_FIFO               0x00
 156 #define HSCX_STAT               0x04
 157
 158 /*
 159  *      AVM PnP Status Latch 0 read only bits
 160  */
 161 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 162 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 163 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 164 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 165 /* actually active LOW */
 166 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 167
 168 /*
 169  *      AVM Status Latch 0 write only bits
 170  */
 171 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 172 #define ASL_TIMERDISABLE        0x02  /* active high */
 173 #define ASL_TIMERRESET          0x04  /* active high */
 174 #define ASL_ENABLE_INT          0x08  /* active high */
 175 #define ASL_TESTBIT             0x10  /* active high */
 176
 177 /*
 178  *      AVM Status Latch 1 write only bits
 179  */
 180 #define ASL1_INTSEL              0x0f  /* active high */
 181 #define ASL1_ENABLE_IOM          0x80  /* active high */
 182
 183 /*
 184  * "HSCX" mode bits
 185  */
 186 #define  HSCX_MODE_ITF_FLG      0x01
 187 #define  HSCX_MODE_TRANS        0x02
 188 #define  HSCX_MODE_CCR_7        0x04
 189 #define  HSCX_MODE_CCR_16       0x08
 190 #define  HSCX_MODE_TESTLOOP     0x80
 191
 192 /*
 193  * "HSCX" status bits
 194  */
 195 #define  HSCX_STAT_RME          0x01
 196 #define  HSCX_STAT_RDO          0x10
 197 #define  HSCX_STAT_CRCVFRRAB    0x0E
 198 #define  HSCX_STAT_CRCVFR       0x06
 199 #define  HSCX_STAT_RML_MASK     0x3f00
 200
 201 /*
 202  * "HSCX" interrupt bits
 203  */
 204 #define  HSCX_INT_XPR           0x80
 205 #define  HSCX_INT_XDU           0x40
 206 #define  HSCX_INT_RPR           0x20
 207 #define  HSCX_INT_MASK          0xE0
 208
 209 /*
 210  * "HSCX" command bits
 211  */
 212 #define  HSCX_CMD_XRS           0x80
 213 #define  HSCX_CMD_XME           0x01
 214 #define  HSCX_CMD_RRS           0x20
 215 #define  HSCX_CMD_XML_MASK      0x3f00
 216
 217 /*
 218  * to prevent deactivating the "HSCX" when both channels are active we
 219  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 220  * flag in avm_pnp_bchannel_setup upon active and cleared upon deactivation.
 221  * It is set high to allow room for new flags.
 222  */
 223 #define HSCX_AVMA1PP_ACTIVE     0x1000
 224
 225 /*---------------------------------------------------------------------------*
 226  *      AVM read fifo routines
 227  *---------------------------------------------------------------------------*/
 228
 229 static void
 230 avm_pnp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 231 {
 232         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 233         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 234
 235         switch (what) {
 236                 case ISIC_WHAT_ISAC:
 237                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 238                         bus_space_read_multi_1(btag, bhandle,  ISAC_REG_OFFSET, buf, size);
 239                         break;
 240                 case ISIC_WHAT_HSCXA:
 241                         hscx_read_fifo(0, buf, size, sc);
 242                         break;
 243                 case ISIC_WHAT_HSCXB:
 244                         hscx_read_fifo(1, buf, size, sc);
 245                         break;
 246         }
 247 }
 248
 249 static void
 250 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 251 {
 252         u_int8_t *ip;
 253         size_t cnt;
 254         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 255         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 256
 257         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 258         ip = (u_int8_t *)buf;
 259         cnt = 0;
 260         while (cnt++ < len)
 261         {
 262                 *ip++ = bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET);
 263         }
 264 }
 265
 266 /*---------------------------------------------------------------------------*
 267  *      AVM write fifo routines
 268  *---------------------------------------------------------------------------*/
 269 static void
 270 avm_pnp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 271 {
 272         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 273         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 274
 275         switch (what) {
 276                 case ISIC_WHAT_ISAC:
 277                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 278                         bus_space_write_multi_1(btag, bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
 279                         break;
 280                 case ISIC_WHAT_HSCXA:
 281                         hscx_write_fifo(0, buf, size, sc);
 282                         break;
 283                 case ISIC_WHAT_HSCXB:
 284                         hscx_write_fifo(1, buf, size, sc);
 285                         break;
 286         }
 287 }
 288
 289 static void
 290 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 291 {
 292         u_int8_t *ip;
 293         size_t cnt;
 294         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 295         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 296         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 297
 298         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 299         sc->avma1pp_txl = 0;
 300
 301         if (Bchan->out_mbuf_cur == NULL)
 302         {
 303           if (Bchan->bprot != BPROT_NONE)
 304                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 305         }
 306         if (len != sc->sc_bfifolen)
 307                 sc->avma1pp_txl = len;
 308
 309         hscx_write_reg(chan, HSCX_STAT, sc, 3);
 310
 311         ip = (u_int8_t *)buf;
 312         cnt = 0;
 313         while (cnt++ < len)
 314         {
 315                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET, *ip++);
 316         }
 317 }
 318
 319 /*---------------------------------------------------------------------------*
 320  *      AVM write register routines
 321  *---------------------------------------------------------------------------*/
 322
 323 static void
 324 avm_pnp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 325 {
 326         u_char reg_bank;
 327         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 328         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 329
 330         switch (what) {
 331                 case ISIC_WHAT_ISAC:
 332                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 333                         /* set the register bank */
 334                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 335                         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
 336                         break;
 337                 case ISIC_WHAT_HSCXA:
 338                         hscx_write_reg_val(0, offs, data, sc);
 339                         break;
 340                 case ISIC_WHAT_HSCXB:
 341                         hscx_write_reg_val(1, offs, data, sc);
 342                         break;
 343         }
 344 }
 345
 346 static void
 347 hscx_write_reg(int chan, u_int off, struct l1_softc *sc, u_int which)
 348 {
 349         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 350         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 351
 352         /* point at the correct channel */
 353         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 354         if (which & 4)
 355                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off + 2, sc->avma1pp_prot);
 356         if (which & 2)
 357                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off + 1, sc->avma1pp_txl);
 358         if (which & 1)
 359                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off, sc->avma1pp_cmd);
 360 }
 361
 362 static void
 363 hscx_write_reg_val(int chan, u_int off, u_int8_t val, struct l1_softc *sc)
 364 {
 365         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 366         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 367
 368         /* point at the correct channel */
 369         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 370         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off, val);
 371 }
 372
 373 /*---------------------------------------------------------------------------*
 374  *      AVM read register routines
 375  *---------------------------------------------------------------------------*/
 376 static u_int8_t
 377 avm_pnp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 378 {
 379         u_char reg_bank;
 380         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 381         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 382
 383         switch (what) {
 384                 case ISIC_WHAT_ISAC:
 385                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 386                         /* set the register bank */
 387                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 388                         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
 389                                 (offs & ISAC_REGSET_MASK)));
 390                 case ISIC_WHAT_HSCXA:
 391                         return hscx_read_reg(0, offs, sc);
 392                 case ISIC_WHAT_HSCXB:
 393                         return hscx_read_reg(1, offs, sc);
 394         }
 395         return 0;
 396 }
 397
 398 static u_int
 399 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
 400 {
 401         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 402         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 403
 404         /* point at the correct channel */
 405         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 406         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET + off));
 407 }
 408
 409
 410 static struct ifpnp_ids {
 411         u_long vend_id;
 412         char *id_str;
 413 } ifpnp_ids[] = {
 414         { 0x0009cd06,           "AVM Fritz!Card PnP"            },
 415         { 0, 0 }
 416 };
 417
 418 /*---------------------------------------------------------------------------*
 419  *      avm_pnp_probe - probe for a card
 420  *---------------------------------------------------------------------------*/
 421 static int
 422 avm_pnp_probe(dev)
 423         device_t                dev;
 424 {
 425         struct ifpnp_ids *ids;                  /* pnp id's */
 426         char *string = NULL;                            /* the name */
 427         u_int32_t vend_id = isa_get_vendorid(dev);      /* vendor id */
 428
 429         /* search table of knowd id's */
 430
 431         for(ids = ifpnp_ids; ids->vend_id != 0; ids++)
 432         {
 433                 if(vend_id == ids->vend_id)
 434                 {
 435                         string = ids->id_str;
 436                         break;
 437                 }
 438         }
 439
 440         if(string)              /* set name if we have one */
 441         {
 442                 device_set_desc(dev, string);   /* set description */
 443                 return 0;
 444         }
 445         else
 446         {
 447                 return ENXIO;
 448         }
 449 }
 450
 451 /*---------------------------------------------------------------------------*
 452  *      avm_pnp_attach - attach Fritz!Card PnP
 453  *---------------------------------------------------------------------------*/
 454 int
 455 avm_pnp_attach(device_t dev)
 456 {
 457         struct l1_softc *sc;
 458         u_int v;
 459         int unit, error = 0;
 460         int s;
 461         u_int16_t vid;
 462         void *ih = 0;
 463         bus_space_handle_t bhandle;
 464         bus_space_tag_t btag;
 465
 466         s = splimp();
 467
 468         vid = isa_get_vendorid(dev);
 469         sc = device_get_softc(dev);
 470         unit = device_get_unit(dev);
 471         bzero(sc, sizeof(struct l1_softc));
 472
 473         /* probably not really required */
 474         if(unit >= IFPNP_MAXUNIT) {
 475                 printf("avm_pnp%d: Error, unit >= IFPNP_MAXUNIT!\n", unit);
 476                 splx(s);
 477                 return(ENXIO);
 478         }
 479
 480         ifpnp_scp[unit] = sc;
 481
 482
 483         /* get io_base */
 484         if(!(sc->sc_resources.io_base[0] =
 485                         bus_alloc_resource_any(dev, SYS_RES_IOPORT,
 486                                                &sc->sc_resources.io_rid[0],
 487                                                RF_ACTIVE ) ))
 488         {
 489                 printf("avm_pnp_attach: Couldn't get my io_base.\n");
 490                 return ENXIO;
 491         }
 492         if (sc->sc_resources.io_base[0] == NULL) {
 493                 printf("avm_pnp%d: couldn't map IO port\n", unit);
 494                 error = ENXIO;
 495                 goto fail;
 496         }
 497
 498         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 499         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 500
 501         /* will not be used for pnp devices */
 502         sc->sc_port = rman_get_start(sc->sc_resources.io_base[0]);
 503
 504         /* get irq, release io_base if we don't get it */
 505
 506         if(!(sc->sc_resources.irq =
 507                         bus_alloc_resource_any(dev, SYS_RES_IRQ,
 508                                                &sc->sc_resources.irq_rid,
 509                                                RF_ACTIVE)))
 510         {
 511                 printf("avm_pnp%d: Could not get irq.\n",unit);
 512                 error = ENXIO;
 513                 goto fail;
 514         }
 515
 516         /* not needed */
 517         sc->sc_irq = rman_get_start(sc->sc_resources.irq);
 518         error = bus_setup_intr(dev,sc->sc_resources.irq,INTR_TYPE_NET,
 519                                 NULL, (void(*)(void*))avm_pnp_intr, sc,&ih);
 520         if (error != 0)
 521         {
 522                 printf("avm_pnp%d: Could not setup irq.\n",unit);
 523                 error = ENXIO;
 524                 goto fail;
 525         }
 526         sc->sc_unit = unit;
 527
 528         /* end of new-bus stuff */
 529
 530         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 531
 532         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 533         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 534
 535         /* setup access routines */
 536
 537         sc->clearirq = NULL;
 538         sc->readreg = avm_pnp_read_reg;
 539         sc->writereg = avm_pnp_write_reg;
 540
 541         sc->readfifo = avm_pnp_read_fifo;
 542         sc->writefifo = avm_pnp_write_fifo;
 543
 544         /* setup card type */
 545
 546         sc->sc_cardtyp = CARD_TYPEP_AVM_PNP;
 547
 548         /* setup IOM bus type */
 549
 550         sc->sc_bustyp = BUS_TYPE_IOM2;
 551
 552         /* set up some other miscellaneous things */
 553         sc->sc_ipac = 0;
 554         sc->sc_bfifolen = HSCX_FIFO_LEN;
 555
 556         /* reset the card */
 557         /* the Linux driver does this to clear any pending ISAC interrupts */
 558         v = 0;
 559         v = ISAC_READ(I_STAR);
 560         v = ISAC_READ(I_MODE);
 561         v = ISAC_READ(I_ADF2);
 562         v = ISAC_READ(I_ISTA);
 563         if (v & ISAC_ISTA_EXI)
 564         {
 565                  v = ISAC_READ(I_EXIR);
 566         }
 567         v = ISAC_READ(I_CIRR);
 568         ISAC_WRITE(I_MASK, 0xff);
 569         /* the Linux driver does this to clear any pending HSCX interrupts */
 570         v = hscx_read_reg(0, HSCX_STAT, sc);
 571         v = hscx_read_reg(1, HSCX_STAT, sc);
 572
 573         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 574         DELAY(SEC_DELAY/100); /* 10 ms */
 575         bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
 576         DELAY(SEC_DELAY/100); /* 10 ms */
 577         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 578         DELAY(SEC_DELAY/100); /* 10 ms */
 579
 580          printf("ifpnp%d: AVM Fritz!Card PnP Class %#x Revision %d \n", unit,
 581                         bus_space_read_1(btag, bhandle, CLASS_OFFSET),
 582                         bus_space_read_1(btag, bhandle, REVISION_OFFSET));
 583
 584          printf("ifpnp%d: ISAC %s (IOM-%c)\n", unit,
 585                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 586                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 587
 588
 589         /* init the ISAC */
 590         ifpnp_isac_init(sc);
 591
 592         /* init the "HSCX" */
 593         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 594
 595         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 596
 597         /* can't use the normal B-Channel stuff */
 598         avm_pnp_init_linktab(sc);
 599
 600         /* set trace level */
 601
 602         sc->sc_trace = TRACE_OFF;
 603
 604         sc->sc_state = ISAC_IDLE;
 605
 606         sc->sc_ibuf = NULL;
 607         sc->sc_ib = NULL;
 608         sc->sc_ilen = 0;
 609
 610         sc->sc_obuf = NULL;
 611         sc->sc_op = NULL;
 612         sc->sc_ol = 0;
 613         sc->sc_freeflag = 0;
 614
 615         sc->sc_obuf2 = NULL;
 616         sc->sc_freeflag2 = 0;
 617
 618         callout_handle_init(&sc->sc_T3_callout);
 619         callout_handle_init(&sc->sc_T4_callout);
 620
 621         /* init higher protocol layers */
 622
 623         i4b_l1_mph_status_ind(L0IFPNPUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avm_pnp_l1mux_func);
 624
 625   fail:
 626         splx(s);
 627         return(error);
 628 }
 629
 630 /*
 631  * this is the real interrupt routine
 632  */
 633 static void
 634 avm_pnp_hscx_intr(int h_chan, u_int stat, u_int cnt, struct l1_softc *sc)
 635 {
 636         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 637         int activity = -1;
 638
 639         NDBGL1(L1_H_IRQ, "%#x", stat);
 640
 641         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 642         {
 643                 chan->stat_XDU++;
 644                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 645                 /* abort the transmission */
 646                 sc->avma1pp_txl = 0;
 647                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 648                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 649                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 650                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 651
 652                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 653                 {
 654                         i4b_Bfreembuf(chan->out_mbuf_head);
 655                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 656                 }
 657         }
 658
 659         /*
 660          * The following is based on examination of the Linux driver.
 661          *
 662          * The logic here is different than with a "real" HSCX; all kinds
 663          * of information (interrupt/status bits) are in stat.
 664          *              HSCX_INT_RPR indicates a receive interrupt
 665          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 666          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 667          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 668          *                      CRC/framing errors are only reported in this state.
 669          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 670          *                                      CRC/framing error
 671          */
 672
 673         if(stat & HSCX_INT_RPR)
 674         {
 675                 register int fifo_data_len;
 676                 int error = 0;
 677                 /* always have to read the FIFO, so use a scratch buffer */
 678                 u_char scrbuf[HSCX_FIFO_LEN];
 679
 680                 if(stat & HSCX_STAT_RDO)
 681                 {
 682                         chan->stat_RDO++;
 683                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 684                         error++;
 685                 }
 686
 687                 /*
 688                  * check whether we're receiving data for an inactive B-channel
 689                  * and discard it. This appears to happen for telephony when
 690                  * both B-channels are active and one is deactivated. Since
 691                  * it is not really possible to deactivate the channel in that
 692                  * case (the ASIC seems to deactivate _both_ channels), the
 693                  * "deactivated" channel keeps receiving data which can lead
 694                  * to exhaustion of mbufs and a kernel panic.
 695                  *
 696                  * This is a hack, but it's the only solution I can think of
 697                  * without having the documentation for the ASIC.
 698                  * GJ - 28 Nov 1999
 699                  */
 700                  if (chan->state == HSCX_IDLE)
 701                  {
 702                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 703                         error++;
 704                  }
 705
 706                 fifo_data_len = cnt;
 707
 708                 if(fifo_data_len == 0)
 709                         fifo_data_len = sc->sc_bfifolen;
 710
 711                 /* ALWAYS read data from HSCX fifo */
 712
 713                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 714                 chan->rxcount += fifo_data_len;
 715
 716                 /* all error conditions checked, now decide and take action */
 717
 718                 if(error == 0)
 719                 {
 720                         if(chan->in_mbuf == NULL)
 721                         {
 722                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 723                                         panic("L1 avm_pnp_hscx_intr: RME, cannot allocate mbuf!\n");
 724                                 chan->in_cbptr = chan->in_mbuf->m_data;
 725                                 chan->in_len = 0;
 726                         }
 727
 728                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 729                         {
 730                                 /* OK to copy the data */
 731                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 732                                 chan->in_cbptr += fifo_data_len;
 733                                 chan->in_len += fifo_data_len;
 734
 735                                 /* setup mbuf data length */
 736
 737                                 chan->in_mbuf->m_len = chan->in_len;
 738                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 739
 740                                 if(sc->sc_trace & TRACE_B_RX)
 741                                 {
 742                                         i4b_trace_hdr_t hdr;
 743                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 744                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 745                                         hdr.dir = FROM_NT;
 746                                         hdr.count = ++sc->sc_trace_bcount;
 747                                         MICROTIME(hdr.time);
 748                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 749                                 }
 750
 751                                 if (stat & HSCX_STAT_RME)
 752                                 {
 753                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 754                                   {
 755                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 756                                          activity = ACT_RX;
 757
 758                                          /* mark buffer ptr as unused */
 759
 760                                          chan->in_mbuf = NULL;
 761                                          chan->in_cbptr = NULL;
 762                                          chan->in_len = 0;
 763                                   }
 764                                   else
 765                                   {
 766                                                 chan->stat_CRC++;
 767                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 768                                           if (chan->in_mbuf != NULL)
 769                                           {
 770                                                   i4b_Bfreembuf(chan->in_mbuf);
 771                                                   chan->in_mbuf = NULL;
 772                                                   chan->in_cbptr = NULL;
 773                                                   chan->in_len = 0;
 774                                           }
 775                                   }
 776                                 }
 777                         } /* END enough space in mbuf */
 778                         else
 779                         {
 780                                  if(chan->bprot == BPROT_NONE)
 781                                  {
 782                                           /* setup mbuf data length */
 783
 784                                           chan->in_mbuf->m_len = chan->in_len;
 785                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 786
 787                                           if(sc->sc_trace & TRACE_B_RX)
 788                                           {
 789                                                         i4b_trace_hdr_t hdr;
 790                                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 791                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 792                                                         hdr.dir = FROM_NT;
 793                                                         hdr.count = ++sc->sc_trace_bcount;
 794                                                         MICROTIME(hdr.time);
 795                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 796                                                 }
 797
 798                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 799                                                  activity = ACT_RX;
 800
 801                                           /* move rx'd data to rx queue */
 802 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 803                                           (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
 804 #else
 805                                           if(!(IF_QFULL(&chan->rx_queue)))
 806                                           {
 807                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 808                                           }
 809                                           else
 810                                           {
 811                                                 i4b_Bfreembuf(chan->in_mbuf);
 812                                           }
 813 #endif
 814                                           /* signal upper layer that data are available */
 815                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 816
 817                                           /* alloc new buffer */
 818
 819                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 820                                                  panic("L1 avm_pnp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 821
 822                                           /* setup new data ptr */
 823
 824                                           chan->in_cbptr = chan->in_mbuf->m_data;
 825
 826                                           /* OK to copy the data */
 827                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 828
 829                                           chan->in_cbptr += fifo_data_len;
 830                                           chan->in_len = fifo_data_len;
 831
 832                                           chan->rxcount += fifo_data_len;
 833                                         }
 834                                  else
 835                                         {
 836                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 837                                           chan->in_cbptr = chan->in_mbuf->m_data;
 838                                           chan->in_len = 0;
 839                                         }
 840                           }
 841                 } /* if(error == 0) */
 842                 else
 843                 {
 844                         /* land here for RDO */
 845                         if (chan->in_mbuf != NULL)
 846                         {
 847                                 i4b_Bfreembuf(chan->in_mbuf);
 848                                 chan->in_mbuf = NULL;
 849                                 chan->in_cbptr = NULL;
 850                                 chan->in_len = 0;
 851                         }
 852                         sc->avma1pp_txl = 0;
 853                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 854                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 855                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 856                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 857                 }
 858         }
 859
 860
 861         /* transmit fifo empty, new data can be written to fifo */
 862
 863         if(stat & HSCX_INT_XPR)
 864         {
 865                 /*
 866                  * for a description what is going on here, please have
 867                  * a look at isic_bchannel_start() in i4b_bchan.c !
 868                  */
 869
 870                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 871
 872                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 873                 {
 874                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 875
 876                         if(chan->out_mbuf_head == NULL)
 877                         {
 878                                 chan->state &= ~HSCX_TX_ACTIVE;
 879                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 880                         }
 881                         else
 882                         {
 883                                 chan->state |= HSCX_TX_ACTIVE;
 884                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 885                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 886                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 887
 888                                 if(sc->sc_trace & TRACE_B_TX)
 889                                 {
 890                                         i4b_trace_hdr_t hdr;
 891                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 892                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 893                                         hdr.dir = FROM_TE;
 894                                         hdr.count = ++sc->sc_trace_bcount;
 895                                         MICROTIME(hdr.time);
 896                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 897                                 }
 898
 899                                 if(chan->bprot == BPROT_NONE)
 900                                 {
 901                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 902                                                 activity = ACT_TX;
 903                                 }
 904                                 else
 905                                 {
 906                                         activity = ACT_TX;
 907                                 }
 908                         }
 909                 }
 910
 911                 avm_pnp_hscx_fifo(chan, sc);
 912         }
 913
 914         /* call timeout handling routine */
 915
 916         if(activity == ACT_RX || activity == ACT_TX)
 917                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 918 }
 919
 920 /*
 921  * this is the main routine which checks each channel and then calls
 922  * the real interrupt routine as appropriate
 923  */
 924 static void
 925 avm_pnp_hscx_int_handler(struct l1_softc *sc)
 926 {
 927         u_char stat = 0;
 928         u_char cnt = 0;
 929
 930         stat = hscx_read_reg(0, HSCX_STAT, sc);
 931         if (stat & HSCX_INT_RPR)
 932           cnt = hscx_read_reg(0, HSCX_STAT+1, sc);
 933         if (stat & HSCX_INT_MASK)
 934           avm_pnp_hscx_intr(0, stat, cnt, sc);
 935
 936         cnt = 0;
 937         stat = hscx_read_reg(1, HSCX_STAT, sc);
 938         if (stat & HSCX_INT_RPR)
 939           cnt = hscx_read_reg(1, HSCX_STAT+1, sc);
 940         if (stat & HSCX_INT_MASK)
 941           avm_pnp_hscx_intr(1, stat, cnt, sc);
 942 }
 943
 944 static void
 945 avm_pnp_intr(void *xsc)
 946 {
 947         u_char stat;
 948         struct l1_softc *sc;
 949         bus_space_handle_t bhandle;
 950         bus_space_tag_t btag;
 951
 952         sc = xsc;
 953         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 954         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 955
 956         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 957         NDBGL1(L1_H_IRQ, "stat %x", stat);
 958         /* was there an interrupt from this card ? */
 959         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
 960                 return; /* no */
 961         /* interrupts are low active */
 962         if (!(stat & ASL_IRQ_TIMER))
 963           NDBGL1(L1_H_IRQ, "timer interrupt ???");
 964         if (!(stat & ASL_IRQ_HSCX))
 965         {
 966           NDBGL1(L1_H_IRQ, "HSCX");
 967                 avm_pnp_hscx_int_handler(sc);
 968         }
 969         if (!(stat & ASL_IRQ_ISAC))
 970         {
 971           NDBGL1(L1_H_IRQ, "ISAC");
 972                 ifpnp_isac_intr(sc);
 973         }
 974 }
 975
 976 static void
 977 avm_pnp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
 978 {
 979         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 980
 981         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
 982                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
 983
 984         if (activate == 0)
 985         {
 986                 /* only deactivate if both channels are idle */
 987                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
 988                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
 989                 {
 990                         return;
 991                 }
 992                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 993                 sc->avma1pp_prot = HSCX_MODE_TRANS;
 994                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
 995                 return;
 996         }
 997         if(chan->bprot == BPROT_RHDLC)
 998         {
 999                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1000
1001                 /* HDLC Frames, transparent mode 0 */
1002                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1003                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1004                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
1005                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1006                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
1007                 sc->avma1pp_cmd = 0;
1008         }
1009         else
1010         {
1011                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1012
1013                 /* Raw Telephony, extended transparent mode 1 */
1014                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1015                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1016                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
1017                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1018                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
1019                 sc->avma1pp_cmd = 0;
1020         }
1021 }
1022
1023 static void
1024 avm_pnp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1025 {
1026         struct l1_softc *sc = ifpnp_scp[unit];
1027         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1028
1029         int s = SPLI4B();
1030
1031         if(activate == 0)
1032         {
1033                 /* deactivation */
1034                 chan->state = HSCX_IDLE;
1035                 avm_pnp_hscx_init(sc, h_chan, activate);
1036         }
1037
1038         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1039                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1040
1041         /* general part */
1042
1043         chan->unit = sc->sc_unit;       /* unit number */
1044         chan->channel = h_chan;         /* B channel */
1045         chan->bprot = bprot;            /* B channel protocol */
1046         chan->state = HSCX_IDLE;        /* B channel state */
1047
1048         /* receiver part */
1049
1050         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1051
1052 #if defined (__FreeBSD__) && __FreeBSD__ > 4
1053         if(!mtx_initialized(&chan->rx_queue.ifq_mtx))
1054                 mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avm_pnp_rx", NULL, MTX_DEF);
1055 #endif
1056
1057         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1058
1059         chan->rxcount = 0;              /* reset rx counter */
1060
1061         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1062
1063         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1064         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1065         chan->in_len = 0;               /* reset mbuf data len */
1066
1067         /* transmitter part */
1068
1069         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1070
1071 #if defined (__FreeBSD__) && __FreeBSD__ > 4
1072         if(!mtx_initialized(&chan->tx_queue.ifq_mtx))
1073                 mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avm_pnp_tx", NULL, MTX_DEF);
1074 #endif
1075         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1076
1077         chan->txcount = 0;              /* reset tx counter */
1078
1079         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1080
1081         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1082         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1083         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1084         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1085
1086         if(activate != 0)
1087         {
1088                 /* activation */
1089                 avm_pnp_hscx_init(sc, h_chan, activate);
1090                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1091         }
1092
1093         splx(s);
1094 }
1095
1096 static void
1097 avm_pnp_bchannel_start(int unit, int h_chan)
1098 {
1099         struct l1_softc *sc = ifpnp_scp[unit];
1100         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1101         int s;
1102         int activity = -1;
1103
1104         s = SPLI4B();                           /* enter critical section */
1105         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1106         {
1107                 splx(s);
1108                 return;                         /* yes, leave */
1109         }
1110
1111         /* get next mbuf from queue */
1112
1113         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1114
1115         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1116         {
1117                 splx(s);                        /* leave critical section */
1118                 return;                         /* yes, exit */
1119         }
1120
1121         /* init current mbuf values */
1122
1123         chan->out_mbuf_cur = chan->out_mbuf_head;
1124         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1125         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1126
1127         /* activity indicator for timeout handling */
1128
1129         if(chan->bprot == BPROT_NONE)
1130         {
1131                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1132                         activity = ACT_TX;
1133         }
1134         else
1135         {
1136                 activity = ACT_TX;
1137         }
1138
1139         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1140
1141         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1142         {
1143                 i4b_trace_hdr_t hdr;
1144                 hdr.unit = L0IFPNPUNIT(sc->sc_unit);
1145                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1146                 hdr.dir = FROM_TE;
1147                 hdr.count = ++sc->sc_trace_bcount;
1148                 MICROTIME(hdr.time);
1149                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1150         }
1151
1152         avm_pnp_hscx_fifo(chan, sc);
1153
1154         /* call timeout handling routine */
1155
1156         if(activity == ACT_RX || activity == ACT_TX)
1157                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1158
1159         splx(s);
1160 }
1161
1162 /*---------------------------------------------------------------------------*
1163  *      return the address of isic drivers linktab
1164  *---------------------------------------------------------------------------*/
1165 static isdn_link_t *
1166 avm_pnp_ret_linktab(int unit, int channel)
1167 {
1168         struct l1_softc *sc = ifpnp_scp[unit];
1169         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1170
1171         return(&chan->isic_isdn_linktab);
1172 }
1173
1174 /*---------------------------------------------------------------------------*
1175  *      set the driver linktab in the b channel softc
1176  *---------------------------------------------------------------------------*/
1177 static void
1178 avm_pnp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1179 {
1180         struct l1_softc *sc = ifpnp_scp[unit];
1181         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1182
1183         chan->isic_drvr_linktab = dlt;
1184 }
1185
1186
1187 /*---------------------------------------------------------------------------*
1188  *      initialize our local linktab
1189  *---------------------------------------------------------------------------*/
1190 static void
1191 avm_pnp_init_linktab(struct l1_softc *sc)
1192 {
1193         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1194         isdn_link_t *lt = &chan->isic_isdn_linktab;
1195
1196         /* make sure the hardware driver is known to layer 4 */
1197         /* avoid overwriting if already set */
1198         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1199         {
1200                 ctrl_types[CTRL_PASSIVE].set_linktab = avm_pnp_set_linktab;
1201                 ctrl_types[CTRL_PASSIVE].get_linktab = avm_pnp_ret_linktab;
1202         }
1203
1204         /* local setup */
1205         lt->unit = sc->sc_unit;
1206         lt->channel = HSCX_CH_A;
1207         lt->bch_config = avm_pnp_bchannel_setup;
1208         lt->bch_tx_start = avm_pnp_bchannel_start;
1209         lt->bch_stat = avm_pnp_bchannel_stat;
1210         lt->tx_queue = &chan->tx_queue;
1211
1212         /* used by non-HDLC data transfers, i.e. telephony drivers */
1213         lt->rx_queue = &chan->rx_queue;
1214
1215         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1216         lt->rx_mbuf = &chan->in_mbuf;
1217
1218         chan = &sc->sc_chan[HSCX_CH_B];
1219         lt = &chan->isic_isdn_linktab;
1220
1221         lt->unit = sc->sc_unit;
1222         lt->channel = HSCX_CH_B;
1223         lt->bch_config = avm_pnp_bchannel_setup;
1224         lt->bch_tx_start = avm_pnp_bchannel_start;
1225         lt->bch_stat = avm_pnp_bchannel_stat;
1226         lt->tx_queue = &chan->tx_queue;
1227
1228         /* used by non-HDLC data transfers, i.e. telephony drivers */
1229         lt->rx_queue = &chan->rx_queue;
1230
1231         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1232         lt->rx_mbuf = &chan->in_mbuf;
1233 }
1234
1235 /*
1236  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1237  */
1238 static void
1239 avm_pnp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1240 {
1241         struct l1_softc *sc = ifpnp_scp[unit];
1242         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1243         int s;
1244
1245         s = SPLI4B();
1246
1247         bsp->outbytes = chan->txcount;
1248         bsp->inbytes = chan->rxcount;
1249
1250         chan->txcount = 0;
1251         chan->rxcount = 0;
1252
1253         splx(s);
1254 }
1255
1256 /*---------------------------------------------------------------------------*
1257  *      fill HSCX fifo with data from the current mbuf
1258  *      Put this here until it can go into i4b_hscx.c
1259  *---------------------------------------------------------------------------*/
1260 static int
1261 avm_pnp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1262 {
1263         int len;
1264         int nextlen;
1265         int i;
1266         int cmd = 0;
1267         /* using a scratch buffer simplifies writing to the FIFO */
1268         u_char scrbuf[HSCX_FIFO_LEN];
1269
1270         len = 0;
1271
1272         /*
1273          * fill the HSCX tx fifo with data from the current mbuf. if
1274          * current mbuf holds less data than HSCX fifo length, try to
1275          * get the next mbuf from (a possible) mbuf chain. if there is
1276          * not enough data in a single mbuf or in a chain, then this
1277          * is the last mbuf and we tell the HSCX that it has to send
1278          * CRC and closing flag
1279          */
1280
1281         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1282         {
1283                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1284
1285 #ifdef NOTDEF
1286                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1287                         chan->out_mbuf_head,
1288                         chan->out_mbuf_cur,
1289                         chan->out_mbuf_cur_ptr,
1290                         chan->out_mbuf_cur_len,
1291                         len,
1292                         nextlen);
1293 #endif
1294
1295                 cmd |= HSCX_CMDR_XTF;
1296                 /* collect the data in the scratch buffer */
1297                 for (i = 0; i < nextlen; i++)
1298                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1299
1300                 len += nextlen;
1301                 chan->txcount += nextlen;
1302
1303                 chan->out_mbuf_cur_ptr += nextlen;
1304                 chan->out_mbuf_cur_len -= nextlen;
1305
1306                 if(chan->out_mbuf_cur_len == 0)
1307                 {
1308                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1309                         {
1310                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1311                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1312
1313                                 if(sc->sc_trace & TRACE_B_TX)
1314                                 {
1315                                         i4b_trace_hdr_t hdr;
1316                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
1317                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1318                                         hdr.dir = FROM_TE;
1319                                         hdr.count = ++sc->sc_trace_bcount;
1320                                         MICROTIME(hdr.time);
1321                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1322                                 }
1323                         }
1324                         else
1325                         {
1326                                 if (chan->bprot != BPROT_NONE)
1327                                         cmd |= HSCX_CMDR_XME;
1328                                 i4b_Bfreembuf(chan->out_mbuf_head);
1329                                 chan->out_mbuf_head = NULL;
1330                         }
1331                 }
1332         }
1333         /* write what we have from the scratch buf to the HSCX fifo */
1334         if (len != 0)
1335                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1336         return(cmd);
1337 }
1338
1339 /*---------------------------------------------------------------------------*
1340  *      ifpnp - ISAC interrupt routine
1341  *---------------------------------------------------------------------------*/
1342 static void
1343 ifpnp_isac_intr(struct l1_softc *sc)
1344 {
1345         register u_char isac_irq_stat;
1346
1347         for(;;)
1348         {
1349                 /* get isac irq status */
1350                 isac_irq_stat = ISAC_READ(I_ISTA);
1351
1352                 if(isac_irq_stat)
1353                         ifpnp_isac_irq(sc, isac_irq_stat); /* isac handler */
1354                 else
1355                         break;
1356         }
1357
1358         ISAC_WRITE(I_MASK, 0xff);
1359
1360         DELAY(100);
1361
1362         ISAC_WRITE(I_MASK, ISAC_IMASK);
1363 }
1364
1365 /*---------------------------------------------------------------------------*
1366  *      ifpnp_recover - try to recover from irq lockup
1367  *---------------------------------------------------------------------------*/
1368 void
1369 ifpnp_recover(struct l1_softc *sc)
1370 {
1371         u_char byte;
1372
1373         /* get isac irq status */
1374
1375         byte = ISAC_READ(I_ISTA);
1376
1377         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1378
1379         if(byte & ISAC_ISTA_EXI)
1380                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1381
1382         if(byte & ISAC_ISTA_CISQ)
1383         {
1384                 byte = ISAC_READ(I_CIRR);
1385
1386                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1387
1388                 if(byte & ISAC_CIRR_SQC)
1389                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1390         }
1391
1392         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
1393
1394         ISAC_WRITE(I_MASK, 0xff);
1395         DELAY(100);
1396         ISAC_WRITE(I_MASK, ISAC_IMASK);
1397 }