sys/i4b/layer1/itjc/i4b_itjc_pci.c

   1 /*-
   2  *   Copyright (c) 2000, 2001 Sergio Prallon. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  */
  31
  32 /*---------------------------------------------------------------------------
  33  *
  34  *      i4b_itjc_pci.c: NetJet-S hardware driver
  35  *      ----------------------------------------
  36  *      last edit-date: [Sat May 13 15:25:47 2006]
  37  *
  38  *---------------------------------------------------------------------------*/
  39
  40 #include <sys/cdefs.h>
  41 __FBSDID("$FreeBSD$");
  42
  43 #include "opt_i4b.h"
  44
  45 #include <sys/param.h>
  46 #include <sys/kernel.h>
  47 #include <sys/systm.h>
  48 #include <sys/mbuf.h>
  49
  50 #include <machine/bus.h>
  51 #include <machine/resource.h>
  52 #include <sys/bus.h>
  53 #include <sys/rman.h>
  54
  55 #include <dev/pci/pcireg.h>
  56 #include <dev/pci/pcivar.h>
  57
  58 #include <sys/socket.h>
  59 #include <net/if.h>
  60
  61 #include <i4b/include/i4b_debug.h>
  62 #include <i4b/include/i4b_ioctl.h>
  63 #include <i4b/include/i4b_trace.h>
  64
  65 #include <i4b/include/i4b_global.h>
  66 #include <i4b/include/i4b_mbuf.h>
  67
  68 #include <i4b/layer1/i4b_l1.h>
  69
  70 #include <i4b/layer1/itjc/i4b_hdlc.h>   /* XXXXXXXXXXXXXXXXXXXXXXXX */
  71
  72 #include <i4b/layer1/isic/i4b_isic.h>
  73 #include <i4b/layer1/isic/i4b_isac.h>
  74
  75 #include <i4b/layer1/itjc/i4b_itjc_ext.h>
  76
  77 #define PCI_TJNET_VID (0xe159)
  78 #define PCI_TJ300_DID (0x0001)
  79
  80
  81 /*
  82  * Function prototypes
  83  */
  84
  85 static int  itjc_probe(device_t dev);
  86 static int  itjc_attach(device_t dev);
  87 static void itjc_shutdown(device_t dev);
  88 static void itjc_intr(void *xsc);
  89 static int  itjc_dma_start(struct l1_softc *sc);
  90 static void itjc_dma_stop(struct l1_softc *sc);
  91 static void itjc_isac_intr(struct l1_softc *sc);
  92 static void itjc_init_linktab(struct l1_softc *sc);
  93 static void itjc_bchannel_setup(int unit, int h_chan, int bprot,
  94         int activate);
  95 static void itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp);
  96
  97
  98 /*
  99  * Shorter names to bus resource manager routines.
 100  */
 101
 102 #define itjc_bus_setup(sc)                                              \
 103         bus_space_handle_t h =                                          \
 104                 rman_get_bushandle((sc)->sc_resources.io_base[0]);      \
 105         bus_space_tag_t    t =                                          \
 106                 rman_get_bustag((sc)->sc_resources.io_base[0]);
 107
 108 #define itjc_read_1(port)       (bus_space_read_1(t, h, (port)))
 109 #define itjc_read_4(port)       (bus_space_read_4(t, h, (port)))
 110 #define itjc_write_1(port, data) (bus_space_write_1(t, h, (port), (data)))
 111 #define itjc_write_4(port, data) (bus_space_write_4(t, h, (port), (data)))
 112 #define itjc_read_multi_1(port, buf, size)                              \
 113         (bus_space_read_multi_1(t, h, (port), (buf), (size)))
 114 #define itjc_write_multi_1(port, buf, size)                             \
 115         (bus_space_write_multi_1(t, h, (port), (buf), (size)))
 116
 117
 118 /*---------------------------------------------------------------------------*
 119  *      Glue data to register ourselves as a PCI device driver.
 120  *---------------------------------------------------------------------------*/
 121
 122 static device_method_t itjc_pci_methods[] =
 123 {
 124         /* Device interface */
 125         DEVMETHOD(device_probe,         itjc_probe),
 126         DEVMETHOD(device_attach,        itjc_attach),
 127         DEVMETHOD(device_shutdown,      itjc_shutdown),
 128
 129         /* bus interface */
 130         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 131         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 132
 133         { 0, 0 }
 134 };
 135
 136 static driver_t itjc_pci_driver =
 137 {
 138         "itjc",
 139         itjc_pci_methods,
 140         sizeof(struct l1_softc)
 141 };
 142
 143 static devclass_t itjc_pci_devclass;
 144
 145 DRIVER_MODULE(netjet, pci, itjc_pci_driver, itjc_pci_devclass, 0, 0);
 146
 147 /*
 148  * Jump table for multiplex routines.
 149  */
 150
 151 struct i4b_l1mux_func itjc_l1mux_func =
 152 {
 153         itjc_ret_linktab,
 154         itjc_set_linktab,
 155         itjc_mph_command_req,
 156         itjc_ph_data_req,
 157         itjc_ph_activate_req,
 158 };
 159
 160 struct l1_softc *itjc_scp[ITJC_MAXUNIT];
 161
 162
 163 /*---------------------------------------------------------------------------*
 164  *      Tiger300/320 PCI ASIC registers.
 165  *---------------------------------------------------------------------------*/
 166
 167 /*
 168  *      Register offsets from i/o base.
 169  */
 170 enum tiger_regs
 171 {
 172         TIGER_RESET_PIB_CL_TIME = 0x00,
 173         TIGER_DMA_OPER          = 0x01,
 174         TIGER_AUX_PORT_CNTL     = 0x02,
 175         TIGER_AUX_PORT_DATA     = 0x03,
 176         TIGER_INT0_MASK         = 0x04,
 177         TIGER_INT1_MASK         = 0x05,
 178         TIGER_INT0_STATUS       = 0x06,
 179         TIGER_INT1_STATUS       = 0x07,
 180         TIGER_DMA_WR_START_ADDR = 0x08,
 181         TIGER_DMA_WR_INT_ADDR   = 0x0C,
 182         TIGER_DMA_WR_END_ADDR   = 0x10,
 183         TIGER_DMA_WR_CURR_ADDR  = 0x14,
 184         TIGER_DMA_RD_START_ADDR = 0x18,
 185         TIGER_DMA_RD_INT_ADDR   = 0x1C,
 186         TIGER_DMA_RD_END_ADDR   = 0x20,
 187         TIGER_DMA_RD_CURR_ADDR  = 0x24,
 188         TIGER_PULSE_COUNTER     = 0x28,
 189 };
 190
 191 /*
 192  * Bits on the above registers.
 193  */
 194
 195 enum tiger_reg_bits
 196 {
 197 /* Reset and PIB Cycle Timing */
 198
 199         TIGER_DMA_OP_MODE_MASK          = 0x80,
 200                 TIGER_SELF_ADDR_DMA     = 0x00, /* Wrap around ending addr */
 201                 TIGER_NORMAL_DMA        = 0x80, /* Stop at ending addr */
 202
 203         TIGER_DMA_INT_MODE_MASK         = 0x40,
 204                 TIGER_DONT_LATCH_DMA_INT= 0x00, /* Bits on int0 status will be
 205                                                    set only while curr addr
 206                                                    equals int or end addr */
 207                 TIGER_LATCH_DMA_INT     = 0x40, /* Bits on int0 status remain
 208                                                    set until cleared by CPU */
 209
 210         TIGER_PIB_CYCLE_TIMING_MASK     = 0x30,
 211                 TIGER_PIB_3_CYCLES      = 0x00,
 212                 TIGER_PIB_5_CYCLES      = 0x10,
 213                 TIGER_PIB_12_CYCLES     = 0x20,
 214
 215         TIGER_RESET_MASK                = 0x0F,
 216                 TIGER_RESET_PULSE_COUNT = 0x08,
 217                 TIGER_RESET_SERIAL_PORT = 0x04,
 218                 TIGER_RESET_DMA_LOGIC   = 0x02,
 219                 TIGER_RESET_EXTERNAL    = 0x01,
 220                 TIGER_RESET_ALL         = 0x0F,
 221
 222 /* DMA Operation */
 223         TIGER_DMA_RESTART_MASK          = 0x02,
 224                 TIGER_HOLD_DMA          = 0x00,
 225                 TIGER_RESTART_DMA       = 0x02,
 226
 227         TIGER_DMA_ENABLE_MASK           = 0x01,
 228                 TIGER_ENABLE_DMA        = 0x01,
 229                 TIGER_DISABLE_DMA       = 0x00,
 230
 231 /* AUX Port Control & Data plus Interrupt 1 Mask & Status  */
 232         TIGER_AUX_7_MASK                = 0x80,
 233         TIGER_AUX_6_MASK                = 0x40,
 234         TIGER_AUX_5_MASK                = 0x20,
 235         TIGER_AUX_4_MASK                = 0x10,
 236         TIGER_ISAC_INT_MASK             = 0x10,
 237         TIGER_AUX_3_MASK                = 0x08,
 238         TIGER_AUX_2_MASK                = 0x04,
 239         TIGER_AUX_1_MASK                = 0x02,
 240         TIGER_AUX_0_MASK                = 0x01,
 241
 242 /* AUX Port Control */
 243                 TIGER_AUX_7_IS_INPUT    = 0x00,
 244                 TIGER_AUX_7_IS_OUTPUT   = 0x80,
 245                 TIGER_AUX_6_IS_INPUT    = 0x00,
 246                 TIGER_AUX_6_IS_OUTPUT   = 0x40,
 247                 TIGER_AUX_5_IS_INPUT    = 0x00,
 248                 TIGER_AUX_5_IS_OUTPUT   = 0x20,
 249                 TIGER_AUX_4_IS_INPUT    = 0x00,
 250                 TIGER_AUX_4_IS_OUTPUT   = 0x10,
 251                 TIGER_AUX_3_IS_INPUT    = 0x00,
 252                 TIGER_AUX_3_IS_OUTPUT   = 0x08,
 253                 TIGER_AUX_2_IS_INPUT    = 0x00,
 254                 TIGER_AUX_2_IS_OUTPUT   = 0x04,
 255                 TIGER_AUX_1_IS_INPUT    = 0x00,
 256                 TIGER_AUX_1_IS_OUTPUT   = 0x02,
 257                 TIGER_AUX_0_IS_INPUT    = 0x00,
 258                 TIGER_AUX_0_IS_OUTPUT   = 0x01,
 259                 TIGER_AUX_NJ_DEFAULT    = 0xEF, /* All but ISAC int is output */
 260
 261 /* Interrupt 0 Mask & Status */
 262         TIGER_PCI_TARGET_ABORT_INT_MASK = 0x20,
 263                 TIGER_NO_TGT_ABORT_INT  = 0x00,
 264                 TIGER_TARGET_ABORT_INT  = 0x20,
 265         TIGER_PCI_MASTER_ABORT_INT_MASK = 0x10,
 266                 TIGER_NO_MST_ABORT_INT  = 0x00,
 267                 TIGER_MASTER_ABORT_INT  = 0x10,
 268         TIGER_DMA_RD_END_INT_MASK       = 0x08,
 269                 TIGER_NO_RD_END_INT     = 0x00,
 270                 TIGER_RD_END_INT        = 0x08,
 271         TIGER_DMA_RD_INT_INT_MASK       = 0x04,
 272                 TIGER_NO_RD_INT_INT     = 0x00,
 273                 TIGER_RD_INT_INT        = 0x04,
 274         TIGER_DMA_WR_END_INT_MASK       = 0x02,
 275                 TIGER_NO_WR_END_INT     = 0x00,
 276                 TIGER_WR_END_INT        = 0x02,
 277         TIGER_DMA_WR_INT_INT_MASK       = 0x01,
 278                 TIGER_NO_WR_INT_INT     = 0x00,
 279                 TIGER_WR_INT_INT        = 0x01,
 280
 281 /* Interrupt 1 Mask & Status */
 282                 TIGER_NO_AUX_7_INT      = 0x00,
 283                 TIGER_AUX_7_INT         = 0x80,
 284                 TIGER_NO_AUX_6_INT      = 0x00,
 285                 TIGER_AUX_6_INT         = 0x40,
 286                 TIGER_NO_AUX_5_INT      = 0x00,
 287                 TIGER_AUX_5_INT         = 0x20,
 288                 TIGER_NO_AUX_4_INT      = 0x00,
 289                 TIGER_AUX_4_INT         = 0x10,
 290                 TIGER_NO_ISAC_INT       = 0x00,
 291                 TIGER_ISAC_INT          = 0x10,
 292                 TIGER_NO_AUX_3_INT      = 0x00,
 293                 TIGER_AUX_3_INT         = 0x08,
 294                 TIGER_NO_AUX_2_INT      = 0x00,
 295                 TIGER_AUX_2_INT         = 0x04,
 296                 TIGER_NO_AUX_1_INT      = 0x00,
 297                 TIGER_AUX_1_INT         = 0x02,
 298                 TIGER_NO_AUX_0_INT      = 0x00,
 299                 TIGER_AUX_0_INT         = 0x01
 300 };
 301
 302 /*
 303  * Peripheral Interface Bus definitions. This is an ISA like bus
 304  * created by the Tiger ASIC to keep ISA chips like the ISAC happy
 305  * on a PCI environment.
 306  *
 307  * Since the PIB only supplies 4 addressing lines, the 2 higher bits
 308  * (A4 & A5) of the ISAC register addresses are wired on the 2 lower
 309  * AUX lines. Another restriction is that all I/O to the PIB (8bit
 310  * wide) is mapped on the PCI side as 32bit data. So the PCI address
 311  * of a given ISAC register has to be multiplied by 4 before being
 312  * added to the PIB base offset.
 313  */
 314 enum tiger_pib_regs_defs
 315 {
 316         /* Offset from the I/O base to the ISAC registers. */
 317         PIB_OFFSET              = 0xC0,
 318         PIB_LO_ADDR_MASK        = 0x0F,
 319         PIB_HI_ADDR_MASK        = 0x30,
 320         PIB_LO_ADDR_SHIFT       = 2,    /* Align on dword boundary */
 321         PIB_HI_ADDR_SHIFT       = 4     /* Right shift to AUX_1 & AUX_0 */
 322 };
 323
 324
 325 #define itjc_set_pib_addr_msb(a)                                        \
 326 (                                                                       \
 327         itjc_write_1(TIGER_AUX_PORT_DATA,                               \
 328                 ((a) & PIB_HI_ADDR_MASK) >> PIB_HI_ADDR_SHIFT)          \
 329 )
 330
 331 #define itjc_pib_2_pci(a)                                               \
 332 (                                                                       \
 333         (((a) & PIB_LO_ADDR_MASK) << PIB_LO_ADDR_SHIFT) + PIB_OFFSET    \
 334 )
 335
 336 #define itjc_get_dma_offset(ctx,reg)                                    \
 337 (                                                                       \
 338         (u_int16_t)((bus_addr_t)itjc_read_4((reg)) - (ctx)->bus_addr)   \
 339 )
 340
 341
 342 /*
 343  * IOM-2 serial channel 0 DMA data ring buffers.
 344  *
 345  * The Tiger300/320 ASIC do not nothing more than transfer via DMA the
 346  * first 32 bits of every IOM-2 frame on the serial interface to the
 347  * ISAC. So we have no framing/deframing facilities like we would have
 348  * with an HSCX, having to do the job with CPU cycles. On the plus side
 349  * we are able to specify large rings which can limit the occurrence of
 350  * over/underruns.
 351  */
 352
 353 enum
 354 {
 355         ITJC_RING_SLOT_WORDS    = 64,
 356         ITJC_RING_WORDS         = 3 * ITJC_RING_SLOT_WORDS,
 357         ITJC_RING_SLOT_BYTES    = 4 * ITJC_RING_SLOT_WORDS,
 358         ITJC_RING_BYTES         = 4 * ITJC_RING_WORDS,
 359         ITJC_DMA_POOL_WORDS     = 2 * ITJC_RING_WORDS,
 360         ITJC_DMA_POOL_BYTES     = 4 * ITJC_DMA_POOL_WORDS
 361 };
 362
 363 #define itjc_ring_add(x, d)     (((x) + 4 * (d)) % ITJC_RING_BYTES)
 364 #define itjc_ring_sub(x, d)     (((x) + ITJC_RING_BYTES - 4 * (d))      \
 365                                         % ITJC_RING_BYTES)
 366
 367
 368 enum
 369 {
 370         TIGER_CH_A              = 0,
 371         TIGER_CH_B              = 1,
 372
 373         HSCX_CH_A               = 0,    /* For compatibility reasons. */
 374         HSCX_CH_B               = 1,
 375 };
 376
 377 enum
 378 {
 379         ITJC_TEL_SILENCE_BYTE   = 0x00,
 380         ITJC_HDLC_FLAG_BYTE     = 0x7E,
 381         ITJC_HDLC_ABORT_BYTE    = 0xFF
 382 };
 383
 384 /*
 385  * Hardware DMA control block (one per card).
 386  */
 387 typedef enum
 388 {
 389         ITJC_DS_LOAD_FAILED     = -1,
 390         ITJC_DS_FREE            =  0,
 391         ITJC_DS_LOADING,
 392         ITJC_DS_STOPPED,
 393         ITJC_DS_RUNNING
 394 }
 395         dma_state_t;
 396
 397 typedef struct
 398 {
 399         dma_state_t     state;
 400         u_int8_t        *pool;
 401         bus_addr_t      bus_addr;
 402         bus_dma_tag_t   tag;
 403         bus_dmamap_t    map;
 404         int             error;
 405 }
 406         dma_context_t;
 407
 408 dma_context_t
 409         dma_context     [ ITJC_MAXUNIT ];
 410
 411 /*
 412  * B-channel DMA control blocks (4 per card -- 1 RX & 1 TX per channel).
 413  */
 414 typedef enum
 415 {
 416         ITJC_RS_IDLE    = 0,
 417         ITJC_RS_ACTIVE
 418 }
 419         dma_rx_state_t;
 420
 421 typedef enum
 422 {
 423         ITJC_TS_IDLE    = 0,
 424         ITJC_TS_ACTIVE,
 425         ITJC_TS_AFTER_XDU
 426 }
 427         dma_tx_state_t;
 428
 429 typedef struct
 430 {
 431         u_int8_t        *ring;
 432         bus_addr_t      bus_addr;
 433         u_int16_t       next_read;
 434         u_int16_t       hdlc_len;
 435         u_int16_t       hdlc_tmp;
 436         u_int16_t       hdlc_crc;
 437         u_int16_t       hdlc_ib;
 438         u_int8_t        hdlc_blevel;
 439         u_int8_t        hdlc_flag;
 440         dma_rx_state_t  state;
 441 }
 442         dma_rx_context_t;
 443
 444 typedef struct
 445 {
 446         u_int8_t        *ring;
 447         bus_addr_t      bus_addr;
 448         u_int16_t       next_write;
 449         u_int32_t       hdlc_tmp;
 450         u_int16_t       hdlc_blevel;
 451         u_int16_t       hdlc_crc;
 452         u_int16_t       hdlc_ib;
 453         u_int16_t       next_frame;
 454         u_int16_t       filled;
 455         u_int8_t        hdlc_flag;
 456         dma_tx_state_t  state;
 457 }
 458         dma_tx_context_t;
 459
 460 dma_rx_context_t
 461         dma_rx_context  [ ITJC_MAXUNIT ] [ 2 ];
 462
 463 dma_tx_context_t
 464         dma_tx_context  [ ITJC_MAXUNIT ] [ 2 ];
 465
 466 /*
 467  * Used by the mbuf handling functions.
 468  */
 469 typedef enum
 470 {
 471         ITJC_MB_CURR = 0,
 472         ITJC_MB_NEXT = 1,
 473         ITJC_MB_NEW  = 2
 474 }
 475         which_mb_t;
 476
 477
 478 /*---------------------------------------------------------------------------*
 479  *      itjc_map_callback - get DMA bus address from resource mgr.
 480  *---------------------------------------------------------------------------*/
 481 static void
 482 itjc_map_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 483 {
 484         dma_context_t           *ctx = (dma_context_t *)arg;
 485
 486         if (error)
 487         {
 488                 ctx->error = error;
 489                 ctx->state = ITJC_DS_LOAD_FAILED;
 490                 return;
 491         }
 492
 493         ctx->bus_addr = segs->ds_addr;
 494         ctx->state = ITJC_DS_STOPPED;
 495 }
 496
 497
 498 /*---------------------------------------------------------------------------*
 499  *      itjc_dma_start - Complete DMA setup & start the Tiger DMA engine.
 500  *---------------------------------------------------------------------------*/
 501 static int
 502 itjc_dma_start(struct l1_softc *sc)
 503 {
 504         int                     unit    = sc->sc_unit;
 505         dma_context_t           *ctx    = &dma_context[unit];
 506         dma_rx_context_t        *rxc    = &dma_rx_context[unit][0];
 507         dma_tx_context_t        *txc    = &dma_tx_context[unit][0];
 508         bus_addr_t              ba;
 509         u_int8_t                i;
 510         u_int32_t               *pool_end,
 511                                 *ip;
 512
 513         itjc_bus_setup(sc);
 514
 515         /* See if it is already running. */
 516
 517         if (ctx->state == ITJC_DS_RUNNING)
 518                 return 0;
 519
 520         if (ctx->state == ITJC_DS_LOAD_FAILED)
 521         {
 522                 NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA map loading "
 523                         "failed (error=%d).\n", unit, ctx->error);
 524                 return 1;
 525         }
 526
 527         if (ctx->state != ITJC_DS_STOPPED)
 528         {
 529                 NDBGL1(L1_ERROR, "itjc%d: dma_start: Unexpected DMA "
 530                         "state (%d).\n", unit, ctx->state);
 531                 return 1;
 532         }
 533
 534         /*
 535          * Initialize the DMA control structures (hardware & B-channel).
 536          */
 537         ba = ctx->bus_addr;
 538
 539         txc->ring = ctx->pool + TIGER_CH_A;
 540         rxc->ring = ctx->pool + TIGER_CH_A + ITJC_RING_BYTES;
 541
 542         txc->bus_addr = ba;
 543         rxc->bus_addr = ba + ITJC_RING_BYTES;
 544
 545         ++rxc; ++txc;
 546
 547         txc->ring = ctx->pool + TIGER_CH_B;
 548         rxc->ring = ctx->pool + TIGER_CH_B + ITJC_RING_BYTES;
 549
 550         txc->bus_addr = ba;
 551         rxc->bus_addr = ba + ITJC_RING_BYTES;
 552
 553         /*
 554          * Fill the DMA ring buffers with IOM-2 channel 0 frames made of
 555          * idle/abort sequences for the B & D channels and NOP for IOM-2
 556          * cmd/ind, monitor handshake & data.
 557          */
 558         pool_end = (u_int32_t *)ctx->pool + ITJC_DMA_POOL_WORDS;
 559         for (ip = (u_int32_t *)ctx->pool; ip < pool_end; ++ip)
 560                 *ip = 0xFFFFFFFF;
 561
 562         /*
 563          * Program the Tiger DMA gears.
 564          */
 565
 566         itjc_write_4(TIGER_DMA_WR_START_ADDR, ba);
 567         itjc_write_4(TIGER_DMA_WR_INT_ADDR, ba + ITJC_RING_SLOT_BYTES - 4);
 568         itjc_write_4(TIGER_DMA_WR_END_ADDR, ba + ITJC_RING_BYTES - 4);
 569
 570         ba += ITJC_RING_BYTES;
 571
 572         itjc_write_4(TIGER_DMA_RD_START_ADDR, ba);
 573         itjc_write_4(TIGER_DMA_RD_INT_ADDR, ba + ITJC_RING_SLOT_BYTES * 2 - 4);
 574         itjc_write_4(TIGER_DMA_RD_END_ADDR, ba + ITJC_RING_BYTES - 4);
 575
 576         itjc_write_1(TIGER_INT0_MASK,
 577                 TIGER_WR_END_INT | TIGER_WR_INT_INT | TIGER_RD_INT_INT);
 578
 579         itjc_write_1(TIGER_DMA_OPER, TIGER_ENABLE_DMA);
 580
 581         /*
 582          * See if it really started.
 583          */
 584         ba = itjc_read_4(TIGER_DMA_RD_CURR_ADDR);
 585         for (i = 0; i < 10; ++i)
 586         {
 587                 DELAY(SEC_DELAY/1000);
 588                 if (ba != itjc_read_4(TIGER_DMA_RD_CURR_ADDR))
 589                 {
 590                         ctx->state = ITJC_DS_RUNNING;
 591                         return 0;
 592                 }
 593         }
 594
 595         NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA start failed.\n ", unit);
 596         return 1;
 597 }
 598
 599
 600 /*---------------------------------------------------------------------------*
 601  *      itjc_dma_stop - Stop the Tiger DMA engine.
 602  *---------------------------------------------------------------------------*/
 603 static void
 604 itjc_dma_stop(struct l1_softc *sc)
 605 {
 606         dma_context_t           *ctx    = &dma_context[sc->sc_unit];
 607
 608         itjc_bus_setup(sc);
 609
 610         /* Only stop the DMA if it is running. */
 611
 612         if (ctx->state != ITJC_DS_RUNNING)
 613                 return;
 614
 615         itjc_write_1(TIGER_DMA_OPER, TIGER_DISABLE_DMA);
 616         DELAY(SEC_DELAY/1000);
 617
 618         ctx->state = ITJC_DS_STOPPED;
 619 }
 620
 621
 622 /*---------------------------------------------------------------------------*
 623  *      itjc_bchannel_dma_setup - The DMA side of itjc_bchannel_setup.
 624  *---------------------------------------------------------------------------*/
 625 static void
 626 itjc_bchannel_dma_setup(struct l1_softc *sc, int h_chan, int activate)
 627 {
 628         dma_rx_context_t        *rxc  = &dma_rx_context[sc->sc_unit][h_chan];
 629         dma_tx_context_t        *txc  = &dma_tx_context[sc->sc_unit][h_chan];
 630
 631         l1_bchan_state_t        *chan = &sc->sc_chan[h_chan];
 632
 633         u_int8_t                fill_byte,
 634                                 *ring_end,
 635                                 *cp;
 636
 637         int                     s = SPLI4B();
 638
 639         itjc_bus_setup(sc);
 640
 641         if (activate)
 642         {
 643                 /*
 644                  * Get the DMA engine going if it's not running already.
 645                  */
 646                 itjc_dma_start(sc);
 647
 648                 rxc->hdlc_len   = rxc->hdlc_tmp    = rxc->hdlc_crc  = 0;
 649                 rxc->hdlc_ib    = rxc->hdlc_blevel = rxc->hdlc_flag = 0;
 650
 651                 txc->hdlc_tmp   = txc->hdlc_blevel = txc->hdlc_crc  = 0;
 652                 txc->hdlc_ib    = 0;
 653                 txc->hdlc_flag  = 2;
 654                 txc->filled     = 0;
 655
 656                 if (chan->bprot == BPROT_NONE)
 657                         fill_byte = ITJC_TEL_SILENCE_BYTE;
 658                 else
 659                         fill_byte = ITJC_HDLC_ABORT_BYTE;
 660
 661                 ring_end = rxc->ring + ITJC_RING_BYTES;
 662                 for (cp = rxc->ring; cp < ring_end; cp += 4)
 663                         *cp = fill_byte;
 664
 665                 ring_end = txc->ring + ITJC_RING_BYTES;
 666                 for (cp = txc->ring; cp < ring_end; cp += 4)
 667                         *cp = fill_byte;
 668
 669                 rxc->next_read  =
 670                         itjc_get_dma_offset(rxc, TIGER_DMA_RD_CURR_ADDR);
 671
 672                 txc->next_frame = txc->next_write =
 673                         itjc_get_dma_offset(txc, TIGER_DMA_WR_CURR_ADDR);
 674
 675                 rxc->state      = ITJC_RS_ACTIVE;
 676                 txc->state      = ITJC_TS_AFTER_XDU;
 677         }
 678         else
 679         {
 680                 dma_rx_context_t        *rxc2;
 681
 682                 txc->state      = ITJC_TS_IDLE;
 683                 rxc->state      = ITJC_RS_IDLE;
 684
 685                 rxc2 = &dma_rx_context[sc->sc_unit][0];
 686
 687                 if (rxc2->state == ITJC_RS_IDLE
 688                 && rxc2[1].state == ITJC_RS_IDLE)
 689                         itjc_dma_stop(sc);
 690         }
 691
 692         splx(s);
 693 }
 694
 695
 696 /*---------------------------------------------------------------------------*
 697  *      Mbuf & if_queues management routines.
 698  *---------------------------------------------------------------------------*/
 699
 700 static u_int8_t *
 701 itjc_get_rx_mbuf(l1_bchan_state_t *chan, u_int8_t **dst_end_p,
 702 which_mb_t which)
 703 {
 704         struct mbuf     *mbuf = chan->in_mbuf;
 705
 706         if (mbuf == NULL && which == ITJC_MB_NEW)
 707         {
 708                 if ((mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 709                         panic("itjc_get_rx_mbuf: cannot allocate mbuf!");
 710
 711                 chan->in_mbuf  = mbuf;
 712                 chan->in_cbptr = (u_int8_t *)mbuf->m_data;
 713                 chan->in_len   = 0;
 714         }
 715
 716         if (dst_end_p != NULL)
 717         {
 718                 if (mbuf != NULL)
 719                         *dst_end_p = (u_int8_t *)(mbuf->m_data)
 720                                 + BCH_MAX_DATALEN;
 721                 else
 722                         *dst_end_p = NULL;
 723         }
 724
 725         return chan->in_cbptr;
 726 }
 727
 728
 729 static void
 730 itjc_save_rx_mbuf(l1_bchan_state_t *chan, u_int8_t * dst)
 731 {
 732         struct mbuf     *mbuf = chan->in_mbuf;
 733
 734         if (dst != NULL && mbuf != NULL)
 735         {
 736                 chan->in_cbptr = dst;
 737                 chan->in_len   = dst - (u_int8_t *)mbuf->m_data;
 738         }
 739         else if (dst == NULL && mbuf == NULL)
 740         {
 741                 chan->in_cbptr = NULL;
 742                 chan->in_len   = 0;
 743         }
 744         else
 745                 panic("itjc_save_rx_mbuf: stale pointer dst=%p mbuf=%p "
 746                         "in_cbptr=%p in_len=%d", dst, mbuf,
 747                         chan->in_cbptr, chan->in_len);
 748 }
 749
 750
 751 static void
 752 itjc_free_rx_mbuf(l1_bchan_state_t *chan)
 753 {
 754         struct mbuf     *mbuf = chan->in_mbuf;
 755
 756         if (mbuf != NULL)
 757                 i4b_Bfreembuf(mbuf);
 758
 759         chan->in_mbuf  = NULL;
 760         chan->in_cbptr = NULL;
 761         chan->in_len   = 0;
 762 }
 763
 764
 765 static void
 766 itjc_put_rx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan, u_int16_t len)
 767 {
 768         i4b_trace_hdr_t hdr;
 769         struct mbuf     *mbuf    = chan->in_mbuf;
 770         u_int8_t        *data    = mbuf->m_data;
 771         int             activity = 1;
 772
 773         mbuf->m_pkthdr.len = mbuf->m_len = len;
 774
 775         if (sc->sc_trace & TRACE_B_RX)
 776         {
 777                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
 778                 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 779                 hdr.dir = FROM_NT;
 780                 hdr.count = ++sc->sc_trace_bcount;
 781                 MICROTIME(hdr.time);
 782                 i4b_l1_trace_ind(&hdr, len, data);
 783         }
 784
 785         if (chan->bprot == BPROT_NONE)
 786         {
 787                 activity = ! i4b_l1_bchan_tel_silence(data, len);
 788
 789                 /* move rx'd data to rx queue */
 790
 791                 if (! _IF_QFULL(&chan->rx_queue))
 792                 {
 793                         IF_ENQUEUE(&chan->rx_queue, mbuf);
 794                 }
 795                 else
 796                 {
 797                         i4b_Bfreembuf(mbuf);
 798                         len = 0;
 799                 }
 800         }
 801
 802         if (len != 0)
 803         {
 804                 chan->rxcount += len;
 805
 806                 (*chan->isic_drvr_linktab->bch_rx_data_ready)
 807                         (chan->isic_drvr_linktab->unit);
 808         }
 809
 810         if (activity)
 811                 (*chan->isic_drvr_linktab->bch_activity)
 812                         (chan->isic_drvr_linktab->unit, ACT_RX);
 813
 814         chan->in_mbuf  = NULL;
 815         chan->in_cbptr = NULL;
 816         chan->in_len   = 0;
 817 }
 818
 819
 820 #define itjc_free_tx_mbufs(chan)                                        \
 821 {                                                                       \
 822         i4b_Bfreembuf((chan)->out_mbuf_head);                           \
 823         (chan)->out_mbuf_cur = (chan)->out_mbuf_head = NULL;            \
 824         (chan)->out_mbuf_cur_ptr = NULL;                                \
 825         (chan)->out_mbuf_cur_len = 0;                                   \
 826 }
 827
 828
 829 static u_int16_t
 830 itjc_get_tx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan,
 831         u_int8_t **src_p, which_mb_t which)
 832 {
 833         i4b_trace_hdr_t hdr;
 834         struct mbuf     *mbuf = chan->out_mbuf_cur;
 835         u_int8_t        activity = 1;
 836         u_int16_t       len;
 837         void            *data;
 838
 839         switch (which)
 840         {
 841         case ITJC_MB_CURR:
 842                 if (mbuf != NULL)
 843                 {
 844                         *src_p = chan->out_mbuf_cur_ptr;
 845                         return   chan->out_mbuf_cur_len;
 846                 }
 847
 848                 break;
 849
 850         case ITJC_MB_NEXT:
 851                 if (mbuf != NULL)
 852                 {
 853                         chan->txcount += mbuf->m_len;
 854
 855                         mbuf = mbuf->m_next;
 856
 857                         if (mbuf != NULL)
 858                                 goto new_mbuf;
 859                 }
 860
 861                 chan->out_mbuf_cur_ptr = *src_p = NULL;
 862                 chan->out_mbuf_cur_len = 0;
 863
 864                 if (chan->out_mbuf_head != NULL)
 865                 {
 866                         i4b_Bfreembuf(chan->out_mbuf_head);
 867                         chan->out_mbuf_head = NULL;
 868                 }
 869
 870                 return 0;
 871
 872         case ITJC_MB_NEW:
 873                 if (mbuf != NULL)
 874                         chan->txcount += mbuf->m_len;
 875         }
 876
 877         if (chan->out_mbuf_head != NULL)
 878                 i4b_Bfreembuf(chan->out_mbuf_head);
 879
 880         IF_DEQUEUE(&chan->tx_queue, mbuf);
 881
 882         if (mbuf == NULL)
 883         {
 884                 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 885                 chan->out_mbuf_cur_ptr = *src_p = NULL;
 886                 chan->out_mbuf_cur_len = 0;
 887
 888                 chan->state &= ~(HSCX_TX_ACTIVE);
 889
 890                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)
 891                         (chan->isic_drvr_linktab->unit);
 892
 893                 return 0;
 894         }
 895
 896         chan->out_mbuf_head = mbuf;
 897
 898 new_mbuf:
 899         chan->out_mbuf_cur      = mbuf;
 900         chan->out_mbuf_cur_ptr  = data = mbuf->m_data;
 901         chan->out_mbuf_cur_len  = len  = mbuf->m_len;
 902
 903         chan->state |= HSCX_TX_ACTIVE;
 904
 905         if (sc->sc_trace & TRACE_B_TX)
 906         {
 907                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
 908                 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 909                 hdr.dir = FROM_TE;
 910                 hdr.count = ++sc->sc_trace_bcount;
 911                 MICROTIME(hdr.time);
 912                 i4b_l1_trace_ind(&hdr, len, data);
 913         }
 914
 915         if (chan->bprot == BPROT_NONE)
 916                 activity = ! i4b_l1_bchan_tel_silence(data, len);
 917
 918         if (activity)
 919                 (*chan->isic_drvr_linktab->bch_activity)
 920                         (chan->isic_drvr_linktab->unit, ACT_TX);
 921
 922         *src_p = data;
 923         return len;
 924 }
 925
 926
 927 #define itjc_save_tx_mbuf(chan, src, dst)                               \
 928 (                                                                       \
 929         (chan)->out_mbuf_cur != NULL ?                                  \
 930         (                                                               \
 931                 (chan)->out_mbuf_cur_ptr = (src),                       \
 932                 (chan)->out_mbuf_cur_len = (len)                        \
 933         )                                                               \
 934         :                                                               \
 935                 0                                                       \
 936 )
 937
 938
 939 /*---------------------------------------------------------------------------*
 940  *      B-channel interrupt service routines.
 941  *---------------------------------------------------------------------------*/
 942
 943 /*
 944  * Since the Tiger ASIC doesn't produce a XMIT underflow indication,
 945  * we need to deduce it ourselves. This is somewhat tricky because we
 946  * are dealing with modulo m arithmetic. The idea here is to have a
 947  * "XDU zone" ahead of the writing pointer sized 1/3 of total ring
 948  * length (a ring slot). If the hardware DMA pointer is found there we
 949  * consider that a XDU has occurred. To complete the scheme, we never
 950  * let the ring have more than 2 slots of (unsent) data and adjust the
 951  * interrupt registers to cause an interrupt at every slot.
 952  */
 953 static u_int8_t
 954 itjc_xdu(struct l1_softc *sc, l1_bchan_state_t *chan, dma_tx_context_t *ctx,
 955 u_int16_t *dst_p, u_int16_t *dst_end_p, u_int8_t tx_restart)
 956 {
 957         u_int8_t        xdu;
 958
 959         u_int16_t       dst_end,
 960                         dst,
 961                         dma,
 962                         dma_l,
 963                         dma_h,
 964                         xdu_l,
 965                         xdu_h;
 966
 967         itjc_bus_setup(sc);
 968
 969         /*
 970          * Since the hardware is running, be conservative and assume
 971          * the pointer location has a `fuzy' error factor.
 972          */
 973         dma   = itjc_get_dma_offset(ctx, TIGER_DMA_WR_CURR_ADDR);
 974         dma_l = dma;
 975         dma_h = itjc_ring_add(dma, 1);
 976
 977         dst_end = itjc_ring_sub(dma_l, ITJC_RING_SLOT_WORDS);
 978
 979         if (ctx->state != ITJC_TS_ACTIVE)
 980         {
 981                 xdu = (ctx->state == ITJC_TS_AFTER_XDU);
 982                 dst = itjc_ring_add(dma_h, 4);
 983                 goto done;
 984         }
 985
 986         /*
 987          * Check for xmit underruns.
 988          */
 989         xdu_l = dst = ctx->next_write;
 990         xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
 991
 992         if (xdu_l < xdu_h)
 993                 xdu =      (xdu_l <= dma_l && dma_l < xdu_h)
 994                         || (xdu_l <= dma_h && dma_h < xdu_h);
 995         else
 996                 xdu =      (xdu_l <= dma_l || dma_l < xdu_h)
 997                         || (xdu_l <= dma_h || dma_h < xdu_h);
 998
 999         if (xdu)
1000         {
1001                 ctx->state = ITJC_TS_AFTER_XDU;
1002
1003                 dst = itjc_ring_add(dma_h, 4);
1004         }
1005         else if (tx_restart)
1006         {
1007                 /*
1008                  * See if we still can restart from immediately
1009                  * after the last frame sent. It's a XDU test but
1010                  * using the real data end on the comparsions. We
1011                  * don't consider XDU an error here because we were
1012                  * just trying to avoid send a filling gap between
1013                  * frames. If it's already sent no harm is done.
1014                  */
1015                 xdu_l = dst = ctx->next_frame;
1016                 xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
1017
1018                 if (xdu_l < xdu_h)
1019                         xdu =      (xdu_l <= dma_l && dma_l < xdu_h)
1020                                 || (xdu_l <= dma_h && dma_h < xdu_h);
1021                 else
1022                         xdu =      (xdu_l <= dma_l || dma_l < xdu_h)
1023                                 || (xdu_l <= dma_h || dma_h < xdu_h);
1024
1025                 if (xdu)
1026                         dst = itjc_ring_add(dma_h, 4);
1027
1028                 xdu = 0;
1029         }
1030
1031 done:
1032         if (dst_p != NULL)
1033                 *dst_p = dst;
1034
1035         if (dst_end_p != NULL)
1036                 *dst_end_p = dst_end;
1037
1038         ctx->next_write = dst_end;
1039
1040         return xdu;
1041 }
1042
1043
1044 #define itjc_rotate_hdlc_flag(blevel)                                   \
1045         ((u_int8_t)(0x7E7E >> (8 - (u_int8_t)((blevel) >> 8))))
1046
1047
1048 static void
1049 itjc_dma_rx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1050 dma_rx_context_t *ctx)
1051 {
1052         u_int8_t        *ring,
1053                         *dst,
1054                         *dst_end,
1055                         flag,
1056                         blevel;
1057
1058         u_int16_t       dma,
1059                         src,
1060                         tmp2,
1061                         tmp,
1062                         len,
1063                         crc,
1064                         ib;
1065
1066         itjc_bus_setup(sc);
1067
1068
1069         if (ctx->state == ITJC_RS_IDLE)
1070                 return;
1071
1072         ring = ctx->ring;
1073         dma = itjc_get_dma_offset(ctx, TIGER_DMA_RD_CURR_ADDR);
1074         dma = itjc_ring_sub(dma, 1);
1075         src = ctx->next_read;
1076
1077         if (chan->bprot == BPROT_NONE)
1078         {
1079                 dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_CURR);
1080
1081                 while (src != dma)
1082                 {
1083                         if (dst == NULL)
1084                                 dst = itjc_get_rx_mbuf(chan, &dst_end,
1085                                         ITJC_MB_NEW);
1086
1087                         *dst++ = ring[src];
1088                         src = itjc_ring_add(src, 1);
1089
1090                         if (dst >= dst_end)
1091                         {
1092                                 itjc_put_rx_mbuf(sc, chan, BCH_MAX_DATALEN);
1093                                 dst = dst_end = NULL;
1094                         }
1095                 }
1096                 ctx->next_read = src;
1097                 itjc_save_rx_mbuf(chan, dst);
1098                 return;
1099         }
1100
1101         blevel = ctx->hdlc_blevel;
1102         flag   = ctx->hdlc_flag;
1103         len    = ctx->hdlc_len;
1104         tmp    = ctx->hdlc_tmp;
1105         crc    = ctx->hdlc_crc;
1106         ib     = ctx->hdlc_ib;
1107
1108         dst = itjc_get_rx_mbuf(chan, NULL, ITJC_MB_CURR);
1109
1110         while (src != dma)
1111         {
1112                 HDLC_DECODE(*dst++, len, tmp, tmp2, blevel, ib, crc, flag,
1113                 {/* rdd */
1114                         tmp2 = ring[src];
1115                         src = itjc_ring_add(src, 1);
1116                 },
1117                 {/* nfr */
1118                         if (dst != NULL)
1119                                 panic("itjc_dma_rx_intr: nfrcmd with "
1120                                         "valid current frame");
1121
1122                         dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_NEW);
1123                         len = dst_end - dst;
1124                 },
1125                 {/* cfr */
1126                         len = BCH_MAX_DATALEN - len;
1127
1128                         if ((!len) || (len > BCH_MAX_DATALEN))
1129                         {
1130                                 /*
1131                                  * NOTE: frames without any data, only crc
1132                                  * field, should be silently discared.
1133                                  */
1134                                 NDBGL1(L1_S_MSG, "itjc_dma_rx_intr: "
1135                                         "bad frame (len=%d, unit=%d)",
1136                                         len, sc->sc_unit);
1137
1138                                 itjc_free_rx_mbuf(chan);
1139
1140                                 goto s0;
1141                         }
1142
1143                         if (crc)
1144                         {
1145                                 NDBGL1(L1_S_ERR,
1146                                         "CRC (crc=0x%04x, len=%d, unit=%d)",
1147                                         crc, len, sc->sc_unit);
1148
1149                                 itjc_free_rx_mbuf(chan);
1150
1151                                 goto s0;
1152                         }
1153
1154                         itjc_put_rx_mbuf(sc, chan, len);
1155
1156                 s0:
1157                         dst = NULL;
1158                         len = 0;
1159                 },
1160                 {/* rab */
1161                         NDBGL1(L1_S_ERR, "Read Abort (unit=%d)", sc->sc_unit);
1162
1163                         itjc_free_rx_mbuf(chan);
1164                         dst = NULL;
1165                         len = 0;
1166                 },
1167                 {/* rdo */
1168                         NDBGL1(L1_S_ERR, "RDO (unit=%d) dma=%d src=%d",
1169                                 sc->sc_unit, dma, src);
1170
1171                         itjc_free_rx_mbuf(chan);
1172                         dst = NULL;
1173                         len = 0;
1174                 },
1175                 continue,
1176                 d);
1177         }
1178
1179         itjc_save_rx_mbuf(chan, dst);
1180
1181         ctx->next_read  = src;
1182         ctx->hdlc_blevel= blevel;
1183         ctx->hdlc_flag  = flag;
1184         ctx->hdlc_len   = len;
1185         ctx->hdlc_tmp   = tmp;
1186         ctx->hdlc_crc   = crc;
1187         ctx->hdlc_ib    = ib;
1188 }
1189
1190
1191 /*
1192  * The HDLC side of itjc_dma_tx_intr. We made a separate function
1193  * to improve readability and (perhaps) help the compiler with
1194  * register allocation.
1195  */
1196 static void
1197 itjc_hdlc_encode(struct l1_softc *sc, l1_bchan_state_t *chan,
1198 dma_tx_context_t * ctx)
1199 {
1200         u_int8_t        *ring,
1201                         *src,
1202                         xdu,
1203                         flag,
1204                         flag_byte,
1205                         tx_restart;
1206
1207         u_int16_t       saved_len,
1208                         dst_end,
1209                         dst_end1,
1210                         dst,
1211                         filled,
1212                         blevel,
1213                         tmp2,
1214                         len,
1215                         crc,
1216                         ib;
1217
1218         u_int32_t       tmp;
1219
1220
1221         saved_len = len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1222
1223         filled = ctx->filled;
1224         flag   = ctx->hdlc_flag;
1225
1226         if (src == NULL && flag == 2 && filled >= ITJC_RING_WORDS)
1227                 return;
1228
1229         tx_restart = (flag == 2 && src != NULL);
1230         xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, tx_restart);
1231
1232         ring   = ctx->ring;
1233
1234         ib     = ctx->hdlc_ib;
1235         crc    = ctx->hdlc_crc;
1236         tmp    = ctx->hdlc_tmp;
1237         blevel = ctx->hdlc_blevel;
1238
1239         if (xdu)
1240         {
1241                 if (flag != 2)
1242                 {
1243                         NDBGL1(L1_H_XFRERR, "XDU");
1244                         ++chan->stat_XDU;
1245
1246                         /*
1247                          * Abort the current frame and
1248                          * prepare for a full restart.
1249                          */
1250                         itjc_free_tx_mbufs(chan);
1251                         saved_len = len = filled = 0;
1252                         flag = (u_int8_t)-2;
1253                 }
1254                 else if (filled < ITJC_RING_SLOT_WORDS)
1255                 {
1256                         /*
1257                          * A little garbage may have been retransmitted.
1258                          * Send an abort before any new data.
1259                          */
1260                         filled = 0;
1261                         flag = (u_int8_t)-2;
1262                 }
1263         }
1264
1265         if (flag != 3)
1266                 len = 0;
1267
1268         while (dst != dst_end)
1269         {
1270                 HDLC_ENCODE(
1271                 *src++, len, tmp, tmp2, blevel, ib, crc, flag,
1272                 {/* gfr */
1273                         if ((len = saved_len) == 0)
1274                                 len = itjc_get_tx_mbuf(sc, chan, &src,
1275                                         ITJC_MB_NEW);
1276
1277                         if (len == 0)
1278                         {
1279                                 ctx->next_frame = dst;
1280
1281                                 flag_byte = itjc_rotate_hdlc_flag(blevel);
1282
1283                                 for (dst_end1 = itjc_ring_sub(dst_end, 1);
1284                                 dst != dst_end1;
1285                                 dst = itjc_ring_add(dst, 1))
1286                                 {
1287                                         ring[dst] = flag_byte;
1288                                         ++filled;
1289                                 }
1290                         }
1291                         else
1292                                 filled = 0;
1293
1294                         ctx->state = ITJC_TS_ACTIVE;
1295                 },
1296                 {/* nmb */
1297                         saved_len = 0;
1298                         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1299                 },
1300                 {/* wrd */
1301                         ring[dst] = (u_int8_t)tmp;
1302                         dst = itjc_ring_add(dst, 1);
1303                 },
1304                 d1);
1305         }
1306
1307         ctx->hdlc_blevel = blevel;
1308         ctx->hdlc_flag   = flag;
1309         ctx->hdlc_tmp    = tmp;
1310         ctx->hdlc_crc    = crc;
1311         ctx->hdlc_ib     = ib;
1312
1313         ctx->filled = filled;
1314         ctx->next_write = dst;
1315
1316         itjc_save_tx_mbuf(chan, src, len);
1317 }
1318
1319
1320 static void
1321 itjc_dma_tx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1322 dma_tx_context_t * ctx)
1323 {
1324         u_int8_t        *data_end,
1325                         *ring,
1326                         *src,
1327                         xdu;
1328
1329         u_int16_t       dst,
1330                         dst_end,
1331                         filled,
1332                         len;
1333
1334
1335         if (ctx->state == ITJC_TS_IDLE)
1336                 goto done;
1337
1338         if (chan->bprot != BPROT_NONE)
1339         {
1340                 itjc_hdlc_encode(sc, chan, ctx);
1341                 goto done;
1342         }
1343
1344         ring   = ctx->ring;
1345         filled = ctx->filled;
1346
1347         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1348
1349         if (len == 0 && filled >= ITJC_RING_WORDS)
1350                 goto done;
1351
1352         xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, len != 0);
1353
1354         if (xdu && filled < ITJC_RING_WORDS)
1355         {
1356                 NDBGL1(L1_H_XFRERR, "XDU");
1357                 ++chan->stat_XDU;
1358                 filled = 0;
1359         }
1360
1361         if (len == 0)
1362                 goto fill_ring;
1363
1364         ctx->state = ITJC_TS_ACTIVE;
1365
1366         data_end = src + len;
1367         while (dst != dst_end)
1368         {
1369                 ring[dst] = *src++; --len;
1370
1371                 dst = itjc_ring_add(dst, 1);
1372
1373                 if (src >= data_end)
1374                 {
1375                         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1376                         if (len == 0)
1377                                 len = itjc_get_tx_mbuf(sc, chan,
1378                                          &src, ITJC_MB_NEW);
1379
1380                         if (len == 0)
1381                         {
1382                                 data_end = NULL;
1383                                 break;
1384                         }
1385                         data_end = src + len;
1386                 }
1387         }
1388
1389         itjc_save_tx_mbuf(chan, src, len);
1390
1391         filled = 0;
1392
1393 fill_ring:
1394         ctx->next_frame = dst;
1395
1396         for (; dst != dst_end; dst = itjc_ring_add(dst, 1))
1397         {
1398                 ring[dst] = ITJC_TEL_SILENCE_BYTE;
1399                 ++filled;
1400         }
1401
1402         ctx->next_write = dst;
1403         ctx->filled = filled;
1404
1405 done:
1406         return;
1407 }
1408
1409
1410 /*---------------------------------------------------------------------------*
1411  *      NetJet fifo read/write routines.
1412  *---------------------------------------------------------------------------*/
1413
1414 static void
1415 itjc_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1416 {
1417         itjc_bus_setup(sc);
1418
1419         if (what != ISIC_WHAT_ISAC)
1420                 panic("itjc_write_fifo: Trying to read from HSCX fifo.\n");
1421
1422         itjc_set_pib_addr_msb(0);
1423         itjc_read_multi_1(PIB_OFFSET, buf, size);
1424 }
1425
1426
1427 static void
1428 itjc_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1429 {
1430         itjc_bus_setup(sc);
1431
1432         if (what != ISIC_WHAT_ISAC)
1433                 panic("itjc_write_fifo: Trying to write to HSCX fifo.\n");
1434
1435         itjc_set_pib_addr_msb(0);
1436         itjc_write_multi_1(PIB_OFFSET, buf, size);
1437 }
1438
1439
1440 /*---------------------------------------------------------------------------*
1441  *      Read an ISAC register.
1442  *---------------------------------------------------------------------------*/
1443 static u_int8_t
1444 itjc_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
1445 {
1446         itjc_bus_setup(sc);
1447
1448         if (what != ISIC_WHAT_ISAC)
1449         {
1450                 panic("itjc_read_reg: what(%d) != ISIC_WHAT_ISAC\n",
1451                         what);
1452                 return 0;
1453         }
1454
1455         itjc_set_pib_addr_msb(offs);
1456         return itjc_read_1(itjc_pib_2_pci(offs));
1457 }
1458
1459
1460 /*---------------------------------------------------------------------------*
1461  *      Write an ISAC register.
1462  *---------------------------------------------------------------------------*/
1463 static void
1464 itjc_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
1465 {
1466         itjc_bus_setup(sc);
1467
1468         if (what != ISIC_WHAT_ISAC)
1469         {
1470                 panic("itjc_write_reg: what(%d) != ISIC_WHAT_ISAC\n",
1471                         what);
1472                 return;
1473         }
1474
1475         itjc_set_pib_addr_msb(offs);
1476         itjc_write_1(itjc_pib_2_pci(offs), data);
1477 }
1478
1479
1480 /*---------------------------------------------------------------------------*
1481  *      itjc_probe - probe for a card.
1482  *---------------------------------------------------------------------------*/
1483 static int itjc_probe(device_t dev)
1484 {
1485         u_int16_t       vid = pci_get_vendor(dev),
1486                         did = pci_get_device(dev);
1487
1488         if ((vid == PCI_TJNET_VID) && (did == PCI_TJ300_DID))
1489         {
1490                 device_set_desc(dev, "NetJet-S");
1491                 return 0;
1492         }
1493
1494         return ENXIO;
1495 }
1496
1497
1498 /*---------------------------------------------------------------------------*
1499  *      itjc_attach - attach a (previously probed) card.
1500  *---------------------------------------------------------------------------*/
1501 static int
1502 itjc_attach(device_t dev)
1503 {
1504         bus_space_handle_t      h;
1505         bus_space_tag_t         t;
1506
1507         struct l1_softc         *sc = device_get_softc(dev);
1508
1509         u_int16_t               vid = pci_get_vendor(dev),
1510                                 did = pci_get_device(dev);
1511
1512         int                     unit = device_get_unit(dev),
1513                                 s = splimp(),
1514                                 res_init_level = 0,
1515                                 error = 0;
1516
1517         void                    *ih = 0;
1518
1519         dma_context_t           *ctx = &dma_context[unit];
1520         l1_bchan_state_t        *chan;
1521
1522         bzero(sc, sizeof(struct l1_softc));
1523
1524         /* Probably not really required. */
1525         if (unit >= ITJC_MAXUNIT)
1526         {
1527                 printf("itjc%d: Error, unit >= ITJC_MAXUNIT!\n", unit);
1528                 splx(s);
1529                 return ENXIO;
1530         }
1531
1532         if (!(vid == PCI_TJNET_VID && did == PCI_TJ300_DID))
1533         {
1534                 printf("itjc%d: unknown device (%04X,%04X)!\n", unit, vid, did);
1535                 goto fail;
1536         }
1537
1538         itjc_scp[unit] = sc;
1539
1540         sc->sc_resources.io_rid[0] = PCIR_BAR(0);
1541         sc->sc_resources.io_base[0] = bus_alloc_resource_any(dev,
1542                 SYS_RES_IOPORT, &sc->sc_resources.io_rid[0], RF_ACTIVE);
1543
1544         if (sc->sc_resources.io_base[0] == NULL)
1545         {
1546                 printf("itjc%d: couldn't map IO port\n", unit);
1547                 error = ENXIO;
1548                 goto fail;
1549         }
1550
1551         h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1552         t = rman_get_bustag(sc->sc_resources.io_base[0]);
1553
1554         ++res_init_level;
1555
1556         /* Allocate interrupt. */
1557         sc->sc_resources.irq_rid = 0;
1558         sc->sc_resources.irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1559                 &sc->sc_resources.irq_rid, RF_SHAREABLE | RF_ACTIVE);
1560
1561         if (sc->sc_resources.irq == NULL)
1562         {
1563                 printf("itjc%d: couldn't map interrupt\n", unit);
1564                 error = ENXIO;
1565                 goto fail;
1566         }
1567
1568         ++res_init_level;
1569
1570         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET,
1571                          NULL, itjc_intr, sc, &ih);
1572
1573         if (error)
1574         {
1575                 printf("itjc%d: couldn't set up irq handler\n", unit);
1576                 error = ENXIO;
1577                 goto fail;
1578         }
1579
1580         /*
1581          * Reset the ASIC & the ISAC.
1582          */
1583         itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1584
1585         DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1586
1587         itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1588                 TIGER_SELF_ADDR_DMA | TIGER_PIB_3_CYCLES);
1589
1590         DELAY(SEC_DELAY/100); /* ... and more 10 to recover. */
1591
1592         /*
1593          * First part of DMA initialization. Create & map the memory
1594          * pool that will be used to bear the rx & tx ring buffers.
1595          */
1596         ctx->state = ITJC_DS_LOADING;
1597
1598         error = bus_dma_tag_create(
1599                 NULL,                                   /* parent */
1600                 4,                                      /* alignment*/
1601                 0,                                      /* boundary*/
1602                 BUS_SPACE_MAXADDR_32BIT,                /* lowaddr*/
1603                 BUS_SPACE_MAXADDR,                      /* highaddr*/
1604                 NULL,                                   /* filter*/
1605                 NULL,                                   /* filterarg*/
1606                 ITJC_DMA_POOL_BYTES,                    /* maxsize*/
1607                 1,                                      /* nsegments*/
1608                 ITJC_DMA_POOL_BYTES,                    /* maxsegsz*/
1609                 BUS_DMA_ALLOCNOW | BUS_DMA_COHERENT,    /* flags*/
1610                 NULL, NULL,                             /* lockfuunc, lockarg */
1611                 &ctx->tag);
1612
1613         if (error)
1614         {
1615                 printf("itjc%d: couldn't create bus DMA tag.\n", unit);
1616                 goto fail;
1617         }
1618
1619         ++res_init_level;
1620
1621         error = bus_dmamem_alloc(
1622                 ctx->tag,                               /* DMA tag */
1623                 (void **)&ctx->pool,    /* KV addr of the allocated memory */
1624                 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,      /* flags */
1625                 &ctx->map);                             /* KV <-> PCI map */
1626
1627         if (error)
1628                 goto fail;
1629
1630         /*
1631          * Load the KV <-> PCI map so the device sees the same
1632          * memory segment as pointed by pool. Note: since the
1633          * load may happen assyncronously (completion indicated by
1634          * the execution of the callback function) we have to
1635          * delay the initialization of the DMA engine to a moment we
1636          * actually have the proper bus addresses to feed the Tiger
1637          * and our DMA control blocks. This will be done in
1638          * itjc_bchannel_setup via a call to itjc_dma_start.
1639          */
1640         bus_dmamap_load(
1641                 ctx->tag,               /* DMA tag */
1642                 ctx->map,               /* DMA map */
1643                 ctx->pool,              /* KV addr of buffer */
1644                 ITJC_DMA_POOL_BYTES,    /* buffer size */
1645                 itjc_map_callback,      /* this receive the bus addr/error */
1646                 ctx,                    /* callback aux arg */
1647                 0);                     /* flags */
1648
1649         ++res_init_level;
1650
1651         /*
1652          * Setup the AUX port so we can talk to the ISAC.
1653          */
1654         itjc_write_1(TIGER_AUX_PORT_CNTL, TIGER_AUX_NJ_DEFAULT);
1655         itjc_write_1(TIGER_INT1_MASK, TIGER_ISAC_INT);
1656
1657         /*
1658          * From now on, almost like a `normal' ISIC driver.
1659          */
1660
1661         sc->sc_unit = unit;
1662
1663         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
1664
1665         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
1666         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
1667
1668         /* setup access routines */
1669
1670         sc->clearirq = NULL;
1671         sc->readreg = itjc_read_reg;
1672         sc->writereg = itjc_write_reg;
1673
1674         sc->readfifo = itjc_read_fifo;
1675         sc->writefifo = itjc_write_fifo;
1676
1677         /* setup card type */
1678
1679         sc->sc_cardtyp = CARD_TYPEP_NETJET_S;
1680
1681         /* setup IOM bus type */
1682
1683         sc->sc_bustyp = BUS_TYPE_IOM2;
1684
1685         /* set up some other miscellaneous things */
1686         sc->sc_ipac = 0;
1687         sc->sc_bfifolen = 2 * ITJC_RING_SLOT_WORDS;
1688
1689         printf("itjc%d: ISAC 2186 Version 1.1 (IOM-2)\n", unit);
1690
1691         /* init the ISAC */
1692         itjc_isac_init(sc);
1693
1694         chan = &sc->sc_chan[HSCX_CH_A];
1695         if(!mtx_initialized(&chan->rx_queue.ifq_mtx))
1696                 mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp_rx", NULL, MTX_DEF);
1697         if(!mtx_initialized(&chan->tx_queue.ifq_mtx))
1698                 mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp_tx", NULL, MTX_DEF);
1699         chan = &sc->sc_chan[HSCX_CH_B];
1700         if(!mtx_initialized(&chan->rx_queue.ifq_mtx))
1701                 mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp_rx", NULL, MTX_DEF);
1702         if(!mtx_initialized(&chan->tx_queue.ifq_mtx))
1703                 mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp_tx", NULL, MTX_DEF);
1704
1705         /* init the "HSCX" */
1706         itjc_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
1707
1708         itjc_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
1709
1710         /* can't use the normal B-Channel stuff */
1711         itjc_init_linktab(sc);
1712
1713         /* set trace level */
1714
1715         sc->sc_trace = TRACE_OFF;
1716
1717         sc->sc_state = ISAC_IDLE;
1718
1719         sc->sc_ibuf = NULL;
1720         sc->sc_ib = NULL;
1721         sc->sc_ilen = 0;
1722
1723         sc->sc_obuf = NULL;
1724         sc->sc_op = NULL;
1725         sc->sc_ol = 0;
1726         sc->sc_freeflag = 0;
1727
1728         sc->sc_obuf2 = NULL;
1729         sc->sc_freeflag2 = 0;
1730
1731 #if defined(__FreeBSD__) && __FreeBSD__ >=3
1732         callout_handle_init(&sc->sc_T3_callout);
1733         callout_handle_init(&sc->sc_T4_callout);
1734 #endif
1735
1736         /* init higher protocol layers */
1737
1738         i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_ATTACH,
1739                 sc->sc_cardtyp, &itjc_l1mux_func);
1740
1741         splx(s);
1742         return 0;
1743
1744   fail:
1745         switch (res_init_level)
1746         {
1747         case 5:
1748                 bus_dmamap_unload(ctx->tag, ctx->map);
1749                 /* FALL TRHU */
1750
1751         case 4:
1752                 bus_dmamem_free(ctx->tag, ctx->pool, ctx->map);
1753                 bus_dmamap_destroy(ctx->tag, ctx->map);
1754                 /* FALL TRHU */
1755
1756         case 3:
1757                 bus_dma_tag_destroy(ctx->tag);
1758                 /* FALL TRHU */
1759
1760         case 2:
1761                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
1762                 /* FALL TRHU */
1763
1764         case 1:
1765                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0),
1766                         sc->sc_resources.io_base[0]);
1767                 /* FALL TRHU */
1768
1769         case 0:
1770                 break;
1771         }
1772
1773         itjc_scp[unit] = NULL;
1774
1775         splx(s);
1776         return error;
1777 }
1778
1779
1780 /*---------------------------------------------------------------------------*
1781  *      itjc_intr - main interrupt service routine.
1782  *---------------------------------------------------------------------------*/
1783 static void
1784 itjc_intr(void *xsc)
1785 {
1786         struct l1_softc         *sc     = xsc;
1787         l1_bchan_state_t        *chan   = &sc->sc_chan[0];
1788         dma_context_t           *dma    = &dma_context[sc->sc_unit];
1789         dma_rx_context_t        *rxc    = &dma_rx_context[sc->sc_unit][0];
1790         dma_tx_context_t        *txc    = &dma_tx_context[sc->sc_unit][0];
1791
1792         itjc_bus_setup(sc);
1793
1794         /* Honor interrupts from successfully configured cards only. */
1795         if (dma->state < ITJC_DS_STOPPED)
1796                 return;
1797
1798         /* First, we check the ISAC... */
1799         if (! (itjc_read_1(TIGER_AUX_PORT_DATA) & TIGER_ISAC_INT_MASK))
1800         {
1801                 itjc_write_1(TIGER_INT1_STATUS, TIGER_ISAC_INT);
1802                 NDBGL1(L1_H_IRQ, "ISAC");
1803                 itjc_isac_intr(sc);
1804         }
1805
1806         /* ... after what we always have a look at the DMA rings. */
1807
1808         NDBGL1(L1_H_IRQ, "Tiger");
1809
1810         itjc_read_1(TIGER_INT0_STATUS);
1811         itjc_write_1(TIGER_INT0_STATUS, TIGER_TARGET_ABORT_INT
1812                 | TIGER_MASTER_ABORT_INT | TIGER_RD_END_INT
1813                 | TIGER_RD_INT_INT       | TIGER_WR_END_INT | TIGER_WR_INT_INT);
1814
1815         itjc_dma_rx_intr(sc, chan, rxc);
1816         itjc_dma_tx_intr(sc, chan, txc);
1817
1818         ++chan; ++rxc; ++txc;
1819
1820         itjc_dma_rx_intr(sc, chan, rxc);
1821         itjc_dma_tx_intr(sc, chan, txc);
1822 }
1823
1824
1825 /*---------------------------------------------------------------------------*
1826  *      itjc_bchannel_setup - (Re)initialize and start/stop a Bchannel.
1827  *---------------------------------------------------------------------------*/
1828 static void
1829 itjc_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1830 {
1831 #ifdef __FreeBSD__
1832         struct l1_softc         *sc     = itjc_scp[unit];
1833 #else
1834         struct l1_softc         *sc     = isic_find_sc(unit);
1835 #endif
1836         l1_bchan_state_t        *chan   = &sc->sc_chan[h_chan];
1837         int                     s       = SPLI4B();
1838
1839         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1840                 unit, h_chan, activate ? "activate" : "deactivate");
1841
1842         /*
1843          * If we are deactivating the channel, we have to stop
1844          * the DMA before we reset the channel control structures.
1845          */
1846         if (! activate)
1847                 itjc_bchannel_dma_setup(sc, h_chan, activate);
1848
1849         /* general part */
1850
1851         chan->state = HSCX_IDLE;
1852
1853         chan->unit = sc->sc_unit;       /* unit number */
1854         chan->channel = h_chan;         /* B channel */
1855         chan->bprot = bprot;            /* B channel protocol */
1856
1857         /* receiver part */
1858
1859         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1860
1861         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1862
1863         chan->rxcount = 0;              /* reset rx counter */
1864
1865         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1866
1867         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1868         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1869         chan->in_len = 0;               /* reset mbuf data len */
1870
1871         /* transmitter part */
1872
1873         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1874
1875         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1876
1877         chan->txcount = 0;              /* reset tx counter */
1878
1879         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1880
1881         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1882         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1883         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1884         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1885
1886         /*
1887          * Only setup & start the DMA after all other channel
1888          * control structures are in place.
1889          */
1890         if (activate)
1891                 itjc_bchannel_dma_setup(sc, h_chan, activate);
1892
1893         splx(s);
1894 }
1895
1896
1897 /*---------------------------------------------------------------------------*
1898  *      itjc_bchannel_start - Signal us we have more data to send.
1899  *---------------------------------------------------------------------------*/
1900 static void
1901 itjc_bchannel_start(int unit, int h_chan)
1902 {
1903 #if 0 /* Buggy code */
1904         /*
1905          * I disabled this routine because it was causing crashes when
1906          * this driver was used with the ISP (kernel SPPP) protocol driver.
1907          * The scenario is reproductible:
1908          *      Use the -link1 (dial on demand) ifconfig option.
1909          *      Start an interactive  TCP connection to somewhere.
1910          *      Wait until the PPP connection times out and is dropped.
1911          *      Try to send something on the TCP connection.
1912          *      The machine will print some garbage and halt or reboot
1913          *      (no panic messages).
1914          *
1915          * I've nailed down the problem to the fact that this routine
1916          * was being called before the B channel had been setup again.
1917          *
1918          * For now, I don't have a good solution other than this one.
1919          * But, don't despair. The impact of it is unnoticeable.
1920          */
1921
1922 #ifdef __FreeBSD__
1923         struct l1_softc  *sc    = itjc_scp[unit];
1924 #else
1925         struct l1_softc  *sc    = isic_find_sc(unit);
1926 #endif
1927         l1_bchan_state_t *chan  = &sc->sc_chan[h_chan];
1928
1929         int              s      = SPLI4B();
1930
1931         dma_tx_context_t *txc   = &dma_tx_context[unit][h_chan];
1932
1933         if (chan->state & HSCX_TX_ACTIVE)
1934         {
1935                 splx(s);
1936                 return;
1937         }
1938
1939         itjc_dma_tx_intr(sc, chan, txc);
1940
1941         splx(s);
1942 #endif
1943 }
1944
1945
1946 /*---------------------------------------------------------------------------*
1947  *      itjc_shutdown - Stop the driver and reset the card.
1948  *---------------------------------------------------------------------------*/
1949 static void
1950 itjc_shutdown(device_t dev)
1951 {
1952         struct l1_softc *sc = device_get_softc(dev);
1953
1954         itjc_bus_setup(sc);
1955
1956         /*
1957          * Stop the DMA the nice and easy way.
1958          */
1959         itjc_bchannel_setup(sc->sc_unit, 0, BPROT_NONE, 0);
1960         itjc_bchannel_setup(sc->sc_unit, 1, BPROT_NONE, 0);
1961
1962         /*
1963          * Reset the card.
1964          */
1965         itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1966
1967         DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1968
1969         itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1970                 TIGER_SELF_ADDR_DMA | TIGER_LATCH_DMA_INT | TIGER_PIB_3_CYCLES);
1971
1972         DELAY(SEC_DELAY/100); /* ... and more 10 to recover */
1973 }
1974
1975
1976 /*---------------------------------------------------------------------------*
1977  *      itjc_ret_linktab - Return the address of itjc drivers linktab.
1978  *---------------------------------------------------------------------------*/
1979 isdn_link_t *
1980 itjc_ret_linktab(int unit, int channel)
1981 {
1982 #ifdef __FreeBSD__
1983         struct l1_softc         *sc = itjc_scp[unit];
1984 #else
1985         struct l1_softc         *sc = isic_find_sc(unit);
1986 #endif
1987         l1_bchan_state_t        *chan = &sc->sc_chan[channel];
1988
1989         return(&chan->isic_isdn_linktab);
1990 }
1991
1992 /*---------------------------------------------------------------------------*
1993  *      itjc_set_linktab - Set the driver linktab in the b channel softc.
1994  *---------------------------------------------------------------------------*/
1995 void
1996 itjc_set_linktab(int unit, int channel, drvr_link_t *dlt)
1997 {
1998 #ifdef __FreeBSD__
1999         struct l1_softc *sc     = itjc_scp[unit];
2000 #else
2001         struct l1_softc *sc     = isic_find_sc(unit);
2002 #endif
2003         l1_bchan_state_t *chan  = &sc->sc_chan[channel];
2004
2005         chan->isic_drvr_linktab = dlt;
2006 }
2007
2008
2009 /*---------------------------------------------------------------------------*
2010  *      itjc_init_linktab - Initialize our local linktab.
2011  *---------------------------------------------------------------------------*/
2012 static void
2013 itjc_init_linktab(struct l1_softc *sc)
2014 {
2015         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
2016         isdn_link_t *lt = &chan->isic_isdn_linktab;
2017
2018         /* make sure the hardware driver is known to layer 4 */
2019         /* avoid overwriting if already set */
2020         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
2021         {
2022                 ctrl_types[CTRL_PASSIVE].set_linktab = itjc_set_linktab;
2023                 ctrl_types[CTRL_PASSIVE].get_linktab = itjc_ret_linktab;
2024         }
2025
2026         /* local setup */
2027         lt->unit = sc->sc_unit;
2028         lt->channel = HSCX_CH_A;
2029         lt->bch_config = itjc_bchannel_setup;
2030         lt->bch_tx_start = itjc_bchannel_start;
2031         lt->bch_stat = itjc_bchannel_stat;
2032         lt->tx_queue = &chan->tx_queue;
2033
2034         /* used by non-HDLC data transfers, i.e. telephony drivers */
2035         lt->rx_queue = &chan->rx_queue;
2036
2037         /* used by HDLC data transfers, i.e. ipr and isp drivers */
2038         lt->rx_mbuf = &chan->in_mbuf;
2039
2040         chan = &sc->sc_chan[HSCX_CH_B];
2041         lt = &chan->isic_isdn_linktab;
2042
2043         lt->unit = sc->sc_unit;
2044         lt->channel = HSCX_CH_B;
2045         lt->bch_config = itjc_bchannel_setup;
2046         lt->bch_tx_start = itjc_bchannel_start;
2047         lt->bch_stat = itjc_bchannel_stat;
2048         lt->tx_queue = &chan->tx_queue;
2049
2050         /* used by non-HDLC data transfers, i.e. telephony drivers */
2051         lt->rx_queue = &chan->rx_queue;
2052
2053         /* used by HDLC data transfers, i.e. ipr and isp drivers */
2054         lt->rx_mbuf = &chan->in_mbuf;
2055 }
2056
2057
2058 /*---------------------------------------------------------------------------*
2059  *      itjc_bchannel_stat - Collect link statistics for a given B channel.
2060  *---------------------------------------------------------------------------*/
2061 static void
2062 itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
2063 {
2064 #ifdef __FreeBSD__
2065         struct l1_softc *sc = itjc_scp[unit];
2066 #else
2067         struct l1_softc *sc = isic_find_sc(unit);
2068 #endif
2069         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
2070         int s;
2071
2072         s = SPLI4B();
2073
2074         bsp->outbytes = chan->txcount;
2075         bsp->inbytes = chan->rxcount;
2076
2077         chan->txcount = 0;
2078         chan->rxcount = 0;
2079
2080         splx(s);
2081 }
2082
2083
2084 /*---------------------------------------------------------------------------*
2085  *      Netjet - ISAC interrupt routine.
2086  *---------------------------------------------------------------------------*/
2087 static void
2088 itjc_isac_intr(struct l1_softc *sc)
2089 {
2090         register u_char irq_stat;
2091
2092         do
2093         {
2094                 /* get isac irq status */
2095                 irq_stat = ISAC_READ(I_ISTA);
2096
2097                 if(irq_stat)
2098                         itjc_isac_irq(sc, irq_stat); /* isac handler */
2099         }
2100         while(irq_stat);
2101
2102         ISAC_WRITE(I_MASK, 0xff);
2103
2104         DELAY(100);
2105
2106         ISAC_WRITE(I_MASK, ISAC_IMASK);
2107 }
2108
2109
2110 /*---------------------------------------------------------------------------*
2111  *      itjc_recover - Try to recover from ISAC irq lockup.
2112  *---------------------------------------------------------------------------*/
2113 void
2114 itjc_recover(struct l1_softc *sc)
2115 {
2116         u_char byte;
2117
2118         /* get isac irq status */
2119
2120         byte = ISAC_READ(I_ISTA);
2121
2122         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
2123
2124         if(byte & ISAC_ISTA_EXI)
2125                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
2126
2127         if(byte & ISAC_ISTA_CISQ)
2128         {
2129                 byte = ISAC_READ(I_CIRR);
2130
2131                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
2132
2133                 if(byte & ISAC_CIRR_SQC)
2134                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
2135         }
2136
2137         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
2138
2139         ISAC_WRITE(I_MASK, 0xff);
2140         DELAY(100);
2141         ISAC_WRITE(I_MASK, ISAC_IMASK);
2142 }