sys/pci/if_rl.c

   1 /*-
   2  * Copyright (c) 1997, 1998
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * RealTek 8129/8139 PCI NIC driver
  38  *
  39  * Supports several extremely cheap PCI 10/100 adapters based on
  40  * the RealTek chipset. Datasheets can be obtained from
  41  * www.realtek.com.tw.
  42  *
  43  * Written by Bill Paul <wpaul@ctr.columbia.edu>
  44  * Electrical Engineering Department
  45  * Columbia University, New York City
  46  */
  47 /*
  48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
  49  * probably the worst PCI ethernet controller ever made, with the possible
  50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
  51  * DMA, but it has a terrible interface that nullifies any performance
  52  * gains that bus-master DMA usually offers.
  53  *
  54  * For transmission, the chip offers a series of four TX descriptor
  55  * registers. Each transmit frame must be in a contiguous buffer, aligned
  56  * on a longword (32-bit) boundary. This means we almost always have to
  57  * do mbuf copies in order to transmit a frame, except in the unlikely
  58  * case where a) the packet fits into a single mbuf, and b) the packet
  59  * is 32-bit aligned within the mbuf's data area. The presence of only
  60  * four descriptor registers means that we can never have more than four
  61  * packets queued for transmission at any one time.
  62  *
  63  * Reception is not much better. The driver has to allocate a single large
  64  * buffer area (up to 64K in size) into which the chip will DMA received
  65  * frames. Because we don't know where within this region received packets
  66  * will begin or end, we have no choice but to copy data from the buffer
  67  * area into mbufs in order to pass the packets up to the higher protocol
  68  * levels.
  69  *
  70  * It's impossible given this rotten design to really achieve decent
  71  * performance at 100Mbps, unless you happen to have a 400Mhz PII or
  72  * some equally overmuscled CPU to drive it.
  73  *
  74  * On the bright side, the 8139 does have a built-in PHY, although
  75  * rather than using an MDIO serial interface like most other NICs, the
  76  * PHY registers are directly accessible through the 8139's register
  77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
  78  * filter.
  79  *
  80  * The 8129 chip is an older version of the 8139 that uses an external PHY
  81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
  82  * the 8139 lets you directly access the on-board PHY registers. We need
  83  * to select which interface to use depending on the chip type.
  84  */
  85
  86 #ifdef HAVE_KERNEL_OPTION_HEADERS
  87 #include "opt_device_polling.h"
  88 #endif
  89
  90 #include <sys/param.h>
  91 #include <sys/endian.h>
  92 #include <sys/systm.h>
  93 #include <sys/sockio.h>
  94 #include <sys/mbuf.h>
  95 #include <sys/malloc.h>
  96 #include <sys/kernel.h>
  97 #include <sys/module.h>
  98 #include <sys/socket.h>
  99
 100 #include <net/if.h>
 101 #include <net/if_arp.h>
 102 #include <net/ethernet.h>
 103 #include <net/if_dl.h>
 104 #include <net/if_media.h>
 105 #include <net/if_types.h>
 106
 107 #include <net/bpf.h>
 108
 109 #include <machine/bus.h>
 110 #include <machine/resource.h>
 111 #include <sys/bus.h>
 112 #include <sys/rman.h>
 113
 114 #include <dev/mii/mii.h>
 115 #include <dev/mii/miivar.h>
 116
 117 #include <dev/pci/pcireg.h>
 118 #include <dev/pci/pcivar.h>
 119
 120 MODULE_DEPEND(rl, pci, 1, 1, 1);
 121 MODULE_DEPEND(rl, ether, 1, 1, 1);
 122 MODULE_DEPEND(rl, miibus, 1, 1, 1);
 123
 124 /* "device miibus" required.  See GENERIC if you get errors here. */
 125 #include "miibus_if.h"
 126
 127 /*
 128  * Default to using PIO access for this driver. On SMP systems,
 129  * there appear to be problems with memory mapped mode: it looks like
 130  * doing too many memory mapped access back to back in rapid succession
 131  * can hang the bus. I'm inclined to blame this on crummy design/construction
 132  * on the part of RealTek. Memory mapped mode does appear to work on
 133  * uniprocessor systems though.
 134  */
 135 #define RL_USEIOSPACE
 136
 137 #include <pci/if_rlreg.h>
 138
 139 /*
 140  * Various supported device vendors/types and their names.
 141  */
 142 static struct rl_type rl_devs[] = {
 143         { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
 144                 "RealTek 8129 10/100BaseTX" },
 145         { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
 146                 "RealTek 8139 10/100BaseTX" },
 147         { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
 148                 "RealTek 8139 10/100BaseTX" },
 149         { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
 150                 "RealTek 8139 10/100BaseTX CardBus" },
 151         { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
 152                 "RealTek 8100 10/100BaseTX" },
 153         { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
 154                 "Accton MPX 5030/5038 10/100BaseTX" },
 155         { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
 156                 "Delta Electronics 8139 10/100BaseTX" },
 157         { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
 158                 "Addtron Technolgy 8139 10/100BaseTX" },
 159         { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
 160                 "D-Link DFE-530TX+ 10/100BaseTX" },
 161         { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
 162                 "D-Link DFE-690TXD 10/100BaseTX" },
 163         { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
 164                 "Nortel Networks 10/100BaseTX" },
 165         { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
 166                 "Corega FEther CB-TXD" },
 167         { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
 168                 "Corega FEtherII CB-TXD" },
 169         { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
 170                 "Peppercon AG ROL-F" },
 171         { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
 172                 "Planex FNW-3603-TX" },
 173         { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
 174                 "Planex FNW-3800-TX" },
 175         { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
 176                 "Compaq HNE-300" },
 177         { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
 178                 "LevelOne FPC-0106TX" },
 179         { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
 180                 "Edimax EP-4103DL CardBus" }
 181 };
 182
 183 static int rl_attach(device_t);
 184 static int rl_detach(device_t);
 185 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 186 static int rl_dma_alloc(struct rl_softc *);
 187 static void rl_dma_free(struct rl_softc *);
 188 static void rl_eeprom_putbyte(struct rl_softc *, int);
 189 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
 190 static int rl_encap(struct rl_softc *, struct mbuf **);
 191 static int rl_list_tx_init(struct rl_softc *);
 192 static int rl_list_rx_init(struct rl_softc *);
 193 static int rl_ifmedia_upd(struct ifnet *);
 194 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 195 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
 196 static void rl_intr(void *);
 197 static void rl_init(void *);
 198 static void rl_init_locked(struct rl_softc *sc);
 199 static void rl_mii_send(struct rl_softc *, uint32_t, int);
 200 static void rl_mii_sync(struct rl_softc *);
 201 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
 202 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
 203 static int rl_miibus_readreg(device_t, int, int);
 204 static void rl_miibus_statchg(device_t);
 205 static int rl_miibus_writereg(device_t, int, int, int);
 206 #ifdef DEVICE_POLLING
 207 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 208 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
 209 #endif
 210 static int rl_probe(device_t);
 211 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
 212 static void rl_reset(struct rl_softc *);
 213 static int rl_resume(device_t);
 214 static void rl_rxeof(struct rl_softc *);
 215 static void rl_setmulti(struct rl_softc *);
 216 static int rl_shutdown(device_t);
 217 static void rl_start(struct ifnet *);
 218 static void rl_start_locked(struct ifnet *);
 219 static void rl_stop(struct rl_softc *);
 220 static int rl_suspend(device_t);
 221 static void rl_tick(void *);
 222 static void rl_txeof(struct rl_softc *);
 223 static void rl_watchdog(struct rl_softc *);
 224
 225 #ifdef RL_USEIOSPACE
 226 #define RL_RES                  SYS_RES_IOPORT
 227 #define RL_RID                  RL_PCI_LOIO
 228 #else
 229 #define RL_RES                  SYS_RES_MEMORY
 230 #define RL_RID                  RL_PCI_LOMEM
 231 #endif
 232
 233 static device_method_t rl_methods[] = {
 234         /* Device interface */
 235         DEVMETHOD(device_probe,         rl_probe),
 236         DEVMETHOD(device_attach,        rl_attach),
 237         DEVMETHOD(device_detach,        rl_detach),
 238         DEVMETHOD(device_suspend,       rl_suspend),
 239         DEVMETHOD(device_resume,        rl_resume),
 240         DEVMETHOD(device_shutdown,      rl_shutdown),
 241
 242         /* bus interface */
 243         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 244         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 245
 246         /* MII interface */
 247         DEVMETHOD(miibus_readreg,       rl_miibus_readreg),
 248         DEVMETHOD(miibus_writereg,      rl_miibus_writereg),
 249         DEVMETHOD(miibus_statchg,       rl_miibus_statchg),
 250
 251         { 0, 0 }
 252 };
 253
 254 static driver_t rl_driver = {
 255         "rl",
 256         rl_methods,
 257         sizeof(struct rl_softc)
 258 };
 259
 260 static devclass_t rl_devclass;
 261
 262 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
 263 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
 264 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
 265
 266 #define EE_SET(x)                                       \
 267         CSR_WRITE_1(sc, RL_EECMD,                       \
 268                 CSR_READ_1(sc, RL_EECMD) | x)
 269
 270 #define EE_CLR(x)                                       \
 271         CSR_WRITE_1(sc, RL_EECMD,                       \
 272                 CSR_READ_1(sc, RL_EECMD) & ~x)
 273
 274 /*
 275  * Send a read command and address to the EEPROM, check for ACK.
 276  */
 277 static void
 278 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
 279 {
 280         register int            d, i;
 281
 282         d = addr | sc->rl_eecmd_read;
 283
 284         /*
 285          * Feed in each bit and strobe the clock.
 286          */
 287         for (i = 0x400; i; i >>= 1) {
 288                 if (d & i) {
 289                         EE_SET(RL_EE_DATAIN);
 290                 } else {
 291                         EE_CLR(RL_EE_DATAIN);
 292                 }
 293                 DELAY(100);
 294                 EE_SET(RL_EE_CLK);
 295                 DELAY(150);
 296                 EE_CLR(RL_EE_CLK);
 297                 DELAY(100);
 298         }
 299 }
 300
 301 /*
 302  * Read a word of data stored in the EEPROM at address 'addr.'
 303  */
 304 static void
 305 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
 306 {
 307         register int            i;
 308         uint16_t                word = 0;
 309
 310         /* Enter EEPROM access mode. */
 311         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 312
 313         /*
 314          * Send address of word we want to read.
 315          */
 316         rl_eeprom_putbyte(sc, addr);
 317
 318         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 319
 320         /*
 321          * Start reading bits from EEPROM.
 322          */
 323         for (i = 0x8000; i; i >>= 1) {
 324                 EE_SET(RL_EE_CLK);
 325                 DELAY(100);
 326                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
 327                         word |= i;
 328                 EE_CLR(RL_EE_CLK);
 329                 DELAY(100);
 330         }
 331
 332         /* Turn off EEPROM access mode. */
 333         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 334
 335         *dest = word;
 336 }
 337
 338 /*
 339  * Read a sequence of words from the EEPROM.
 340  */
 341 static void
 342 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
 343 {
 344         int                     i;
 345         uint16_t                word = 0, *ptr;
 346
 347         for (i = 0; i < cnt; i++) {
 348                 rl_eeprom_getword(sc, off + i, &word);
 349                 ptr = (uint16_t *)(dest + (i * 2));
 350                 if (swap)
 351                         *ptr = ntohs(word);
 352                 else
 353                         *ptr = word;
 354         }
 355 }
 356
 357 /*
 358  * MII access routines are provided for the 8129, which
 359  * doesn't have a built-in PHY. For the 8139, we fake things
 360  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
 361  * direct access PHY registers.
 362  */
 363 #define MII_SET(x)                                      \
 364         CSR_WRITE_1(sc, RL_MII,                         \
 365                 CSR_READ_1(sc, RL_MII) | (x))
 366
 367 #define MII_CLR(x)                                      \
 368         CSR_WRITE_1(sc, RL_MII,                         \
 369                 CSR_READ_1(sc, RL_MII) & ~(x))
 370
 371 /*
 372  * Sync the PHYs by setting data bit and strobing the clock 32 times.
 373  */
 374 static void
 375 rl_mii_sync(struct rl_softc *sc)
 376 {
 377         register int            i;
 378
 379         MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
 380
 381         for (i = 0; i < 32; i++) {
 382                 MII_SET(RL_MII_CLK);
 383                 DELAY(1);
 384                 MII_CLR(RL_MII_CLK);
 385                 DELAY(1);
 386         }
 387 }
 388
 389 /*
 390  * Clock a series of bits through the MII.
 391  */
 392 static void
 393 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
 394 {
 395         int                     i;
 396
 397         MII_CLR(RL_MII_CLK);
 398
 399         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
 400                 if (bits & i) {
 401                         MII_SET(RL_MII_DATAOUT);
 402                 } else {
 403                         MII_CLR(RL_MII_DATAOUT);
 404                 }
 405                 DELAY(1);
 406                 MII_CLR(RL_MII_CLK);
 407                 DELAY(1);
 408                 MII_SET(RL_MII_CLK);
 409         }
 410 }
 411
 412 /*
 413  * Read an PHY register through the MII.
 414  */
 415 static int
 416 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
 417 {
 418         int                     i, ack;
 419
 420         /* Set up frame for RX. */
 421         frame->mii_stdelim = RL_MII_STARTDELIM;
 422         frame->mii_opcode = RL_MII_READOP;
 423         frame->mii_turnaround = 0;
 424         frame->mii_data = 0;
 425
 426         CSR_WRITE_2(sc, RL_MII, 0);
 427
 428         /* Turn on data xmit. */
 429         MII_SET(RL_MII_DIR);
 430
 431         rl_mii_sync(sc);
 432
 433         /* Send command/address info. */
 434         rl_mii_send(sc, frame->mii_stdelim, 2);
 435         rl_mii_send(sc, frame->mii_opcode, 2);
 436         rl_mii_send(sc, frame->mii_phyaddr, 5);
 437         rl_mii_send(sc, frame->mii_regaddr, 5);
 438
 439         /* Idle bit */
 440         MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
 441         DELAY(1);
 442         MII_SET(RL_MII_CLK);
 443         DELAY(1);
 444
 445         /* Turn off xmit. */
 446         MII_CLR(RL_MII_DIR);
 447
 448         /* Check for ack */
 449         MII_CLR(RL_MII_CLK);
 450         DELAY(1);
 451         ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
 452         MII_SET(RL_MII_CLK);
 453         DELAY(1);
 454
 455         /*
 456          * Now try reading data bits. If the ack failed, we still
 457          * need to clock through 16 cycles to keep the PHY(s) in sync.
 458          */
 459         if (ack) {
 460                 for(i = 0; i < 16; i++) {
 461                         MII_CLR(RL_MII_CLK);
 462                         DELAY(1);
 463                         MII_SET(RL_MII_CLK);
 464                         DELAY(1);
 465                 }
 466                 goto fail;
 467         }
 468
 469         for (i = 0x8000; i; i >>= 1) {
 470                 MII_CLR(RL_MII_CLK);
 471                 DELAY(1);
 472                 if (!ack) {
 473                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
 474                                 frame->mii_data |= i;
 475                         DELAY(1);
 476                 }
 477                 MII_SET(RL_MII_CLK);
 478                 DELAY(1);
 479         }
 480
 481 fail:
 482         MII_CLR(RL_MII_CLK);
 483         DELAY(1);
 484         MII_SET(RL_MII_CLK);
 485         DELAY(1);
 486
 487         return (ack ? 1 : 0);
 488 }
 489
 490 /*
 491  * Write to a PHY register through the MII.
 492  */
 493 static int
 494 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
 495 {
 496
 497         /* Set up frame for TX. */
 498         frame->mii_stdelim = RL_MII_STARTDELIM;
 499         frame->mii_opcode = RL_MII_WRITEOP;
 500         frame->mii_turnaround = RL_MII_TURNAROUND;
 501
 502         /* Turn on data output. */
 503         MII_SET(RL_MII_DIR);
 504
 505         rl_mii_sync(sc);
 506
 507         rl_mii_send(sc, frame->mii_stdelim, 2);
 508         rl_mii_send(sc, frame->mii_opcode, 2);
 509         rl_mii_send(sc, frame->mii_phyaddr, 5);
 510         rl_mii_send(sc, frame->mii_regaddr, 5);
 511         rl_mii_send(sc, frame->mii_turnaround, 2);
 512         rl_mii_send(sc, frame->mii_data, 16);
 513
 514         /* Idle bit. */
 515         MII_SET(RL_MII_CLK);
 516         DELAY(1);
 517         MII_CLR(RL_MII_CLK);
 518         DELAY(1);
 519
 520         /* Turn off xmit. */
 521         MII_CLR(RL_MII_DIR);
 522
 523         return (0);
 524 }
 525
 526 static int
 527 rl_miibus_readreg(device_t dev, int phy, int reg)
 528 {
 529         struct rl_softc         *sc;
 530         struct rl_mii_frame     frame;
 531         uint16_t                rval = 0;
 532         uint16_t                rl8139_reg = 0;
 533
 534         sc = device_get_softc(dev);
 535
 536         if (sc->rl_type == RL_8139) {
 537                 /* Pretend the internal PHY is only at address 0 */
 538                 if (phy) {
 539                         return (0);
 540                 }
 541                 switch (reg) {
 542                 case MII_BMCR:
 543                         rl8139_reg = RL_BMCR;
 544                         break;
 545                 case MII_BMSR:
 546                         rl8139_reg = RL_BMSR;
 547                         break;
 548                 case MII_ANAR:
 549                         rl8139_reg = RL_ANAR;
 550                         break;
 551                 case MII_ANER:
 552                         rl8139_reg = RL_ANER;
 553                         break;
 554                 case MII_ANLPAR:
 555                         rl8139_reg = RL_LPAR;
 556                         break;
 557                 case MII_PHYIDR1:
 558                 case MII_PHYIDR2:
 559                         return (0);
 560                 /*
 561                  * Allow the rlphy driver to read the media status
 562                  * register. If we have a link partner which does not
 563                  * support NWAY, this is the register which will tell
 564                  * us the results of parallel detection.
 565                  */
 566                 case RL_MEDIASTAT:
 567                         rval = CSR_READ_1(sc, RL_MEDIASTAT);
 568                         return (rval);
 569                 default:
 570                         device_printf(sc->rl_dev, "bad phy register\n");
 571                         return (0);
 572                 }
 573                 rval = CSR_READ_2(sc, rl8139_reg);
 574                 return (rval);
 575         }
 576
 577         bzero((char *)&frame, sizeof(frame));
 578         frame.mii_phyaddr = phy;
 579         frame.mii_regaddr = reg;
 580         rl_mii_readreg(sc, &frame);
 581
 582         return (frame.mii_data);
 583 }
 584
 585 static int
 586 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
 587 {
 588         struct rl_softc         *sc;
 589         struct rl_mii_frame     frame;
 590         uint16_t                rl8139_reg = 0;
 591
 592         sc = device_get_softc(dev);
 593
 594         if (sc->rl_type == RL_8139) {
 595                 /* Pretend the internal PHY is only at address 0 */
 596                 if (phy) {
 597                         return (0);
 598                 }
 599                 switch (reg) {
 600                 case MII_BMCR:
 601                         rl8139_reg = RL_BMCR;
 602                         break;
 603                 case MII_BMSR:
 604                         rl8139_reg = RL_BMSR;
 605                         break;
 606                 case MII_ANAR:
 607                         rl8139_reg = RL_ANAR;
 608                         break;
 609                 case MII_ANER:
 610                         rl8139_reg = RL_ANER;
 611                         break;
 612                 case MII_ANLPAR:
 613                         rl8139_reg = RL_LPAR;
 614                         break;
 615                 case MII_PHYIDR1:
 616                 case MII_PHYIDR2:
 617                         return (0);
 618                         break;
 619                 default:
 620                         device_printf(sc->rl_dev, "bad phy register\n");
 621                         return (0);
 622                 }
 623                 CSR_WRITE_2(sc, rl8139_reg, data);
 624                 return (0);
 625         }
 626
 627         bzero((char *)&frame, sizeof(frame));
 628         frame.mii_phyaddr = phy;
 629         frame.mii_regaddr = reg;
 630         frame.mii_data = data;
 631         rl_mii_writereg(sc, &frame);
 632
 633         return (0);
 634 }
 635
 636 static void
 637 rl_miibus_statchg(device_t dev)
 638 {
 639         struct rl_softc         *sc;
 640         struct ifnet            *ifp;
 641         struct mii_data         *mii;
 642
 643         sc = device_get_softc(dev);
 644         mii = device_get_softc(sc->rl_miibus);
 645         ifp = sc->rl_ifp;
 646         if (mii == NULL || ifp == NULL ||
 647             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 648                 return;
 649
 650         sc->rl_flags &= ~RL_FLAG_LINK;
 651         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 652             (IFM_ACTIVE | IFM_AVALID)) {
 653                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 654                 case IFM_10_T:
 655                 case IFM_100_TX:
 656                         sc->rl_flags |= RL_FLAG_LINK;
 657                         break;
 658                 default:
 659                         break;
 660                 }
 661         }
 662         /*
 663          * RealTek controllers do not provide any interface to
 664          * Tx/Rx MACs for resolved speed, duplex and flow-control
 665          * parameters.
 666          */
 667 }
 668
 669 /*
 670  * Program the 64-bit multicast hash filter.
 671  */
 672 static void
 673 rl_setmulti(struct rl_softc *sc)
 674 {
 675         struct ifnet            *ifp = sc->rl_ifp;
 676         int                     h = 0;
 677         uint32_t                hashes[2] = { 0, 0 };
 678         struct ifmultiaddr      *ifma;
 679         uint32_t                rxfilt;
 680         int                     mcnt = 0;
 681
 682         RL_LOCK_ASSERT(sc);
 683
 684         rxfilt = CSR_READ_4(sc, RL_RXCFG);
 685
 686         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 687                 rxfilt |= RL_RXCFG_RX_MULTI;
 688                 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 689                 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
 690                 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
 691                 return;
 692         }
 693
 694         /* first, zot all the existing hash bits */
 695         CSR_WRITE_4(sc, RL_MAR0, 0);
 696         CSR_WRITE_4(sc, RL_MAR4, 0);
 697
 698         /* now program new ones */
 699         IF_ADDR_LOCK(ifp);
 700         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 701                 if (ifma->ifma_addr->sa_family != AF_LINK)
 702                         continue;
 703                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 704                     ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
 705                 if (h < 32)
 706                         hashes[0] |= (1 << h);
 707                 else
 708                         hashes[1] |= (1 << (h - 32));
 709                 mcnt++;
 710         }
 711         IF_ADDR_UNLOCK(ifp);
 712
 713         if (mcnt)
 714                 rxfilt |= RL_RXCFG_RX_MULTI;
 715         else
 716                 rxfilt &= ~RL_RXCFG_RX_MULTI;
 717
 718         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 719         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
 720         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
 721 }
 722
 723 static void
 724 rl_reset(struct rl_softc *sc)
 725 {
 726         register int            i;
 727
 728         RL_LOCK_ASSERT(sc);
 729
 730         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
 731
 732         for (i = 0; i < RL_TIMEOUT; i++) {
 733                 DELAY(10);
 734                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
 735                         break;
 736         }
 737         if (i == RL_TIMEOUT)
 738                 device_printf(sc->rl_dev, "reset never completed!\n");
 739 }
 740
 741 /*
 742  * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
 743  * IDs against our list and return a device name if we find a match.
 744  */
 745 static int
 746 rl_probe(device_t dev)
 747 {
 748         struct rl_type          *t;
 749         uint16_t                devid, revid, vendor;
 750         int                     i;
 751
 752         vendor = pci_get_vendor(dev);
 753         devid = pci_get_device(dev);
 754         revid = pci_get_revid(dev);
 755
 756         if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
 757                 if (revid == 0x20) {
 758                         /* 8139C+, let re(4) take care of this device. */
 759                         return (ENXIO);
 760                 }
 761         }
 762         t = rl_devs;
 763         for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
 764                 if (vendor == t->rl_vid && devid == t->rl_did) {
 765                         device_set_desc(dev, t->rl_name);
 766                         return (BUS_PROBE_DEFAULT);
 767                 }
 768         }
 769
 770         return (ENXIO);
 771 }
 772
 773 struct rl_dmamap_arg {
 774         bus_addr_t      rl_busaddr;
 775 };
 776
 777 static void
 778 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 779 {
 780         struct rl_dmamap_arg    *ctx;
 781
 782         if (error != 0)
 783                 return;
 784
 785         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 786
 787         ctx = (struct rl_dmamap_arg *)arg;
 788         ctx->rl_busaddr = segs[0].ds_addr;
 789 }
 790
 791 /*
 792  * Attach the interface. Allocate softc structures, do ifmedia
 793  * setup and ethernet/BPF attach.
 794  */
 795 static int
 796 rl_attach(device_t dev)
 797 {
 798         uint8_t                 eaddr[ETHER_ADDR_LEN];
 799         uint16_t                as[3];
 800         struct ifnet            *ifp;
 801         struct rl_softc         *sc;
 802         struct rl_type          *t;
 803         int                     error = 0, i, rid;
 804         int                     unit;
 805         uint16_t                rl_did = 0;
 806
 807         sc = device_get_softc(dev);
 808         unit = device_get_unit(dev);
 809         sc->rl_dev = dev;
 810
 811         mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 812             MTX_DEF);
 813         callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
 814
 815         pci_enable_busmaster(dev);
 816
 817         /* Map control/status registers. */
 818         rid = RL_RID;
 819         sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
 820
 821         if (sc->rl_res == NULL) {
 822                 device_printf(dev, "couldn't map ports/memory\n");
 823                 error = ENXIO;
 824                 goto fail;
 825         }
 826
 827 #ifdef notdef
 828         /*
 829          * Detect the Realtek 8139B. For some reason, this chip is very
 830          * unstable when left to autoselect the media
 831          * The best workaround is to set the device to the required
 832          * media type or to set it to the 10 Meg speed.
 833          */
 834         if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
 835                 device_printf(dev,
 836 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
 837 #endif
 838
 839         sc->rl_btag = rman_get_bustag(sc->rl_res);
 840         sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
 841
 842         /* Allocate interrupt */
 843         rid = 0;
 844         sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 845             RF_SHAREABLE | RF_ACTIVE);
 846
 847         if (sc->rl_irq[0] == NULL) {
 848                 device_printf(dev, "couldn't map interrupt\n");
 849                 error = ENXIO;
 850                 goto fail;
 851         }
 852
 853         /*
 854          * Reset the adapter. Only take the lock here as it's needed in
 855          * order to call rl_reset().
 856          */
 857         RL_LOCK(sc);
 858         rl_reset(sc);
 859         RL_UNLOCK(sc);
 860
 861         sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
 862         rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
 863         if (rl_did != 0x8129)
 864                 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
 865
 866         /*
 867          * Get station address from the EEPROM.
 868          */
 869         rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
 870         for (i = 0; i < 3; i++) {
 871                 eaddr[(i * 2) + 0] = as[i] & 0xff;
 872                 eaddr[(i * 2) + 1] = as[i] >> 8;
 873         }
 874
 875         /*
 876          * Now read the exact device type from the EEPROM to find
 877          * out if it's an 8129 or 8139.
 878          */
 879         rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
 880
 881         t = rl_devs;
 882         sc->rl_type = 0;
 883         while(t->rl_name != NULL) {
 884                 if (rl_did == t->rl_did) {
 885                         sc->rl_type = t->rl_basetype;
 886                         break;
 887                 }
 888                 t++;
 889         }
 890
 891         if (sc->rl_type == 0) {
 892                 device_printf(dev, "unknown device ID: %x assuming 8139\n",
 893                     rl_did);
 894                 sc->rl_type = RL_8139;
 895                 /*
 896                  * Read RL_IDR register to get ethernet address as accessing
 897                  * EEPROM may not extract correct address.
 898                  */
 899                 for (i = 0; i < ETHER_ADDR_LEN; i++)
 900                         eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
 901         }
 902
 903         if ((error = rl_dma_alloc(sc)) != 0)
 904                 goto fail;
 905
 906         ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
 907         if (ifp == NULL) {
 908                 device_printf(dev, "can not if_alloc()\n");
 909                 error = ENOSPC;
 910                 goto fail;
 911         }
 912
 913         /* Do MII setup */
 914         if (mii_phy_probe(dev, &sc->rl_miibus,
 915             rl_ifmedia_upd, rl_ifmedia_sts)) {
 916                 device_printf(dev, "MII without any phy!\n");
 917                 error = ENXIO;
 918                 goto fail;
 919         }
 920
 921         ifp->if_softc = sc;
 922         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 923         ifp->if_mtu = ETHERMTU;
 924         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 925         ifp->if_ioctl = rl_ioctl;
 926         ifp->if_start = rl_start;
 927         ifp->if_init = rl_init;
 928         ifp->if_capabilities = IFCAP_VLAN_MTU;
 929         ifp->if_capenable = ifp->if_capabilities;
 930 #ifdef DEVICE_POLLING
 931         ifp->if_capabilities |= IFCAP_POLLING;
 932 #endif
 933         IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
 934         ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
 935         IFQ_SET_READY(&ifp->if_snd);
 936
 937         /*
 938          * Call MI attach routine.
 939          */
 940         ether_ifattach(ifp, eaddr);
 941
 942         /* Hook interrupt last to avoid having to lock softc */
 943         error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
 944             NULL, rl_intr, sc, &sc->rl_intrhand[0]);
 945         if (error) {
 946                 device_printf(sc->rl_dev, "couldn't set up irq\n");
 947                 ether_ifdetach(ifp);
 948         }
 949
 950 fail:
 951         if (error)
 952                 rl_detach(dev);
 953
 954         return (error);
 955 }
 956
 957 /*
 958  * Shutdown hardware and free up resources. This can be called any
 959  * time after the mutex has been initialized. It is called in both
 960  * the error case in attach and the normal detach case so it needs
 961  * to be careful about only freeing resources that have actually been
 962  * allocated.
 963  */
 964 static int
 965 rl_detach(device_t dev)
 966 {
 967         struct rl_softc         *sc;
 968         struct ifnet            *ifp;
 969
 970         sc = device_get_softc(dev);
 971         ifp = sc->rl_ifp;
 972
 973         KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
 974
 975 #ifdef DEVICE_POLLING
 976         if (ifp->if_capenable & IFCAP_POLLING)
 977                 ether_poll_deregister(ifp);
 978 #endif
 979         /* These should only be active if attach succeeded */
 980         if (device_is_attached(dev)) {
 981                 RL_LOCK(sc);
 982                 rl_stop(sc);
 983                 RL_UNLOCK(sc);
 984                 callout_drain(&sc->rl_stat_callout);
 985                 ether_ifdetach(ifp);
 986         }
 987 #if 0
 988         sc->suspended = 1;
 989 #endif
 990         if (sc->rl_miibus)
 991                 device_delete_child(dev, sc->rl_miibus);
 992         bus_generic_detach(dev);
 993
 994         if (sc->rl_intrhand[0])
 995                 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
 996         if (sc->rl_irq[0])
 997                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
 998         if (sc->rl_res)
 999                 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1000
1001         if (ifp)
1002                 if_free(ifp);
1003
1004         rl_dma_free(sc);
1005
1006         mtx_destroy(&sc->rl_mtx);
1007
1008         return (0);
1009 }
1010
1011 static int
1012 rl_dma_alloc(struct rl_softc *sc)
1013 {
1014         struct rl_dmamap_arg    ctx;
1015         int                     error, i;
1016
1017         /*
1018          * Allocate the parent bus DMA tag appropriate for PCI.
1019          */
1020         error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
1021             1, 0,                       /* alignment, boundary */
1022             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1023             BUS_SPACE_MAXADDR,          /* highaddr */
1024             NULL, NULL,                 /* filter, filterarg */
1025             BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
1026             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1027             0,                          /* flags */
1028             NULL, NULL,                 /* lockfunc, lockarg */
1029             &sc->rl_parent_tag);
1030         if (error) {
1031                 device_printf(sc->rl_dev,
1032                     "failed to create parent DMA tag.\n");
1033                 goto fail;
1034         }
1035         /* Create DMA tag for Rx memory block. */
1036         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
1037             RL_RX_8139_BUF_ALIGN, 0,    /* alignment, boundary */
1038             BUS_SPACE_MAXADDR,          /* lowaddr */
1039             BUS_SPACE_MAXADDR,          /* highaddr */
1040             NULL, NULL,                 /* filter, filterarg */
1041             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1,   /* maxsize,nsegments */
1042             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ,      /* maxsegsize */
1043             0,                          /* flags */
1044             NULL, NULL,                 /* lockfunc, lockarg */
1045             &sc->rl_cdata.rl_rx_tag);
1046         if (error) {
1047                 device_printf(sc->rl_dev,
1048                     "failed to create Rx memory block DMA tag.\n");
1049                 goto fail;
1050         }
1051         /* Create DMA tag for Tx buffer. */
1052         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
1053             RL_TX_8139_BUF_ALIGN, 0,    /* alignment, boundary */
1054             BUS_SPACE_MAXADDR,          /* lowaddr */
1055             BUS_SPACE_MAXADDR,          /* highaddr */
1056             NULL, NULL,                 /* filter, filterarg */
1057             MCLBYTES, 1,                /* maxsize, nsegments */
1058             MCLBYTES,                   /* maxsegsize */
1059             0,                          /* flags */
1060             NULL, NULL,                 /* lockfunc, lockarg */
1061             &sc->rl_cdata.rl_tx_tag);
1062         if (error) {
1063                 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
1064                 goto fail;
1065         }
1066
1067         /*
1068          * Allocate DMA'able memory and load DMA map for Rx memory block.
1069          */
1070         error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
1071             (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
1072             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
1073         if (error != 0) {
1074                 device_printf(sc->rl_dev,
1075                     "failed to allocate Rx DMA memory block.\n");
1076                 goto fail;
1077         }
1078         ctx.rl_busaddr = 0;
1079         error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
1080             sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
1081             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
1082             BUS_DMA_NOWAIT);
1083         if (error != 0 || ctx.rl_busaddr == 0) {
1084                 device_printf(sc->rl_dev,
1085                     "could not load Rx DMA memory block.\n");
1086                 goto fail;
1087         }
1088         sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
1089
1090         /* Create DMA maps for Tx buffers. */
1091         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1092                 sc->rl_cdata.rl_tx_chain[i] = NULL;
1093                 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1094                 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
1095                     &sc->rl_cdata.rl_tx_dmamap[i]);
1096                 if (error != 0) {
1097                         device_printf(sc->rl_dev,
1098                             "could not create Tx dmamap.\n");
1099                         goto fail;
1100                 }
1101         }
1102
1103         /* Leave a few bytes before the start of the RX ring buffer. */
1104         sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1105         sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1106
1107 fail:
1108         return (error);
1109 }
1110
1111 static void
1112 rl_dma_free(struct rl_softc *sc)
1113 {
1114         int                     i;
1115
1116         /* Rx memory block. */
1117         if (sc->rl_cdata.rl_rx_tag != NULL) {
1118                 if (sc->rl_cdata.rl_rx_dmamap != NULL)
1119                         bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1120                             sc->rl_cdata.rl_rx_dmamap);
1121                 if (sc->rl_cdata.rl_rx_dmamap != NULL &&
1122                     sc->rl_cdata.rl_rx_buf_ptr != NULL)
1123                         bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1124                             sc->rl_cdata.rl_rx_buf_ptr,
1125                             sc->rl_cdata.rl_rx_dmamap);
1126                 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1127                 sc->rl_cdata.rl_rx_buf = NULL;
1128                 sc->rl_cdata.rl_rx_dmamap = NULL;
1129                 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1130                 sc->rl_cdata.rl_tx_tag = NULL;
1131         }
1132
1133         /* Tx buffers. */
1134         if (sc->rl_cdata.rl_tx_tag != NULL) {
1135                 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1136                         if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1137                                 bus_dmamap_destroy(
1138                                     sc->rl_cdata.rl_tx_tag,
1139                                     sc->rl_cdata.rl_tx_dmamap[i]);
1140                                 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1141                         }
1142                 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1143                 sc->rl_cdata.rl_tx_tag = NULL;
1144                 }
1145         }
1146
1147         if (sc->rl_parent_tag != NULL) {
1148                 bus_dma_tag_destroy(sc->rl_parent_tag);
1149                 sc->rl_parent_tag = NULL;
1150         }
1151 }
1152
1153 /*
1154  * Initialize the transmit descriptors.
1155  */
1156 static int
1157 rl_list_tx_init(struct rl_softc *sc)
1158 {
1159         struct rl_chain_data    *cd;
1160         int                     i;
1161
1162         RL_LOCK_ASSERT(sc);
1163
1164         cd = &sc->rl_cdata;
1165         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1166                 cd->rl_tx_chain[i] = NULL;
1167                 CSR_WRITE_4(sc,
1168                     RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1169         }
1170
1171         sc->rl_cdata.cur_tx = 0;
1172         sc->rl_cdata.last_tx = 0;
1173
1174         return (0);
1175 }
1176
1177 static int
1178 rl_list_rx_init(struct rl_softc *sc)
1179 {
1180
1181         RL_LOCK_ASSERT(sc);
1182
1183         bzero(sc->rl_cdata.rl_rx_buf_ptr,
1184             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1185         bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1186             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1187
1188         return (0);
1189 }
1190
1191 /*
1192  * A frame has been uploaded: pass the resulting mbuf chain up to
1193  * the higher level protocols.
1194  *
1195  * You know there's something wrong with a PCI bus-master chip design
1196  * when you have to use m_devget().
1197  *
1198  * The receive operation is badly documented in the datasheet, so I'll
1199  * attempt to document it here. The driver provides a buffer area and
1200  * places its base address in the RX buffer start address register.
1201  * The chip then begins copying frames into the RX buffer. Each frame
1202  * is preceded by a 32-bit RX status word which specifies the length
1203  * of the frame and certain other status bits. Each frame (starting with
1204  * the status word) is also 32-bit aligned. The frame length is in the
1205  * first 16 bits of the status word; the lower 15 bits correspond with
1206  * the 'rx status register' mentioned in the datasheet.
1207  *
1208  * Note: to make the Alpha happy, the frame payload needs to be aligned
1209  * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1210  * as the offset argument to m_devget().
1211  */
1212 static void
1213 rl_rxeof(struct rl_softc *sc)
1214 {
1215         struct mbuf             *m;
1216         struct ifnet            *ifp = sc->rl_ifp;
1217         uint8_t                 *rxbufpos;
1218         int                     total_len = 0;
1219         int                     wrap = 0;
1220         uint32_t                rxstat;
1221         uint16_t                cur_rx;
1222         uint16_t                limit;
1223         uint16_t                max_bytes, rx_bytes = 0;
1224
1225         RL_LOCK_ASSERT(sc);
1226
1227         bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1228             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1229
1230         cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1231
1232         /* Do not try to read past this point. */
1233         limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1234
1235         if (limit < cur_rx)
1236                 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1237         else
1238                 max_bytes = limit - cur_rx;
1239
1240         while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1241 #ifdef DEVICE_POLLING
1242                 if (ifp->if_capenable & IFCAP_POLLING) {
1243                         if (sc->rxcycles <= 0)
1244                                 break;
1245                         sc->rxcycles--;
1246                 }
1247 #endif
1248                 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1249                 rxstat = le32toh(*(uint32_t *)rxbufpos);
1250
1251                 /*
1252                  * Here's a totally undocumented fact for you. When the
1253                  * RealTek chip is in the process of copying a packet into
1254                  * RAM for you, the length will be 0xfff0. If you spot a
1255                  * packet header with this value, you need to stop. The
1256                  * datasheet makes absolutely no mention of this and
1257                  * RealTek should be shot for this.
1258                  */
1259                 total_len = rxstat >> 16;
1260                 if (total_len == RL_RXSTAT_UNFINISHED)
1261                         break;
1262
1263                 if (!(rxstat & RL_RXSTAT_RXOK) ||
1264                     total_len < ETHER_MIN_LEN ||
1265                     total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1266                         ifp->if_ierrors++;
1267                         rl_init_locked(sc);
1268                         return;
1269                 }
1270
1271                 /* No errors; receive the packet. */
1272                 rx_bytes += total_len + 4;
1273
1274                 /*
1275                  * XXX The RealTek chip includes the CRC with every
1276                  * received frame, and there's no way to turn this
1277                  * behavior off (at least, I can't find anything in
1278                  * the manual that explains how to do it) so we have
1279                  * to trim off the CRC manually.
1280                  */
1281                 total_len -= ETHER_CRC_LEN;
1282
1283                 /*
1284                  * Avoid trying to read more bytes than we know
1285                  * the chip has prepared for us.
1286                  */
1287                 if (rx_bytes > max_bytes)
1288                         break;
1289
1290                 rxbufpos = sc->rl_cdata.rl_rx_buf +
1291                         ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1292                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1293                         rxbufpos = sc->rl_cdata.rl_rx_buf;
1294
1295                 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1296                 if (total_len > wrap) {
1297                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1298                             NULL);
1299                         if (m != NULL)
1300                                 m_copyback(m, wrap, total_len - wrap,
1301                                         sc->rl_cdata.rl_rx_buf);
1302                         cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1303                 } else {
1304                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1305                             NULL);
1306                         cur_rx += total_len + 4 + ETHER_CRC_LEN;
1307                 }
1308
1309                 /* Round up to 32-bit boundary. */
1310                 cur_rx = (cur_rx + 3) & ~3;
1311                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1312
1313                 if (m == NULL) {
1314                         ifp->if_iqdrops++;
1315                         continue;
1316                 }
1317
1318                 ifp->if_ipackets++;
1319                 RL_UNLOCK(sc);
1320                 (*ifp->if_input)(ifp, m);
1321                 RL_LOCK(sc);
1322         }
1323
1324         /* No need to sync Rx memory block as we didn't mofify it. */
1325 }
1326
1327 /*
1328  * A frame was downloaded to the chip. It's safe for us to clean up
1329  * the list buffers.
1330  */
1331 static void
1332 rl_txeof(struct rl_softc *sc)
1333 {
1334         struct ifnet            *ifp = sc->rl_ifp;
1335         uint32_t                txstat;
1336
1337         RL_LOCK_ASSERT(sc);
1338
1339         /*
1340          * Go through our tx list and free mbufs for those
1341          * frames that have been uploaded.
1342          */
1343         do {
1344                 if (RL_LAST_TXMBUF(sc) == NULL)
1345                         break;
1346                 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1347                 if (!(txstat & (RL_TXSTAT_TX_OK|
1348                     RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1349                         break;
1350
1351                 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1352
1353                 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1354                     BUS_DMASYNC_POSTWRITE);
1355                 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1356                 m_freem(RL_LAST_TXMBUF(sc));
1357                 RL_LAST_TXMBUF(sc) = NULL;
1358                 /*
1359                  * If there was a transmit underrun, bump the TX threshold.
1360                  * Make sure not to overflow the 63 * 32byte we can address
1361                  * with the 6 available bit.
1362                  */
1363                 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1364                     (sc->rl_txthresh < 2016))
1365                         sc->rl_txthresh += 32;
1366                 if (txstat & RL_TXSTAT_TX_OK)
1367                         ifp->if_opackets++;
1368                 else {
1369                         int                     oldthresh;
1370                         ifp->if_oerrors++;
1371                         if ((txstat & RL_TXSTAT_TXABRT) ||
1372                             (txstat & RL_TXSTAT_OUTOFWIN))
1373                                 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1374                         oldthresh = sc->rl_txthresh;
1375                         /* error recovery */
1376                         rl_init_locked(sc);
1377                         /* restore original threshold */
1378                         sc->rl_txthresh = oldthresh;
1379                         return;
1380                 }
1381                 RL_INC(sc->rl_cdata.last_tx);
1382                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1383         } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1384
1385         if (RL_LAST_TXMBUF(sc) == NULL)
1386                 sc->rl_watchdog_timer = 0;
1387 }
1388
1389 static void
1390 rl_tick(void *xsc)
1391 {
1392         struct rl_softc         *sc = xsc;
1393         struct mii_data         *mii;
1394
1395         RL_LOCK_ASSERT(sc);
1396         mii = device_get_softc(sc->rl_miibus);
1397         mii_tick(mii);
1398         if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1399                 rl_miibus_statchg(sc->rl_dev);
1400
1401         rl_watchdog(sc);
1402
1403         callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1404 }
1405
1406 #ifdef DEVICE_POLLING
1407 static void
1408 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1409 {
1410         struct rl_softc *sc = ifp->if_softc;
1411
1412         RL_LOCK(sc);
1413         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1414                 rl_poll_locked(ifp, cmd, count);
1415         RL_UNLOCK(sc);
1416 }
1417
1418 static void
1419 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1420 {
1421         struct rl_softc *sc = ifp->if_softc;
1422
1423         RL_LOCK_ASSERT(sc);
1424
1425         sc->rxcycles = count;
1426         rl_rxeof(sc);
1427         rl_txeof(sc);
1428
1429         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1430                 rl_start_locked(ifp);
1431
1432         if (cmd == POLL_AND_CHECK_STATUS) {
1433                 uint16_t        status;
1434
1435                 /* We should also check the status register. */
1436                 status = CSR_READ_2(sc, RL_ISR);
1437                 if (status == 0xffff)
1438                         return;
1439                 if (status != 0)
1440                         CSR_WRITE_2(sc, RL_ISR, status);
1441
1442                 /* XXX We should check behaviour on receiver stalls. */
1443
1444                 if (status & RL_ISR_SYSTEM_ERR)
1445                         rl_init_locked(sc);
1446         }
1447 }
1448 #endif /* DEVICE_POLLING */
1449
1450 static void
1451 rl_intr(void *arg)
1452 {
1453         struct rl_softc         *sc = arg;
1454         struct ifnet            *ifp = sc->rl_ifp;
1455         uint16_t                status;
1456
1457         RL_LOCK(sc);
1458
1459         if (sc->suspended)
1460                 goto done_locked;
1461
1462 #ifdef DEVICE_POLLING
1463         if  (ifp->if_capenable & IFCAP_POLLING)
1464                 goto done_locked;
1465 #endif
1466
1467         for (;;) {
1468                 status = CSR_READ_2(sc, RL_ISR);
1469                 /* If the card has gone away, the read returns 0xffff. */
1470                 if (status == 0xffff)
1471                         break;
1472                 if (status != 0)
1473                         CSR_WRITE_2(sc, RL_ISR, status);
1474                 if ((status & RL_INTRS) == 0)
1475                         break;
1476                 if (status & RL_ISR_RX_OK)
1477                         rl_rxeof(sc);
1478                 if (status & RL_ISR_RX_ERR)
1479                         rl_rxeof(sc);
1480                 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1481                         rl_txeof(sc);
1482                 if (status & RL_ISR_SYSTEM_ERR)
1483                         rl_init_locked(sc);
1484         }
1485
1486         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1487                 rl_start_locked(ifp);
1488
1489 done_locked:
1490         RL_UNLOCK(sc);
1491 }
1492
1493 /*
1494  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1495  * pointers to the fragment pointers.
1496  */
1497 static int
1498 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1499 {
1500         struct mbuf             *m;
1501         bus_dma_segment_t       txsegs[1];
1502         int                     error, nsegs, padlen;
1503
1504         RL_LOCK_ASSERT(sc);
1505
1506         m = *m_head;
1507         padlen = 0;
1508         /*
1509          * Hardware doesn't auto-pad, so we have to make sure
1510          * pad short frames out to the minimum frame length.
1511          */
1512         if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1513                 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1514         /*
1515          * The RealTek is brain damaged and wants longword-aligned
1516          * TX buffers, plus we can only have one fragment buffer
1517          * per packet. We have to copy pretty much all the time.
1518          */
1519         if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1520             (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1521                 m = m_defrag(*m_head, M_DONTWAIT);
1522                 if (m == NULL) {
1523                         m_freem(*m_head);
1524                         *m_head = NULL;
1525                         return (ENOMEM);
1526                 }
1527         }
1528         *m_head = m;
1529
1530         if (padlen > 0) {
1531                 /*
1532                  * Make security concious people happy: zero out the
1533                  * bytes in the pad area, since we don't know what
1534                  * this mbuf cluster buffer's previous user might
1535                  * have left in it.
1536                  */
1537                 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1538                 m->m_pkthdr.len += padlen;
1539                 m->m_len = m->m_pkthdr.len;
1540         }
1541
1542         error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1543             RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1544         if (error != 0)
1545                 return (error);
1546         if (nsegs == 0) {
1547                 m_freem(*m_head);
1548                 *m_head = NULL;
1549                 return (EIO);
1550         }
1551
1552         RL_CUR_TXMBUF(sc) = m;
1553         bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1554             BUS_DMASYNC_PREWRITE);
1555         CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1556
1557         return (0);
1558 }
1559
1560 /*
1561  * Main transmit routine.
1562  */
1563 static void
1564 rl_start(struct ifnet *ifp)
1565 {
1566         struct rl_softc         *sc = ifp->if_softc;
1567
1568         RL_LOCK(sc);
1569         rl_start_locked(ifp);
1570         RL_UNLOCK(sc);
1571 }
1572
1573 static void
1574 rl_start_locked(struct ifnet *ifp)
1575 {
1576         struct rl_softc         *sc = ifp->if_softc;
1577         struct mbuf             *m_head = NULL;
1578
1579         RL_LOCK_ASSERT(sc);
1580
1581         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1582             IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1583                 return;
1584
1585         while (RL_CUR_TXMBUF(sc) == NULL) {
1586
1587                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1588
1589                 if (m_head == NULL)
1590                         break;
1591
1592                 if (rl_encap(sc, &m_head)) {
1593                         if (m_head == NULL)
1594                                 break;
1595                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1596                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1597                         break;
1598                 }
1599
1600                 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1601                 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1602
1603                 /* Transmit the frame. */
1604                 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1605                     RL_TXTHRESH(sc->rl_txthresh) |
1606                     RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1607
1608                 RL_INC(sc->rl_cdata.cur_tx);
1609
1610                 /* Set a timeout in case the chip goes out to lunch. */
1611                 sc->rl_watchdog_timer = 5;
1612         }
1613
1614         /*
1615          * We broke out of the loop because all our TX slots are
1616          * full. Mark the NIC as busy until it drains some of the
1617          * packets from the queue.
1618          */
1619         if (RL_CUR_TXMBUF(sc) != NULL)
1620                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1621 }
1622
1623 static void
1624 rl_init(void *xsc)
1625 {
1626         struct rl_softc         *sc = xsc;
1627
1628         RL_LOCK(sc);
1629         rl_init_locked(sc);
1630         RL_UNLOCK(sc);
1631 }
1632
1633 static void
1634 rl_init_locked(struct rl_softc *sc)
1635 {
1636         struct ifnet            *ifp = sc->rl_ifp;
1637         struct mii_data         *mii;
1638         uint32_t                rxcfg = 0;
1639         uint32_t                eaddr[2];
1640
1641         RL_LOCK_ASSERT(sc);
1642
1643         mii = device_get_softc(sc->rl_miibus);
1644
1645         /*
1646          * Cancel pending I/O and free all RX/TX buffers.
1647          */
1648         rl_stop(sc);
1649
1650         rl_reset(sc);
1651
1652         /*
1653          * Init our MAC address.  Even though the chipset
1654          * documentation doesn't mention it, we need to enter "Config
1655          * register write enable" mode to modify the ID registers.
1656          */
1657         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1658         bzero(eaddr, sizeof(eaddr));
1659         bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1660         CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1661         CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1662         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1663
1664         /* Init the RX memory block pointer register. */
1665         CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1666             RL_RX_8139_BUF_RESERVE);
1667         /* Init TX descriptors. */
1668         rl_list_tx_init(sc);
1669         /* Init Rx memory block. */
1670         rl_list_rx_init(sc);
1671
1672         /*
1673          * Enable transmit and receive.
1674          */
1675         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1676
1677         /*
1678          * Set the initial TX and RX configuration.
1679          */
1680         CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1681         CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1682
1683         /* Set the individual bit to receive frames for this host only. */
1684         rxcfg = CSR_READ_4(sc, RL_RXCFG);
1685         rxcfg |= RL_RXCFG_RX_INDIV;
1686
1687         /* If we want promiscuous mode, set the allframes bit. */
1688         if (ifp->if_flags & IFF_PROMISC) {
1689                 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1690                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1691         } else {
1692                 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1693                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1694         }
1695
1696         /* Set capture broadcast bit to capture broadcast frames. */
1697         if (ifp->if_flags & IFF_BROADCAST) {
1698                 rxcfg |= RL_RXCFG_RX_BROAD;
1699                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1700         } else {
1701                 rxcfg &= ~RL_RXCFG_RX_BROAD;
1702                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1703         }
1704
1705         /* Program the multicast filter, if necessary. */
1706         rl_setmulti(sc);
1707
1708 #ifdef DEVICE_POLLING
1709         /* Disable interrupts if we are polling. */
1710         if (ifp->if_capenable & IFCAP_POLLING)
1711                 CSR_WRITE_2(sc, RL_IMR, 0);
1712         else
1713 #endif
1714         /* Enable interrupts. */
1715         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1716
1717         /* Set initial TX threshold */
1718         sc->rl_txthresh = RL_TX_THRESH_INIT;
1719
1720         /* Start RX/TX process. */
1721         CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1722
1723         /* Enable receiver and transmitter. */
1724         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1725
1726         sc->rl_flags &= ~RL_FLAG_LINK;
1727         mii_mediachg(mii);
1728
1729         CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1730
1731         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1732         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1733
1734         callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1735 }
1736
1737 /*
1738  * Set media options.
1739  */
1740 static int
1741 rl_ifmedia_upd(struct ifnet *ifp)
1742 {
1743         struct rl_softc         *sc = ifp->if_softc;
1744         struct mii_data         *mii;
1745
1746         mii = device_get_softc(sc->rl_miibus);
1747
1748         RL_LOCK(sc);
1749         mii_mediachg(mii);
1750         RL_UNLOCK(sc);
1751
1752         return (0);
1753 }
1754
1755 /*
1756  * Report current media status.
1757  */
1758 static void
1759 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1760 {
1761         struct rl_softc         *sc = ifp->if_softc;
1762         struct mii_data         *mii;
1763
1764         mii = device_get_softc(sc->rl_miibus);
1765
1766         RL_LOCK(sc);
1767         mii_pollstat(mii);
1768         RL_UNLOCK(sc);
1769         ifmr->ifm_active = mii->mii_media_active;
1770         ifmr->ifm_status = mii->mii_media_status;
1771 }
1772
1773 static int
1774 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1775 {
1776         struct ifreq            *ifr = (struct ifreq *)data;
1777         struct mii_data         *mii;
1778         struct rl_softc         *sc = ifp->if_softc;
1779         int                     error = 0;
1780
1781         switch (command) {
1782         case SIOCSIFFLAGS:
1783                 RL_LOCK(sc);
1784                 if (ifp->if_flags & IFF_UP) {
1785                         rl_init_locked(sc);
1786                 } else {
1787                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1788                                 rl_stop(sc);
1789                 }
1790                 RL_UNLOCK(sc);
1791                 error = 0;
1792                 break;
1793         case SIOCADDMULTI:
1794         case SIOCDELMULTI:
1795                 RL_LOCK(sc);
1796                 rl_setmulti(sc);
1797                 RL_UNLOCK(sc);
1798                 error = 0;
1799                 break;
1800         case SIOCGIFMEDIA:
1801         case SIOCSIFMEDIA:
1802                 mii = device_get_softc(sc->rl_miibus);
1803                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1804                 break;
1805         case SIOCSIFCAP:
1806 #ifdef DEVICE_POLLING
1807                 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1808                     !(ifp->if_capenable & IFCAP_POLLING)) {
1809                         error = ether_poll_register(rl_poll, ifp);
1810                         if (error)
1811                                 return(error);
1812                         RL_LOCK(sc);
1813                         /* Disable interrupts */
1814                         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1815                         ifp->if_capenable |= IFCAP_POLLING;
1816                         RL_UNLOCK(sc);
1817                         return (error);
1818
1819                 }
1820                 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1821                     ifp->if_capenable & IFCAP_POLLING) {
1822                         error = ether_poll_deregister(ifp);
1823                         /* Enable interrupts. */
1824                         RL_LOCK(sc);
1825                         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1826                         ifp->if_capenable &= ~IFCAP_POLLING;
1827                         RL_UNLOCK(sc);
1828                         return (error);
1829                 }
1830 #endif /* DEVICE_POLLING */
1831                 break;
1832         default:
1833                 error = ether_ioctl(ifp, command, data);
1834                 break;
1835         }
1836
1837         return (error);
1838 }
1839
1840 static void
1841 rl_watchdog(struct rl_softc *sc)
1842 {
1843
1844         RL_LOCK_ASSERT(sc);
1845
1846         if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1847                 return;
1848
1849         device_printf(sc->rl_dev, "watchdog timeout\n");
1850         sc->rl_ifp->if_oerrors++;
1851
1852         rl_txeof(sc);
1853         rl_rxeof(sc);
1854         rl_init_locked(sc);
1855 }
1856
1857 /*
1858  * Stop the adapter and free any mbufs allocated to the
1859  * RX and TX lists.
1860  */
1861 static void
1862 rl_stop(struct rl_softc *sc)
1863 {
1864         register int            i;
1865         struct ifnet            *ifp = sc->rl_ifp;
1866
1867         RL_LOCK_ASSERT(sc);
1868
1869         sc->rl_watchdog_timer = 0;
1870         callout_stop(&sc->rl_stat_callout);
1871         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1872         sc->rl_flags &= ~RL_FLAG_LINK;
1873
1874         CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1875         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1876         for (i = 0; i < RL_TIMEOUT; i++) {
1877                 DELAY(10);
1878                 if ((CSR_READ_1(sc, RL_COMMAND) &
1879                     (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
1880                         break;
1881         }
1882         if (i == RL_TIMEOUT)
1883                 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
1884
1885         /*
1886          * Free the TX list buffers.
1887          */
1888         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1889                 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1890                         if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1891                                 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
1892                                     sc->rl_cdata.rl_tx_dmamap[i],
1893                                     BUS_DMASYNC_POSTWRITE);
1894                                 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1895                                     sc->rl_cdata.rl_tx_dmamap[i]);
1896                                 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1897                                 sc->rl_cdata.rl_tx_chain[i] = NULL;
1898                         }
1899                         CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1900                             0x0000000);
1901                 }
1902         }
1903 }
1904
1905 /*
1906  * Device suspend routine.  Stop the interface and save some PCI
1907  * settings in case the BIOS doesn't restore them properly on
1908  * resume.
1909  */
1910 static int
1911 rl_suspend(device_t dev)
1912 {
1913         struct rl_softc         *sc;
1914
1915         sc = device_get_softc(dev);
1916
1917         RL_LOCK(sc);
1918         rl_stop(sc);
1919         sc->suspended = 1;
1920         RL_UNLOCK(sc);
1921
1922         return (0);
1923 }
1924
1925 /*
1926  * Device resume routine.  Restore some PCI settings in case the BIOS
1927  * doesn't, re-enable busmastering, and restart the interface if
1928  * appropriate.
1929  */
1930 static int
1931 rl_resume(device_t dev)
1932 {
1933         struct rl_softc         *sc;
1934         struct ifnet            *ifp;
1935
1936         sc = device_get_softc(dev);
1937         ifp = sc->rl_ifp;
1938
1939         RL_LOCK(sc);
1940
1941         /* reinitialize interface if necessary */
1942         if (ifp->if_flags & IFF_UP)
1943                 rl_init_locked(sc);
1944
1945         sc->suspended = 0;
1946
1947         RL_UNLOCK(sc);
1948
1949         return (0);
1950 }
1951
1952 /*
1953  * Stop all chip I/O so that the kernel's probe routines don't
1954  * get confused by errant DMAs when rebooting.
1955  */
1956 static int
1957 rl_shutdown(device_t dev)
1958 {
1959         struct rl_softc         *sc;
1960
1961         sc = device_get_softc(dev);
1962
1963         RL_LOCK(sc);
1964         rl_stop(sc);
1965         RL_UNLOCK(sc);
1966
1967         return (0);
1968 }