sys/powerpc/powerpc/trap_subr.S

   1 /* $FreeBSD$ */
   2 /* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
   3
   4 /*-
   5  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
   6  * Copyright (C) 1995, 1996 TooLs GmbH.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed by TooLs GmbH.
  20  * 4. The name of TooLs GmbH may not be used to endorse or promote products
  21  *    derived from this software without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
  24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  26  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  28  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  29  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  31  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  32  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /*
  36  * NOTICE: This is not a standalone file.  to use it, #include it in
  37  * your port's locore.S, like so:
  38  *
  39  *      #include <powerpc/powerpc/trap_subr.S>
  40  */
  41
  42 /*
  43  * Save/restore segment registers
  44  */
  45 #define RESTORE_SRS(pmap,sr)    mtsr    0,sr; \
  46         lwz     sr,1*4(pmap);   mtsr    1,sr; \
  47         lwz     sr,2*4(pmap);   mtsr    2,sr; \
  48         lwz     sr,3*4(pmap);   mtsr    3,sr; \
  49         lwz     sr,4*4(pmap);   mtsr    4,sr; \
  50         lwz     sr,5*4(pmap);   mtsr    5,sr; \
  51         lwz     sr,6*4(pmap);   mtsr    6,sr; \
  52         lwz     sr,7*4(pmap);   mtsr    7,sr; \
  53         lwz     sr,8*4(pmap);   mtsr    8,sr; \
  54         lwz     sr,9*4(pmap);   mtsr    9,sr; \
  55         lwz     sr,10*4(pmap);  mtsr    10,sr; \
  56         lwz     sr,11*4(pmap);  mtsr    11,sr; \
  57         lwz     sr,12*4(pmap);  mtsr    12,sr; \
  58         lwz     sr,13*4(pmap);  mtsr    13,sr; \
  59         lwz     sr,14*4(pmap);  mtsr    14,sr; \
  60         lwz     sr,15*4(pmap);  mtsr    15,sr; isync;
  61
  62 /*
  63  * User SRs are loaded through a pointer to the current pmap.
  64  */
  65 #define RESTORE_USER_SRS(pmap,sr) \
  66         GET_CPUINFO(pmap); \
  67         lwz     pmap,PC_CURPMAP(pmap); \
  68         lwzu    sr,PM_SR(pmap); \
  69         RESTORE_SRS(pmap,sr)
  70
  71 /*
  72  * Kernel SRs are loaded directly from kernel_pmap_
  73  */
  74 #define RESTORE_KERN_SRS(pmap,sr) \
  75         lis     pmap,CNAME(kernel_pmap_store)@ha; \
  76         lwzu    sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \
  77         RESTORE_SRS(pmap,sr)
  78
  79 /*
  80  * FRAME_SETUP assumes:
  81  *      SPRG1           SP (1)
  82  *      SPRG3           trap type
  83  *      savearea        r28-r31,DAR,DSISR   (DAR & DSISR only for DSI traps)
  84  *      r28             LR
  85  *      r29             CR
  86  *      r30             scratch
  87  *      r31             scratch
  88  *      r1              kernel stack
  89  *      SRR0/1          as at start of trap
  90  */
  91 #define FRAME_SETUP(savearea)                                           \
  92 /* Have to enable translation to allow access of kernel stack: */       \
  93         GET_CPUINFO(%r31);                                              \
  94         mfsrr0  %r30;                                                   \
  95         stw     %r30,(savearea+CPUSAVE_SRR0)(%r31);     /* save SRR0 */ \
  96         mfsrr1  %r30;                                                   \
  97         stw     %r30,(savearea+CPUSAVE_SRR1)(%r31);     /* save SRR1 */ \
  98         mfmsr   %r30;                                                   \
  99         ori     %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
 100         mtmsr   %r30;                   /* stack can now be accessed */ \
 101         isync;                                                          \
 102         mfsprg1 %r31;                   /* get saved SP */              \
 103         stwu    %r31,-FRAMELEN(%r1);    /* save it in the callframe */  \
 104         stw     %r0, FRAME_0+8(%r1);    /* save r0 in the trapframe */  \
 105         stw     %r31,FRAME_1+8(%r1);    /* save SP   "      "       */  \
 106         stw     %r2, FRAME_2+8(%r1);    /* save r2   "      "       */  \
 107         stw     %r28,FRAME_LR+8(%r1);   /* save LR   "      "       */  \
 108         stw     %r29,FRAME_CR+8(%r1);   /* save CR   "      "       */  \
 109         GET_CPUINFO(%r2);                                               \
 110         lwz     %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */   \
 111         lwz     %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */   \
 112         lwz     %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */   \
 113         lwz     %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */   \
 114         stw     %r3,  FRAME_3+8(%r1);   /* save r3-r31 */               \
 115         stw     %r4,  FRAME_4+8(%r1);                                   \
 116         stw     %r5,  FRAME_5+8(%r1);                                   \
 117         stw     %r6,  FRAME_6+8(%r1);                                   \
 118         stw     %r7,  FRAME_7+8(%r1);                                   \
 119         stw     %r8,  FRAME_8+8(%r1);                                   \
 120         stw     %r9,  FRAME_9+8(%r1);                                   \
 121         stw     %r10, FRAME_10+8(%r1);                                  \
 122         stw     %r11, FRAME_11+8(%r1);                                  \
 123         stw     %r12, FRAME_12+8(%r1);                                  \
 124         stw     %r13, FRAME_13+8(%r1);                                  \
 125         stw     %r14, FRAME_14+8(%r1);                                  \
 126         stw     %r15, FRAME_15+8(%r1);                                  \
 127         stw     %r16, FRAME_16+8(%r1);                                  \
 128         stw     %r17, FRAME_17+8(%r1);                                  \
 129         stw     %r18, FRAME_18+8(%r1);                                  \
 130         stw     %r19, FRAME_19+8(%r1);                                  \
 131         stw     %r20, FRAME_20+8(%r1);                                  \
 132         stw     %r21, FRAME_21+8(%r1);                                  \
 133         stw     %r22, FRAME_22+8(%r1);                                  \
 134         stw     %r23, FRAME_23+8(%r1);                                  \
 135         stw     %r24, FRAME_24+8(%r1);                                  \
 136         stw     %r25, FRAME_25+8(%r1);                                  \
 137         stw     %r26, FRAME_26+8(%r1);                                  \
 138         stw     %r27, FRAME_27+8(%r1);                                  \
 139         stw     %r28, FRAME_28+8(%r1);                                  \
 140         stw     %r29, FRAME_29+8(%r1);                                  \
 141         stw     %r30, FRAME_30+8(%r1);                                  \
 142         stw     %r31, FRAME_31+8(%r1);                                  \
 143         lwz     %r28,(savearea+CPUSAVE_DAR)(%r2);  /* saved DAR */      \
 144         lwz     %r29,(savearea+CPUSAVE_DSISR)(%r2);/* saved DSISR */    \
 145         lwz     %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */     \
 146         lwz     %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */     \
 147         mfxer   %r3;                                                    \
 148         mfctr   %r4;                                                    \
 149         mfsprg3 %r5;                                                    \
 150         stw     %r3, FRAME_XER+8(1);    /* save xer/ctr/exc */          \
 151         stw     %r4, FRAME_CTR+8(1);                                    \
 152         stw     %r5, FRAME_EXC+8(1);                                    \
 153         stw     %r28,FRAME_DAR+8(1);                                    \
 154         stw     %r29,FRAME_DSISR+8(1);  /* save dsisr/srr0/srr1 */      \
 155         stw     %r30,FRAME_SRR0+8(1);                                   \
 156         stw     %r31,FRAME_SRR1+8(1)
 157
 158 #define FRAME_LEAVE(savearea)                                           \
 159 /* Now restore regs: */                                                 \
 160         lwz     %r2,FRAME_SRR0+8(%r1);                                  \
 161         lwz     %r3,FRAME_SRR1+8(%r1);                                  \
 162         lwz     %r4,FRAME_CTR+8(%r1);                                   \
 163         lwz     %r5,FRAME_XER+8(%r1);                                   \
 164         lwz     %r6,FRAME_LR+8(%r1);                                    \
 165         GET_CPUINFO(%r7);                                               \
 166         stw     %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */       \
 167         stw     %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */       \
 168         lwz     %r7,FRAME_CR+8(%r1);                                    \
 169         mtctr   %r4;                                                    \
 170         mtxer   %r5;                                                    \
 171         mtlr    %r6;                                                    \
 172         mtsprg1 %r7;                    /* save cr */                   \
 173         lwz     %r31,FRAME_31+8(%r1);   /* restore r0-31 */             \
 174         lwz     %r30,FRAME_30+8(%r1);                                   \
 175         lwz     %r29,FRAME_29+8(%r1);                                   \
 176         lwz     %r28,FRAME_28+8(%r1);                                   \
 177         lwz     %r27,FRAME_27+8(%r1);                                   \
 178         lwz     %r26,FRAME_26+8(%r1);                                   \
 179         lwz     %r25,FRAME_25+8(%r1);                                   \
 180         lwz     %r24,FRAME_24+8(%r1);                                   \
 181         lwz     %r23,FRAME_23+8(%r1);                                   \
 182         lwz     %r22,FRAME_22+8(%r1);                                   \
 183         lwz     %r21,FRAME_21+8(%r1);                                   \
 184         lwz     %r20,FRAME_20+8(%r1);                                   \
 185         lwz     %r19,FRAME_19+8(%r1);                                   \
 186         lwz     %r18,FRAME_18+8(%r1);                                   \
 187         lwz     %r17,FRAME_17+8(%r1);                                   \
 188         lwz     %r16,FRAME_16+8(%r1);                                   \
 189         lwz     %r15,FRAME_15+8(%r1);                                   \
 190         lwz     %r14,FRAME_14+8(%r1);                                   \
 191         lwz     %r13,FRAME_13+8(%r1);                                   \
 192         lwz     %r12,FRAME_12+8(%r1);                                   \
 193         lwz     %r11,FRAME_11+8(%r1);                                   \
 194         lwz     %r10,FRAME_10+8(%r1);                                   \
 195         lwz     %r9, FRAME_9+8(%r1);                                    \
 196         lwz     %r8, FRAME_8+8(%r1);                                    \
 197         lwz     %r7, FRAME_7+8(%r1);                                    \
 198         lwz     %r6, FRAME_6+8(%r1);                                    \
 199         lwz     %r5, FRAME_5+8(%r1);                                    \
 200         lwz     %r4, FRAME_4+8(%r1);                                    \
 201         lwz     %r3, FRAME_3+8(%r1);                                    \
 202         lwz     %r2, FRAME_2+8(%r1);                                    \
 203         lwz     %r0, FRAME_0+8(%r1);                                    \
 204         lwz     %r1, FRAME_1+8(%r1);                                    \
 205 /* Can't touch %r1 from here on */                                      \
 206         mtsprg2 %r2;                    /* save r2 & r3 */              \
 207         mtsprg3 %r3;                                                    \
 208 /* Disable translation, machine check and recoverability: */            \
 209         mfmsr   %r2;                                                    \
 210         andi.   %r2,%r2,~(PSL_DR|PSL_IR|PSL_EE|PSL_ME|PSL_RI)@l;        \
 211         mtmsr   %r2;                                                    \
 212         isync;                                                          \
 213 /* Decide whether we return to user mode: */                            \
 214         GET_CPUINFO(%r2);                                               \
 215         lwz     %r3,(savearea+CPUSAVE_SRR1)(%r2);                       \
 216         mtcr    %r3;                                                    \
 217         bf      17,1f;                  /* branch if PSL_PR is false */ \
 218 /* Restore user SRs */                                                  \
 219         RESTORE_USER_SRS(%r2,%r3);                                      \
 220 1:      mfsprg1 %r2;                    /* restore cr */                \
 221         mtcr    %r2;                                                    \
 222         GET_CPUINFO(%r2);                                               \
 223         lwz     %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */    \
 224         mtsrr0  %r3;                                                    \
 225         lwz     %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */    \
 226         mtsrr1  %r3;                                                    \
 227         mfsprg2 %r2;                    /* restore r2 & r3 */           \
 228         mfsprg3 %r3
 229
 230 #ifdef KDB
 231 /*
 232  * Define the kdb debugger stack
 233  */
 234         .data
 235 GLOBAL(dbstk)
 236         .space INTSTK+8                 /* kdb stack */
 237 #endif
 238
 239 /*
 240  * This code gets copied to all the trap vectors
 241  * (except ISI/DSI, ALI, and the interrupts)
 242  */
 243         .text
 244         .globl  CNAME(trapcode),CNAME(trapsize)
 245 CNAME(trapcode):
 246         mtsprg1 %r1                     /* save SP */
 247         mflr    %r1                     /* Save the old LR in r1 */
 248         mtsprg2 %r1                     /* And then in SPRG2 */
 249         li      %r1, 0x20               /* How to get the vector from LR */
 250         bla     generictrap             /* LR & SPRG3 is exception # */
 251 CNAME(trapsize) = .-CNAME(trapcode)
 252
 253 /*
 254  * For ALI: has to save DSISR and DAR
 255  */
 256         .globl  CNAME(alitrap),CNAME(alisize)
 257 CNAME(alitrap):
 258         mtsprg1 %r1                     /* save SP */
 259         GET_CPUINFO(%r1)
 260         stw     %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)     /* free r28-r31 */
 261         stw     %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
 262         stw     %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
 263         stw     %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
 264         mfdar   %r30
 265         mfdsisr %r31
 266         stw     %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1)
 267         stw     %r31,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1)
 268         mfsprg1 %r1                     /* restore SP, in case of branch */
 269         mflr    %r28                    /* save LR */
 270         mfcr    %r29                    /* save CR */
 271
 272         /* Put our exception vector in SPRG3 */
 273         li      %r31, EXC_ALI
 274         mtsprg3 %r31
 275
 276         /* Test whether we already had PR set */
 277         mfsrr1  %r31
 278         mtcr    %r31
 279         bla     s_trap
 280 CNAME(alisize) = .-CNAME(alitrap)
 281
 282 /*
 283  * Similar to the above for DSI
 284  * Has to handle BAT spills
 285  * and standard pagetable spills
 286  */
 287         .globl  CNAME(dsitrap),CNAME(dsisize)
 288 CNAME(dsitrap):
 289         mtsprg1 %r1                     /* save SP */
 290         GET_CPUINFO(%r1)
 291         stw     %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1)     /* free r28-r31 */
 292         stw     %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
 293         stw     %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
 294         stw     %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
 295         mfsprg1 %r1                     /* restore SP */
 296         mfcr    %r29                    /* save CR */
 297         mfxer   %r30                    /* save XER */
 298         mtsprg2 %r30                    /* in SPRG2 */
 299         mfsrr1  %r31                    /* test kernel mode */
 300         mtcr    %r31
 301         bt      17,1f                   /* branch if PSL_PR is set */
 302         mfdar   %r31                    /* get fault address */
 303         rlwinm  %r31,%r31,7,25,28       /* get segment * 8 */
 304
 305         /* get batu */
 306         addis   %r31,%r31,CNAME(battable)@ha
 307         lwz     %r30,CNAME(battable)@l(31)
 308         mtcr    %r30
 309         bf      30,1f                   /* branch if supervisor valid is
 310                                            false */
 311         /* get batl */
 312         lwz     %r31,CNAME(battable)+4@l(31)
 313 /* We randomly use the highest two bat registers here */
 314         mftb    %r28
 315         andi.   %r28,%r28,1
 316         bne     2f
 317         mtdbatu 2,%r30
 318         mtdbatl 2,%r31
 319         b       3f
 320 2:
 321         mtdbatu 3,%r30
 322         mtdbatl 3,%r31
 323 3:
 324         mfsprg2 %r30                    /* restore XER */
 325         mtxer   %r30
 326         mtcr    %r29                    /* restore CR */
 327         mtsprg1 %r1
 328         GET_CPUINFO(%r1)
 329         lwz     %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1)     /* restore r28-r31 */
 330         lwz     %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
 331         lwz     %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
 332         lwz     %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
 333         mfsprg1 %r1
 334         rfi                             /* return to trapped code */
 335 1:
 336         mflr    %r28                    /* save LR (SP already saved) */
 337         bla     disitrap
 338 CNAME(dsisize) = .-CNAME(dsitrap)
 339
 340 /*
 341  * Preamble code for DSI/ISI traps
 342  */
 343 disitrap:
 344         /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
 345         mflr    %r1
 346         andi.   %r1,%r1,0xff00
 347         mtsprg3 %r1
 348
 349         GET_CPUINFO(%r1)
 350         lwz     %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
 351         stw     %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
 352         lwz     %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
 353         stw     %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
 354         lwz     %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
 355         stw     %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
 356         lwz     %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
 357         stw     %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
 358         mfdar   %r30
 359         mfdsisr %r31
 360         stw     %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1)
 361         stw     %r31,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1)
 362
 363 #ifdef KDB
 364         /* Try and detect a kernel stack overflow */
 365         mfsrr1  %r31
 366         mtcr    %r31
 367         bt      17,realtrap             /* branch is user mode */
 368         mfsprg1 %r31                    /* get old SP */
 369         sub.    %r30,%r31,%r30          /* SP - DAR */
 370         bge     1f
 371         neg     %r30,%r30               /* modulo value */
 372 1:      cmplwi  %cr0,%r30,4096          /* is DAR within a page of SP? */
 373         bge     %cr0,realtrap           /* no, too far away. */
 374
 375         /* Now convert this DSI into a DDB trap.  */
 376         GET_CPUINFO(%r1)
 377         lwz     %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1) /* get DAR */
 378         stw     %r30,(PC_DBSAVE  +CPUSAVE_DAR)(%r1) /* save DAR */
 379         lwz     %r30,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1) /* get DSISR */
 380         lwz     %r30,(PC_DBSAVE  +CPUSAVE_DSISR)(%r1) /* save DSISR */
 381         lwz     %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get  r28 */
 382         stw     %r30,(PC_DBSAVE  +CPUSAVE_R28)(%r1) /* save r28 */
 383         lwz     %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get  r29 */
 384         stw     %r31,(PC_DBSAVE  +CPUSAVE_R29)(%r1) /* save r29 */
 385         lwz     %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get  r30 */
 386         stw     %r30,(PC_DBSAVE  +CPUSAVE_R30)(%r1) /* save r30 */
 387         lwz     %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get  r31 */
 388         stw     %r31,(PC_DBSAVE  +CPUSAVE_R31)(%r1) /* save r31 */
 389         lis     %r1,dbstk+INTSTK@ha     /* get new SP */
 390         addi    %r1,%r1,dbstk+INTSTK@l
 391         b       dbtrap
 392 #endif
 393
 394         /* XXX need stack probe here */
 395 realtrap:
 396 /* Test whether we already had PR set */
 397         mfsrr1  %r1
 398         mtcr    %r1
 399         mfsprg1 %r1                     /* restore SP (might have been
 400                                            overwritten) */
 401         bf      17,k_trap               /* branch if PSL_PR is false */
 402         GET_CPUINFO(%r1)
 403         lwz     %r1,PC_CURPCB(%r1)
 404         RESTORE_KERN_SRS(%r30,%r31)     /* enable kernel mapping */
 405         ba s_trap
 406
 407 /*
 408  * generictrap does some standard setup for trap handling to minimize
 409  * the code that need be installed in the actual vectors. It expects
 410  * the following conditions.
 411  *
 412  * R1 - Trap vector = LR & (0xff00 | R1)
 413  * SPRG1 - Original R1 contents
 414  * SPRG2 - Original LR
 415  */
 416
 417 generictrap:
 418         /* Save R1 for computing the exception vector */
 419         mtsprg3 %r1
 420
 421         /* Save interesting registers */
 422         GET_CPUINFO(%r1)
 423         stw     %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)     /* free r28-r31 */
 424         stw     %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
 425         stw     %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
 426         stw     %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
 427         mfsprg1 %r1                     /* restore SP, in case of branch */
 428         mfsprg2 %r28                    /* save LR */
 429         mfcr    %r29                    /* save CR */
 430
 431         /* Compute the exception vector from the link register */
 432         mfsprg3 %r31
 433         ori     %r31,%r31,0xff00
 434         mflr    %r30
 435         and     %r30,%r30,%r31
 436         mtsprg3 %r30
 437
 438         /* Test whether we already had PR set */
 439         mfsrr1  %r31
 440         mtcr    %r31
 441
 442 s_trap:
 443         bf      17,k_trap               /* branch if PSL_PR is false */
 444         GET_CPUINFO(%r1)
 445 u_trap:
 446         lwz     %r1,PC_CURPCB(%r1)
 447         RESTORE_KERN_SRS(%r30,%r31)     /* enable kernel mapping */
 448
 449 /*
 450  * Now the common trap catching code.
 451  */
 452 k_trap:
 453         FRAME_SETUP(PC_TEMPSAVE)
 454 /* Call C interrupt dispatcher: */
 455 trapagain:
 456         addi    %r3,%r1,8
 457         bl      CNAME(powerpc_interrupt)
 458         .globl  CNAME(trapexit)         /* backtrace code sentinel */
 459 CNAME(trapexit):
 460
 461 /* Disable interrupts: */
 462         mfmsr   %r3
 463         andi.   %r3,%r3,~PSL_EE@l
 464         mtmsr   %r3
 465 /* Test AST pending: */
 466         lwz     %r5,FRAME_SRR1+8(%r1)
 467         mtcr    %r5
 468         bf      17,1f                   /* branch if PSL_PR is false */
 469
 470         GET_CPUINFO(%r3)                /* get per-CPU pointer */
 471         lwz     %r4, PC_CURTHREAD(%r3)  /* deref to get curthread */
 472         lwz     %r4, TD_FLAGS(%r4)      /* get thread flags value */
 473         lis     %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
 474         ori     %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
 475         and.    %r4,%r4,%r5
 476         beq     1f
 477         mfmsr   %r3                     /* re-enable interrupts */
 478         ori     %r3,%r3,PSL_EE@l
 479         mtmsr   %r3
 480         isync
 481         addi    %r3,%r1,8
 482         bl      CNAME(ast)
 483         .globl  CNAME(asttrapexit)      /* backtrace code sentinel #2 */
 484 CNAME(asttrapexit):
 485         b       trapexit                /* test ast ret value ? */
 486 1:
 487         FRAME_LEAVE(PC_TEMPSAVE)
 488         rfi
 489
 490 #if defined(KDB)
 491 /*
 492  * Deliberate entry to dbtrap
 493  */
 494         .globl  CNAME(ppc_db_trap)
 495 CNAME(ppc_db_trap):
 496         mtsprg1 %r1
 497         mfmsr   %r3
 498         mtsrr1  %r3
 499         andi.   %r3,%r3,~(PSL_EE|PSL_ME)@l
 500         mtmsr   %r3                     /* disable interrupts */
 501         isync
 502         GET_CPUINFO(%r3)
 503         stw     %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3)
 504         stw     %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3)
 505         stw     %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3)
 506         stw     %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3)
 507         mflr    %r28
 508         li      %r29,EXC_BPT
 509         mtlr    %r29
 510         mfcr    %r29
 511         mtsrr0  %r28
 512
 513 /*
 514  * Now the kdb trap catching code.
 515  */
 516 dbtrap:
 517         /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
 518         mflr    %r31
 519         andi.   %r31,%r31,0xff00
 520         mtsprg3 %r31
 521
 522         FRAME_SETUP(PC_DBSAVE)
 523 /* Call C trap code: */
 524         addi    %r3,%r1,8
 525         bl      CNAME(db_trap_glue)
 526         or.     %r3,%r3,%r3
 527         bne     dbleave
 528 /* This wasn't for KDB, so switch to real trap: */
 529         lwz     %r3,FRAME_EXC+8(%r1)    /* save exception */
 530         GET_CPUINFO(%r4)
 531         stw     %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4)
 532         FRAME_LEAVE(PC_DBSAVE)
 533         mtsprg1 %r1                     /* prepare for entrance to realtrap */
 534         GET_CPUINFO(%r1)
 535         stw     %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
 536         stw     %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
 537         stw     %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
 538         stw     %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
 539         mflr    %r28
 540         mfcr    %r29
 541         lwz     %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1)
 542         mtsprg3 %r31                    /* SPRG3 was clobbered by FRAME_LEAVE */
 543         mfsprg1 %r1
 544         b       realtrap
 545 dbleave:
 546         FRAME_LEAVE(PC_DBSAVE)
 547         rfi
 548
 549 /*
 550  * In case of KDB we want a separate trap catcher for it
 551  */
 552         .globl  CNAME(dblow),CNAME(dbsize)
 553 CNAME(dblow):
 554         mtsprg1 %r1                     /* save SP */
 555         mtsprg2 %r29                    /* save r29 */
 556         mfcr    %r29                    /* save CR in r29 */
 557         mfsrr1  %r1
 558         mtcr    %r1
 559         bf      17,1f                   /* branch if privileged */
 560
 561         /* Unprivileged case */
 562         mtcr    %r29                    /* put the condition register back */
 563         mfsprg2 %r29                    /* ... and r29 */
 564         mflr    %r1                     /* save LR */
 565         mtsprg2 %r1                     /* And then in SPRG2 */
 566         li      %r1, 0                  /* How to get the vector from LR */
 567
 568         bla     generictrap             /* and we look like a generic trap */
 569 1:
 570         /* Privileged, so drop to KDB */
 571         GET_CPUINFO(%r1)
 572         stw     %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1)       /* free r28 */
 573         mfsprg2 %r28                            /* r29 holds cr...  */
 574         stw     %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1)       /* free r29 */
 575         stw     %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1)       /* free r30 */
 576         stw     %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1)       /* free r31 */
 577         mflr    %r28                                    /* save LR */
 578         lis     %r1,dbstk+INTSTK@ha     /* get new SP */
 579         addi    %r1,%r1,dbstk+INTSTK@l
 580         bla     dbtrap
 581 CNAME(dbsize) = .-CNAME(dblow)
 582 #endif /* KDB */