2 * Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Berkeley Software Design Inc's name may not be used to endorse or
13 * promote products derived from this software without specific prior
16 * THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * from: BSDI: asi.h,v 1.3 1997/08/08 14:31:42 torek
32 #ifndef _MACHINE_ASI_H_
33 #define _MACHINE_ASI_H_
42 #define ASI_AIUPL 0x18
43 #define ASI_AIUSL 0x19
54 * UltraSPARC extensions. ASIs limited to a certain family are annotated.
56 #define ASI_PHYS_USE_EC 0x14
57 #define ASI_PHYS_BYPASS_EC_WITH_EBIT 0x15
58 #define ASI_PHYS_USE_EC_L 0x1c
59 #define ASI_PHYS_BYPASS_EC_WITH_EBIT_L 0x1d
61 #define ASI_NUCLEUS_QUAD_LDD 0x24
62 #define ASI_NUCLEUS_QUAD_LDD_L 0x2c
64 #define ASI_PCACHE_STATUS_DATA 0x30 /* US-III Cu */
65 #define ASI_PCACHE_DATA 0x31 /* US-III Cu */
66 #define ASI_PCACHE_TAG 0x32 /* US-III Cu */
67 #define ASI_PCACHE_SNOOP_TAG 0x33 /* US-III Cu */
69 #define ASI_ATOMIC_QUAD_LDD_PHYS 0x34 /* US-III Cu */
71 #define ASI_WCACHE_VALID_BITS 0x38 /* US-III Cu */
72 #define ASI_WCACHE_DATA 0x39 /* US-III Cu */
73 #define ASI_WCACHE_TAG 0x3a /* US-III Cu */
74 #define ASI_WCACHE_SNOOP_TAG 0x3b /* US-III Cu */
76 #define ASI_ATOMIC_QUAD_LDD_PHYS_L 0x3c /* US-III Cu */
78 #define ASI_SRAM_FAST_INIT 0x40 /* US-III Cu */
80 #define ASI_DCACHE_INVALIDATE 0x42 /* US-III Cu */
81 #define ASI_DCACHE_UTAG 0x43 /* US-III Cu */
82 #define ASI_DCACHE_SNOOP_TAG 0x44 /* US-III Cu */
84 /* Named ASI_DCUCR on US-III, but is mostly identical except for added bits. */
85 #define ASI_LSU_CTL_REG 0x45
87 #define ASI_DCACHE_DATA 0x46
88 #define ASI_DCACHE_TAG 0x47
90 #define ASI_INTR_DISPATCH_STATUS 0x48
91 #define ASI_INTR_RECEIVE 0x49
92 #define ASI_UPA_CONFIG_REG 0x4a /* US-I, II */
94 #define ASI_FIREPLANE_CONFIG_REG 0x4a /* US-III Cu */
95 #define AA_FIREPLANE_CONFIG 0x0 /* US-III Cu */
96 #define AA_FIREPLANE_ADDRESS 0x8 /* US-III Cu */
98 #define ASI_ESTATE_ERROR_EN_REG 0x4b
99 #define AA_ESTATE_CEEN 0x1
100 #define AA_ESTATE_NCEEN 0x2
101 #define AA_ESTATE_ISAPEN 0x4
103 #define ASI_AFSR 0x4c
104 #define ASI_AFAR 0x4d
106 #define ASI_ECACHE_TAG_DATA 0x4e
108 #define ASI_IMMU_TAG_TARGET_REG 0x50
109 #define ASI_IMMU 0x50
110 #define AA_IMMU_TTR 0x0
111 #define AA_IMMU_SFSR 0x18
112 #define AA_IMMU_TSB 0x28
113 #define AA_IMMU_TAR 0x30
114 #define AA_IMMU_TSB_PEXT_REG 0x48 /* US-III family */
115 #define AA_IMMU_TSB_SEXT_REG 0x50 /* US-III family */
116 #define AA_IMMU_TSB_NEXT_REG 0x58 /* US-III family */
118 #define ASI_IMMU_TSB_8KB_PTR_REG 0x51
119 #define ASI_IMMU_TSB_64KB_PTR_REG 0x52
121 #define ASI_SERIAL_ID 0x53 /* US-III family */
123 #define ASI_ITLB_DATA_IN_REG 0x54
124 /* US-III Cu: also ASI_ITLB_CAM_ADDRESS_REG */
125 #define ASI_ITLB_DATA_ACCESS_REG 0x55
126 #define ASI_ITLB_TAG_READ_REG 0x56
127 #define ASI_IMMU_DEMAP 0x57
129 #define ASI_DMMU_TAG_TARGET_REG 0x58
130 #define ASI_DMMU 0x58
131 #define AA_DMMU_TTR 0x0
132 #define AA_DMMU_PCXR 0x8
133 #define AA_DMMU_SCXR 0x10
134 #define AA_DMMU_SFSR 0x18
135 #define AA_DMMU_SFAR 0x20
136 #define AA_DMMU_TSB 0x28
137 #define AA_DMMU_TAR 0x30
138 #define AA_DMMU_VWPR 0x38
139 #define AA_DMMU_PWPR 0x40
140 #define AA_DMMU_TSB_PEXT_REG 0x48
141 #define AA_DMMU_TSB_SEXT_REG 0x50
142 #define AA_DMMU_TSB_NEXT_REG 0x58
143 #define AA_DMMU_TAG_ACCESS_EXT 0x60 /* US-III family */
145 #define ASI_DMMU_TSB_8KB_PTR_REG 0x59
146 #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
147 #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
148 #define ASI_DTLB_DATA_IN_REG 0x5c
149 /* US-III Cu: also ASI_DTLB_CAM_ADDRESS_REG */
150 #define ASI_DTLB_DATA_ACCESS_REG 0x5d
151 #define ASI_DTLB_TAG_READ_REG 0x5e
152 #define ASI_DMMU_DEMAP 0x5f
154 #define ASI_IIU_INST_TRAP 0x60 /* US-III family */
156 #define ASI_ICACHE_INSTR 0x66
157 #define ASI_ICACHE_TAG 0x67
158 #define ASI_ICACHE_SNOOP_TAG 0x68 /* US-III family */
159 #define ASI_ICACHE_PRE_DECODE 0x6e /* US-I, II */
160 #define ASI_ICACHE_PRE_NEXT_FIELD 0x6f /* US-I, II */
162 #define ASI_BLK_AUIP 0x70
163 #define ASI_BLK_AIUS 0x71
165 #define ASI_MCU_CONFIG_REG 0x72 /* US-III Cu */
166 #define AA_MCU_TIMING1_REG 0x0 /* US-III Cu */
167 #define AA_MCU_TIMING2_REG 0x8 /* US-III Cu */
168 #define AA_MCU_TIMING3_REG 0x10 /* US-III Cu */
169 #define AA_MCU_TIMING4_REG 0x18 /* US-III Cu */
170 #define AA_MCU_DEC1_REG 0x20 /* US-III Cu */
171 #define AA_MCU_DEC2_REG 0x28 /* US-III Cu */
172 #define AA_MCU_DEC3_REG 0x30 /* US-III Cu */
173 #define AA_MCU_DEC4_REG 0x38 /* US-III Cu */
174 #define AA_MCU_ADDR_CNTL_REG 0x40 /* US-III Cu */
176 #define ASI_ECACHE_DATA 0x74 /* US-III Cu */
177 #define ASI_ECACHE_CONTROL 0x75 /* US-III Cu */
178 #define ASI_ECACHE_W 0x76
181 * With the advent of the US-III, the numbering has changed, as additional
182 * registers were inserted in between. We retain the original ordering for
183 * now, and append an A to the inserted registers.
184 * Exceptions are AA_SDB_INTR_D6 and AA_SDB_INTR_D7, which were appended
187 #define ASI_SDB_ERROR_W 0x77
188 #define ASI_SDB_CONTROL_W 0x77
189 #define ASI_SDB_INTR_W 0x77
190 #define AA_SDB_ERR_HIGH 0x0
191 #define AA_SDB_ERR_LOW 0x18
192 #define AA_SDB_CNTL_HIGH 0x20
193 #define AA_SDB_CNTL_LOW 0x38
194 #define AA_SDB_INTR_D0 0x40
195 #define AA_SDB_INTR_D0A 0x48 /* US-III family */
196 #define AA_SDB_INTR_D1 0x50
197 #define AA_SDB_INTR_D1A 0x5A /* US-III family */
198 #define AA_SDB_INTR_D2 0x60
199 #define AA_SDB_INTR_D2A 0x68 /* US-III family */
200 #define AA_INTR_SEND 0x70
201 #define AA_SDB_INTR_D6 0x80 /* US-III family */
202 #define AA_SDB_INTR_D7 0x88 /* US-III family */
204 #define ASI_BLK_AIUPL 0x78
205 #define ASI_BLK_AIUSL 0x79
207 #define ASI_ECACHE_R 0x7e
210 * These have the same registers as their corresponding write versions
211 * except for AA_INTR_SEND.
213 #define ASI_SDB_ERROR_R 0x7f
214 #define ASI_SDB_CONTROL_R 0x7f
215 #define ASI_SDB_INTR_R 0x7f
217 #define ASI_PST8_P 0xc0
218 #define ASI_PST8_S 0xc1
219 #define ASI_PST16_P 0xc2
220 #define ASI_PST16_S 0xc3
221 #define ASI_PST32_P 0xc4
222 #define ASI_PST32_S 0xc5
224 #define ASI_PST8_PL 0xc8
225 #define ASI_PST8_SL 0xc9
226 #define ASI_PST16_PL 0xca
227 #define ASI_PST16_SL 0xcb
228 #define ASI_PST32_PL 0xcc
229 #define ASI_PST32_SL 0xcd
231 #define ASI_FL8_P 0xd0
232 #define ASI_FL8_S 0xd1
233 #define ASI_FL16_P 0xd2
234 #define ASI_FL16_S 0xd3
235 #define ASI_FL8_PL 0xd8
236 #define ASI_FL8_SL 0xd9
237 #define ASI_FL16_PL 0xda
238 #define ASI_FL16_SL 0xdb
240 #define ASI_BLK_COMMIT_P 0xe0
241 #define ASI_BLK_COMMIT_S 0xe1
242 #define ASI_BLK_P 0xf0
243 #define ASI_BLK_S 0xf1
244 #define ASI_BLK_PL 0xf8
245 #define ASI_BLK_SL 0xf9
247 #endif /* !_MACHINE_ASI_H_ */