sys/sparc64/include/tlb.h

   1 /*-
   2  * Copyright (c) 2001 Jake Burkholder.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #ifndef _MACHINE_TLB_H_
  30 #define _MACHINE_TLB_H_
  31
  32 #define TLB_DIRECT_ADDRESS_BITS         (43)
  33 #define TLB_DIRECT_PAGE_BITS            (PAGE_SHIFT_4M)
  34
  35 #define TLB_DIRECT_ADDRESS_MASK         ((1UL << TLB_DIRECT_ADDRESS_BITS) - 1)
  36 #define TLB_DIRECT_PAGE_MASK            ((1UL << TLB_DIRECT_PAGE_BITS) - 1)
  37
  38 #define TLB_PHYS_TO_DIRECT(pa) \
  39         ((pa) | VM_MIN_DIRECT_ADDRESS)
  40 #define TLB_DIRECT_TO_PHYS(va) \
  41         ((va) & TLB_DIRECT_ADDRESS_MASK)
  42 #define TLB_DIRECT_TO_TTE_MASK \
  43         (TD_V | TD_4M | (TLB_DIRECT_ADDRESS_MASK - TLB_DIRECT_PAGE_MASK))
  44
  45 #define TLB_DAR_SLOT_SHIFT              (3)
  46 #define TLB_DAR_SLOT(slot)              ((slot) << TLB_DAR_SLOT_SHIFT)
  47
  48 #define TAR_VPN_SHIFT                   (13)
  49 #define TAR_CTX_MASK                    ((1 << TAR_VPN_SHIFT) - 1)
  50
  51 #define TLB_TAR_VA(va)                  ((va) & ~TAR_CTX_MASK)
  52 #define TLB_TAR_CTX(ctx)                ((ctx) & TAR_CTX_MASK)
  53
  54 #define TLB_CXR_CTX_BITS                (13)
  55 #define TLB_CXR_CTX_MASK                                                \
  56         (((1UL << TLB_CXR_CTX_BITS) - 1) << TLB_CXR_CTX_SHIFT)
  57 #define TLB_CXR_CTX_SHIFT               (0)
  58 #define TLB_CXR_PGSZ_BITS               (3)
  59 #define TLB_PCXR_PGSZ_MASK                                              \
  60         ((((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_N_PGSZ0_SHIFT) | \
  61         (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_N_PGSZ1_SHIFT) |  \
  62         (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_P_PGSZ0_SHIFT) |  \
  63         (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_P_PGSZ1_SHIFT))
  64 #define TLB_PCXR_N_PGSZ0_SHIFT          (61)
  65 #define TLB_PCXR_N_PGSZ1_SHIFT          (58)
  66 #define TLB_PCXR_P_PGSZ0_SHIFT          (16)
  67 #define TLB_PCXR_P_PGSZ1_SHIFT          (19)
  68 #define TLB_SCXR_PGSZ_MASK                                              \
  69         ((((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_SCXR_S_PGSZ0_SHIFT) | \
  70         (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_SCXR_S_PGSZ1_SHIFT))
  71 #define TLB_SCXR_S_PGSZ1_SHIFT          (19)
  72 #define TLB_SCXR_S_PGSZ0_SHIFT          (16)
  73
  74 #define TLB_TAE_PGSZ_BITS               (3)
  75 #define TLB_TAE_PGSZ0_MASK                                              \
  76         (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ0_SHIFT)
  77 #define TLB_TAE_PGSZ1_MASK                                              \
  78         (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ1_SHIFT)
  79 #define TLB_TAE_PGSZ0_SHIFT             (16)
  80 #define TLB_TAE_PGSZ1_SHIFT             (19)
  81
  82 #define TLB_DEMAP_ID_SHIFT              (4)
  83 #define TLB_DEMAP_ID_PRIMARY            (0)
  84 #define TLB_DEMAP_ID_SECONDARY          (1)
  85 #define TLB_DEMAP_ID_NUCLEUS            (2)
  86
  87 #define TLB_DEMAP_TYPE_SHIFT            (6)
  88 #define TLB_DEMAP_TYPE_PAGE             (0)
  89 #define TLB_DEMAP_TYPE_CONTEXT          (1)
  90 #define TLB_DEMAP_TYPE_ALL              (2)     /* USIII and beyond only */
  91
  92 #define TLB_DEMAP_VA(va)                ((va) & ~PAGE_MASK)
  93 #define TLB_DEMAP_ID(id)                ((id) << TLB_DEMAP_ID_SHIFT)
  94 #define TLB_DEMAP_TYPE(type)            ((type) << TLB_DEMAP_TYPE_SHIFT)
  95
  96 #define TLB_DEMAP_PAGE                  (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE))
  97 #define TLB_DEMAP_CONTEXT               (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT))
  98 #define TLB_DEMAP_ALL                   (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_ALL))
  99
 100 #define TLB_DEMAP_PRIMARY               (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY))
 101 #define TLB_DEMAP_SECONDARY             (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY))
 102 #define TLB_DEMAP_NUCLEUS               (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS))
 103
 104 #define TLB_CTX_KERNEL                  (0)
 105 #define TLB_CTX_USER_MIN                (1)
 106 #define TLB_CTX_USER_MAX                (8192)
 107
 108 #define MMU_SFSR_ASI_SHIFT              (16)
 109 #define MMU_SFSR_FT_SHIFT               (7)
 110 #define MMU_SFSR_E_SHIFT                (6)
 111 #define MMU_SFSR_CT_SHIFT               (4)
 112 #define MMU_SFSR_PR_SHIFT               (3)
 113 #define MMU_SFSR_W_SHIFT                (2)
 114 #define MMU_SFSR_OW_SHIFT               (1)
 115 #define MMU_SFSR_FV_SHIFT               (0)
 116
 117 #define MMU_SFSR_ASI_SIZE               (8)
 118 #define MMU_SFSR_FT_SIZE                (6)
 119 #define MMU_SFSR_CT_SIZE                (2)
 120
 121 #define MMU_SFSR_GET_ASI(sfsr) \
 122         (((sfsr) >> MMU_SFSR_ASI_SHIFT) & ((1UL << MMU_SFSR_ASI_SIZE) - 1))
 123 #define MMU_SFSR_W                      (1UL << MMU_SFSR_W_SHIFT)
 124 #define MMU_SFSR_FV                     (1UL << MMU_SFSR_FV_SHIFT)
 125
 126 typedef void tlb_flush_nonlocked_t(void);
 127 typedef void tlb_flush_user_t(void);
 128
 129 struct pmap;
 130 struct tlb_entry;
 131
 132 extern int dtlb_slots;
 133 extern int itlb_slots;
 134 extern int kernel_tlb_slots;
 135 extern struct tlb_entry *kernel_tlbs;
 136
 137 void    tlb_context_demap(struct pmap *pm);
 138 void    tlb_page_demap(struct pmap *pm, vm_offset_t va);
 139 void    tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end);
 140
 141 tlb_flush_nonlocked_t cheetah_tlb_flush_nonlocked;
 142 tlb_flush_user_t cheetah_tlb_flush_user;
 143
 144 tlb_flush_nonlocked_t spitfire_tlb_flush_nonlocked;
 145 tlb_flush_user_t spitfire_tlb_flush_user;
 146
 147 extern tlb_flush_nonlocked_t *tlb_flush_nonlocked;
 148 extern tlb_flush_user_t *tlb_flush_user;
 149
 150 #endif /* !_MACHINE_TLB_H_ */