2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
41 #include "opt_ofw_pci.h"
42 #include "opt_psycho.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/endian.h>
49 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
55 #include <sys/reboot.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_pci.h>
60 #include <dev/ofw/openfirm.h>
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/iommureg.h>
66 #include <machine/iommuvar.h>
67 #include <machine/ofw_bus.h>
68 #include <machine/resource.h>
69 #include <machine/ver.h>
71 #include <dev/pci/pcireg.h>
72 #include <dev/pci/pcivar.h>
74 #include <sparc64/pci/ofw_pci.h>
75 #include <sparc64/pci/psychoreg.h>
76 #include <sparc64/pci/psychovar.h>
80 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
82 static const struct psycho_desc *psycho_get_desc(device_t);
83 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
84 driver_filter_t, driver_intr_t);
85 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
86 bus_addr_t *, u_long *);
87 static driver_filter_t psycho_dma_sync_stub;
88 static void psycho_intr_enable(void *);
89 static void psycho_intr_disable(void *);
90 static void psycho_intr_assign(void *);
91 static void psycho_intr_clear(void *);
92 static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int);
94 /* Interrupt handlers */
95 static driver_filter_t psycho_ue;
96 static driver_filter_t psycho_ce;
97 static driver_filter_t psycho_pci_bus;
98 static driver_filter_t psycho_powerfail;
99 static driver_intr_t psycho_overtemp;
100 #ifdef PSYCHO_MAP_WAKEUP
101 static driver_filter_t psycho_wakeup;
105 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
110 static device_probe_t psycho_probe;
111 static device_attach_t psycho_attach;
112 static bus_read_ivar_t psycho_read_ivar;
113 static bus_setup_intr_t psycho_setup_intr;
114 static bus_teardown_intr_t psycho_teardown_intr;
115 static bus_alloc_resource_t psycho_alloc_resource;
116 static bus_activate_resource_t psycho_activate_resource;
117 static bus_deactivate_resource_t psycho_deactivate_resource;
118 static bus_release_resource_t psycho_release_resource;
119 static bus_get_dma_tag_t psycho_get_dma_tag;
120 static pcib_maxslots_t psycho_maxslots;
121 static pcib_read_config_t psycho_read_config;
122 static pcib_write_config_t psycho_write_config;
123 static pcib_route_interrupt_t psycho_route_interrupt;
124 static ofw_bus_get_node_t psycho_get_node;
126 static device_method_t psycho_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, psycho_probe),
129 DEVMETHOD(device_attach, psycho_attach),
130 DEVMETHOD(device_shutdown, bus_generic_shutdown),
131 DEVMETHOD(device_suspend, bus_generic_suspend),
132 DEVMETHOD(device_resume, bus_generic_resume),
135 DEVMETHOD(bus_print_child, bus_generic_print_child),
136 DEVMETHOD(bus_read_ivar, psycho_read_ivar),
137 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
138 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr),
139 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
140 DEVMETHOD(bus_activate_resource, psycho_activate_resource),
141 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource),
142 DEVMETHOD(bus_release_resource, psycho_release_resource),
143 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
146 DEVMETHOD(pcib_maxslots, psycho_maxslots),
147 DEVMETHOD(pcib_read_config, psycho_read_config),
148 DEVMETHOD(pcib_write_config, psycho_write_config),
149 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
151 /* ofw_bus interface */
152 DEVMETHOD(ofw_bus_get_node, psycho_get_node),
157 static devclass_t psycho_devclass;
159 DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
160 sizeof(struct psycho_softc));
161 DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0);
163 static SLIST_HEAD(, psycho_softc) psycho_softcs =
164 SLIST_HEAD_INITIALIZER(psycho_softcs);
166 static const struct intr_controller psycho_ic = {
173 struct psycho_icarg {
174 struct psycho_softc *pica_sc;
179 struct psycho_dma_sync {
180 struct psycho_softc *pds_sc;
181 driver_filter_t *pds_handler; /* handler to call */
182 void *pds_arg; /* argument for the handler */
183 void *pds_cookie; /* parent bus int. cookie */
184 device_t pds_ppb; /* farest PCI-PCI bridge */
185 uint8_t pds_bus; /* bus of farest PCI device */
186 uint8_t pds_slot; /* slot of farest PCI device */
187 uint8_t pds_func; /* func. of farest PCI device */
190 #define PSYCHO_READ8(sc, off) \
191 bus_read_8((sc)->sc_mem_res, (off))
192 #define PSYCHO_WRITE8(sc, off, v) \
193 bus_write_8((sc)->sc_mem_res, (off), (v))
194 #define PCICTL_READ8(sc, off) \
195 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
196 #define PCICTL_WRITE8(sc, off, v) \
197 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
200 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
201 * single PCI bus and does not have a streaming buffer. It often has an APB
202 * (advanced PCI bridge) connected to it, which was designed specifically for
203 * the IIi. The APB let's the IIi handle two independednt PCI buses, and
204 * appears as two "Simba"'s underneath the Sabre.
206 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
207 * basically the same as Sabre but without an APB underneath it.
209 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus
210 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
211 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
212 * will usually find a "Psycho+" since I don't think the original "Psycho"
213 * ever shipped, and if it did it would be in the U30.
215 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
216 * both part of the same IC, they only have a single register space. As such,
217 * they need to be configured together, even though the autoconfiguration will
218 * attach them separately.
220 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
221 * as pci1 and pci2, although they have been implemented with other PCI bus
222 * numbers on some machines.
224 * On UltraII machines, there can be any number of "Psycho+" ICs, each
225 * providing two PCI buses.
228 #define OFW_PCI_TYPE "pci"
231 const char *pd_string;
236 static const struct psycho_desc const psycho_compats[] = {
237 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
238 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
239 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
243 static const struct psycho_desc const psycho_models[] = {
244 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
245 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
249 static const struct psycho_desc *
250 psycho_find_desc(const struct psycho_desc *table, const char *string)
252 const struct psycho_desc *desc;
256 for (desc = table; desc->pd_string != NULL; desc++)
257 if (strcmp(desc->pd_string, string) == 0)
262 static const struct psycho_desc *
263 psycho_get_desc(device_t dev)
265 const struct psycho_desc *rv;
267 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
269 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev));
274 psycho_probe(device_t dev)
278 dtype = ofw_bus_get_type(dev);
279 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 &&
280 psycho_get_desc(dev) != NULL) {
281 device_set_desc(dev, "U2P UPA-PCI bridge");
288 psycho_attach(device_t dev)
290 char name[sizeof("pci108e,1000")];
291 struct psycho_icarg *pica;
292 struct psycho_softc *asc, *sc, *osc;
293 struct ofw_pci_ranges *range;
294 const struct psycho_desc *desc;
295 bus_addr_t intrclr, intrmap;
297 phandle_t child, node;
298 uint32_t dvmabase, prop, prop_array[2];
303 node = ofw_bus_get_node(dev);
304 sc = device_get_softc(dev);
305 desc = psycho_get_desc(dev);
309 sc->sc_mode = desc->pd_mode;
312 * The Psycho gets three register banks:
313 * (0) per-PBM configuration and status registers
314 * (1) per-PBM PCI configuration space, containing only the
315 * PBM 256-byte PCI header
316 * (2) the shared Psycho configuration registers
318 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
321 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
322 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
323 switch (sc->sc_pcictl) {
331 panic("%s: bogus PCI control register location",
337 sc->sc_pcictl = PSR_PCICTL0;
340 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
341 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
343 if (sc->sc_mem_res == NULL)
344 panic("%s: could not allocate registers", __func__);
347 * Match other Psychos that are already configured against
348 * the base physical address. This will be the same for a
349 * pair of devices that share register space.
352 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
353 if (rman_get_start(asc->sc_mem_res) ==
354 rman_get_start(sc->sc_mem_res)) {
361 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
363 if (sc->sc_mtx == NULL)
364 panic("%s: could not malloc mutex", __func__);
365 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
367 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
368 panic("%s: no partner expected", __func__);
369 if (mtx_initialized(osc->sc_mtx) == 0)
370 panic("%s: mutex not initialized", __func__);
371 sc->sc_mtx = osc->sc_mtx;
374 csr = PSYCHO_READ8(sc, PSR_CS);
375 ver = PSYCHO_GCSR_VERS(csr);
376 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
377 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
378 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
379 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
383 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
384 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
385 'A' + sc->sc_half, prop / 1000 / 1000);
387 /* Set up the PCI control and PCI diagnostic registers. */
390 * Revision 0 EBus bridges have a bug which prevents them from
391 * working when bus parking is enabled.
394 csr = PCICTL_READ8(sc, PCR_CS);
395 csr &= ~PCICTL_ARB_PARK;
396 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
397 if (OF_getprop(child, "name", name, sizeof(name)) == -1)
399 if ((strcmp(name, "ebus") == 0 ||
400 strcmp(name, "pci108e,1000") == 0) &&
401 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 &&
405 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0)
406 csr |= PCICTL_ARB_PARK;
408 /* Workarounds for version specific bugs. */
409 dr = PCICTL_READ8(sc, PCR_DIAG);
413 dr &= ~DIAG_DWSYNC_DIS;
417 csr &= ~PCICTL_ARB_PARK;
418 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
422 dr |= DIAG_DWSYNC_DIS;
423 dr &= ~DIAG_RTRY_DIS;
428 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
429 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
431 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
432 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
433 (unsigned long long)csr);
435 PCICTL_WRITE8(sc, PCR_CS, csr);
437 dr &= ~DIAG_ISYNC_DIS;
439 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
440 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
441 (unsigned long long)dr);
443 PCICTL_WRITE8(sc, PCR_DIAG, dr);
445 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
446 /* Use the PROM preset for now. */
447 csr = PCICTL_READ8(sc, PCR_TAS);
449 panic("%s: Hummingbird/Sabre TAS not initialized.",
451 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
455 /* Initialize memory and I/O rmans. */
456 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
457 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
458 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
459 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
460 panic("%s: failed to set up I/O rman", __func__);
461 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
462 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
463 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
464 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
465 panic("%s: failed to set up memory rman", __func__);
467 n = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
469 * Make sure that the expected ranges are present. The
470 * OFW_PCI_CS_MEM64 one is not currently used though.
472 if (n != PSYCHO_NRANGE)
473 panic("%s: unsupported number of ranges", __func__);
475 * Find the addresses of the various bus spaces.
476 * There should not be multiple ones of one kind.
477 * The physical start addresses of the ranges are the configuration,
478 * memory and I/O handles.
480 for (n = 0; n < PSYCHO_NRANGE; n++) {
481 i = OFW_PCI_RANGE_CS(&range[n]);
482 if (sc->sc_pci_bh[i] != 0)
483 panic("%s: duplicate range for space %d", __func__, i);
484 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]);
486 free(range, M_OFWPROP);
488 /* Register the softc, this is needed for paired Psychos. */
489 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
492 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
493 * to arrive here, do the interrupt setup and start up the IOMMU.
497 * Hunt through all the interrupt mapping regs and register
498 * our interrupt controller for the corresponding interrupt
499 * vectors. We do this early in order to be able to catch
502 for (n = 0; n <= PSYCHO_MAX_INO; n++) {
503 if (psycho_find_intrmap(sc, n, &intrmap, &intrclr,
506 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
508 panic("%s: could not allocate interrupt "
509 "controller argument", __func__);
511 pica->pica_map = intrmap;
512 pica->pica_clr = intrclr;
515 * Enable all interrupts and clear all interrupt
516 * states. This aids the debugging of interrupt
520 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
521 n, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
522 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, intrmap),
524 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, n));
525 PSYCHO_WRITE8(sc, intrclr, 0);
526 PSYCHO_WRITE8(sc, intrmap,
527 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, n),
530 i = intr_controller_register(INTMAP_VEC(sc->sc_ign, n),
533 device_printf(dev, "could not register "
534 "interrupt controller for INO %d (%d)\n",
538 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
539 sparc64_counter_init(device_get_nameunit(dev),
540 rman_get_bustag(sc->sc_mem_res),
541 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
544 * Set up IOMMU and PCI configuration if we're the first
545 * of a pair of Psychos to arrive here or a Hummingbird
548 * We should calculate a TSB size based on amount of RAM
549 * and number of bus controllers and number and type of
552 * For the moment, 32KB should be more than enough.
554 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF,
556 if (sc->sc_is == NULL)
557 panic("%s: malloc iommu_state failed", __func__);
558 if (sc->sc_mode == PSYCHO_MODE_SABRE)
559 sc->sc_is->is_pmaxaddr =
560 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
562 sc->sc_is->is_pmaxaddr =
563 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
564 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0;
565 if (OF_getproplen(node, "no-streaming-cache") < 0)
566 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
567 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0;
568 psycho_iommu_init(sc, 3, dvmabase);
570 /* Just copy IOMMU state, config tag and address. */
571 sc->sc_is = osc->sc_is;
572 if (OF_getproplen(node, "no-streaming-cache") < 0)
573 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
574 iommu_reset(sc->sc_is);
577 /* Allocate our tags. */
578 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
579 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
580 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
581 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
582 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
583 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
584 panic("%s: bus_dma_tag_create failed", __func__);
585 /* Customize the tag. */
586 sc->sc_pci_dmat->dt_cookie = sc->sc_is;
587 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods;
589 n = OF_getprop(node, "bus-range", (void *)prop_array,
592 panic("%s: could not get bus-range", __func__);
593 if (n != sizeof(prop_array))
594 panic("%s: broken bus-range (%d)", __func__, n);
596 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
597 prop_array[0], prop_array[1], prop_array[0]);
598 sc->sc_pci_secbus = prop_array[0];
600 /* Clear any pending PCI error bits. */
601 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
602 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
603 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
604 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
605 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
609 * Establish handlers for interesting interrupts...
611 * XXX We need to remember these and remove this to support
612 * hotplug on the UPA/FHC bus.
614 * XXX Not all controllers have these, but installing them
615 * is better than trying to sort through this mess.
617 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
618 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
619 #ifdef DEBUGGER_ON_POWERFAIL
620 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail,
623 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
624 (driver_intr_t *)psycho_powerfail);
626 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
628 * Hummingbirds/Sabres do not have the following two
633 * The spare hardware interrupt is used for the
634 * over-temperature interrupt.
636 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP,
637 NULL, psycho_overtemp);
638 #ifdef PSYCHO_MAP_WAKEUP
640 * psycho_wakeup() doesn't do anything useful right
643 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
644 psycho_wakeup, NULL);
645 #endif /* PSYCHO_MAP_WAKEUP */
649 * Register a PCI bus error interrupt handler according to which
650 * half this is. Hummingbird/Sabre don't have a PCI bus B error
651 * interrupt but they are also only used for PCI bus A.
653 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
654 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
657 * Set the latency timer register as this isn't always done by the
660 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
661 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
663 for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t))
664 le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2(
665 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
666 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
668 for (n = PCIR_REVID; n <= PCIR_BIST; n += sizeof(uint8_t))
669 sc->sc_pci_hpbcfg[n] = bus_space_read_1(sc->sc_pci_cfgt,
670 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
671 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, n));
673 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
675 * On E250 the interrupt map entry for the EBus bridge is wrong,
676 * causing incorrect interrupts to be assigned to some devices on
677 * the EBus. Work around it by changing our copy of the interrupt
678 * map mask to perform a full comparison of the INO. That way
679 * the interrupt map entry for the EBus bridge won't match at all
680 * and the INOs specified in the "interrupts" properties of the
681 * EBus devices will be used directly instead.
683 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
684 sc->sc_pci_iinfo.opi_imapmsk != NULL)
685 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
686 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
688 device_add_child(dev, "pci", -1);
689 return (bus_generic_attach(dev));
693 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
694 driver_filter_t filt, driver_intr_t intr)
700 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ,
702 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) {
704 * These interrupts aren't mandatory and not available
705 * with all controllers (not even Psychos).
709 if (sc->sc_irq_res[index] == NULL ||
710 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign ||
711 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
712 intr_vectors[vec].iv_ic != &psycho_ic ||
713 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
714 INTR_TYPE_MISC | INTR_FAST, filt, intr, sc,
715 &sc->sc_ihand[index]) != 0)
716 panic("%s: failed to set up interrupt %d", __func__, index);
720 psycho_find_intrmap(struct psycho_softc *sc, u_int ino, bus_addr_t *intrmapptr,
721 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
723 bus_addr_t intrclr, intrmap;
728 * XXX we only compare INOs rather than INRs since the firmware may
729 * not provide the IGN and the IGN is constant for all devices on
730 * that PCI controller.
731 * This could cause problems for the FFB/external interrupt which
732 * has a full vector that can be set arbitrarily.
735 if (ino > PSYCHO_MAX_INO) {
736 device_printf(sc->sc_dev, "out of range INO %d requested\n",
742 /* Hunt through OBIO first. */
743 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
744 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
745 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
747 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
748 (intrmap == PSR_TIMER0_INT_MAP ||
749 intrmap == PSR_TIMER1_INT_MAP ||
750 intrmap == PSR_PCIBERR_INT_MAP ||
751 intrmap == PSR_PWRMGT_INT_MAP))
753 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
761 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
762 /* Now do PCI interrupts. */
763 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
764 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
766 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
767 (intrmap == PSR_PCIA2_INT_MAP ||
768 intrmap == PSR_PCIA3_INT_MAP))
770 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
771 intrclr += 8 * (ino & 3);
772 diag = (diag >> ((ino & 3) * 2)) & 2;
778 if (intrmapptr != NULL)
779 *intrmapptr = intrmap;
780 if (intrclrptr != NULL)
781 *intrclrptr = intrclr;
782 if (intrdiagptr != NULL)
793 struct psycho_softc *sc = arg;
796 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
797 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
799 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
800 * the AFAR to be set to the physical address of the TTE entry that
801 * was invalid/write protected. Call into the IOMMU code to have
802 * them decoded to virtual I/O addresses.
804 if ((afsr & UEAFSR_P_DTE) != 0)
805 iommu_decode_fault(sc->sc_is, afar);
806 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
807 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr);
808 return (FILTER_HANDLED);
814 struct psycho_softc *sc = arg;
817 mtx_lock_spin(sc->sc_mtx);
818 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
819 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
820 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
821 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
822 /* Clear the error bits that we caught. */
823 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
824 mtx_unlock_spin(sc->sc_mtx);
825 return (FILTER_HANDLED);
829 psycho_pci_bus(void *arg)
831 struct psycho_softc *sc = arg;
834 afar = PCICTL_READ8(sc, PCR_AFA);
835 afsr = PCICTL_READ8(sc, PCR_AFS);
836 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
837 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
839 return (FILTER_HANDLED);
843 psycho_powerfail(void *arg)
845 #ifdef DEBUGGER_ON_POWERFAIL
846 struct psycho_softc *sc = arg;
848 kdb_enter_why(KDB_WHY_POWERFAIL, "powerfail");
852 /* As the interrupt is cleared we may be called multiple times. */
854 return (FILTER_HANDLED);
856 printf("Power Failure Detected: Shutting down NOW.\n");
859 return (FILTER_HANDLED);
863 psycho_overtemp(void *arg)
867 /* As the interrupt is cleared we may be called multiple times. */
871 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
872 shutdown_nice(RB_POWEROFF);
875 #ifdef PSYCHO_MAP_WAKEUP
877 psycho_wakeup(void *arg)
879 struct psycho_softc *sc = arg;
881 /* Gee, we don't really have a framework to deal with this properly. */
882 device_printf(sc->sc_dev, "power management wakeup\n");
883 return (FILTER_HANDLED);
885 #endif /* PSYCHO_MAP_WAKEUP */
888 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
890 struct iommu_state *is = sc->sc_is;
892 /* Punch in our copies. */
893 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
894 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
895 is->is_iommu = PSR_IOMMU;
896 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
897 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
898 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
899 is->is_dva = PSR_IOMMU_SVADIAG;
900 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
902 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
906 psycho_maxslots(device_t dev)
909 /* XXX: is this correct? */
910 return (PCI_SLOTMAX);
914 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
917 struct psycho_softc *sc;
918 bus_space_handle_t bh;
925 sc = device_get_softc(dev);
926 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
929 * The Hummingbird and Sabre bridges are picky in that they
930 * only allow their config space to be accessed using the
931 * "native" width of the respective register being accessed
932 * and return semi-random other content of their config space
933 * otherwise. Given that the PCI specs don't say anything
934 * about such a (unusual) limitation and lots of stuff expects
935 * to be able to access the contents of the config space at
936 * any width we allow just that. We do this by using a copy
937 * of the header of the bridge (the rest is all zero anyway)
938 * read during attach (expect for PCIR_STATUS) in order to
940 * The Psycho bridges contain a dupe of their header at 0x80
941 * which we nullify that way also.
943 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE &&
945 if (offset % width != 0)
948 if (reg >= sizeof(sc->sc_pci_hpbcfg))
951 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
952 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
953 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
954 bus_space_read_2(sc->sc_pci_cfgt, bh,
955 PSYCHO_CONF_OFF(sc->sc_pci_secbus,
956 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
960 return (sc->sc_pci_hpbcfg[reg]);
962 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
964 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
968 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
971 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
975 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
979 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
983 panic("%s: bad width", __func__);
989 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
990 __func__, bus, slot, func, reg);
998 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
999 uint32_t val, int width)
1001 struct psycho_softc *sc;
1002 bus_space_handle_t bh;
1005 sc = device_get_softc(dev);
1006 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
1007 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1010 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1013 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1016 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1019 panic("%s: bad width", __func__);
1025 psycho_route_interrupt(device_t bridge, device_t dev, int pin)
1027 struct psycho_softc *sc;
1028 struct ofw_pci_register reg;
1030 ofw_pci_intr_t pintr, mintr;
1031 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
1033 sc = device_get_softc(bridge);
1035 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®,
1036 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf))
1039 * If this is outside of the range for an intpin, it's likely a full
1040 * INO, and no mapping is required at all; this happens on the U30,
1041 * where there's no interrupt map at the Psycho node. Fortunately,
1042 * there seem to be no INOs in the intpin range on this boxen, so
1043 * this easy heuristics will do.
1048 * Guess the INO; we always assume that this is a non-OBIO
1049 * device, and that pin is a "real" intpin number. Determine
1050 * the mapping register to be used by the slot number.
1051 * We only need to do this on E450s, it seems; here, the slot numbers
1052 * for bus A are one-based, while those for bus B seemingly have an
1053 * offset of 2 (hence the factor of 3 below).
1055 intrmap = PSR_PCIA0_INT_MAP +
1056 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
1057 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
1058 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n",
1059 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
1064 psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1066 struct psycho_softc *sc;
1068 sc = device_get_softc(dev);
1070 case PCIB_IVAR_DOMAIN:
1071 *result = device_get_unit(dev);
1074 *result = sc->sc_pci_secbus;
1081 psycho_dma_sync_stub(void *arg)
1083 struct psycho_dma_sync *pds = arg;
1085 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot,
1086 pds->pds_func, PCIR_VENDOR, 2);
1087 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC);
1088 return (pds->pds_handler(pds->pds_arg));
1092 psycho_intr_enable(void *arg)
1094 struct intr_vector *iv = arg;
1095 struct psycho_icarg *pica = iv->iv_icarg;
1097 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
1098 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1102 psycho_intr_disable(void *arg)
1104 struct intr_vector *iv = arg;
1105 struct psycho_icarg *pica = iv->iv_icarg;
1107 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
1111 psycho_intr_assign(void *arg)
1113 struct intr_vector *iv = arg;
1114 struct psycho_icarg *pica = iv->iv_icarg;
1116 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
1117 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
1121 psycho_intr_clear(void *arg)
1123 struct intr_vector *iv = arg;
1124 struct psycho_icarg *pica = iv->iv_icarg;
1126 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, 0);
1130 psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1131 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1138 devclass_t pci_devclass;
1139 device_t cdev, pdev, pcidev;
1140 struct psycho_softc *sc;
1141 struct psycho_dma_sync *pds;
1145 sc = device_get_softc(dev);
1147 * Make sure the vector is fully specified and we registered
1148 * our interrupt controller for it.
1150 vec = rman_get_start(ires);
1151 if (INTIGN(vec) != sc->sc_ign ||
1152 intr_vectors[vec].iv_ic != &psycho_ic) {
1153 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1158 * The Sabre-APB-combination does not automatically flush DMA
1159 * write data for devices behind additional PCI-PCI bridges
1160 * underneath the APB PCI-PCI bridge. The procedure for a
1161 * manual flush is to do a PIO read on the far side of the
1162 * farthest PCI-PCI bridge followed by a read of the PCI DMA
1163 * write sync register of the Sabre.
1165 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
1166 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO);
1170 found.apb = found.ppb = 0;
1171 pci_devclass = devclass_find("pci");
1172 for (cdev = child; cdev != dev; cdev = pdev) {
1173 pdev = device_get_parent(cdev);
1174 if (pcidev == NULL) {
1175 if (device_get_devclass(pdev) != pci_devclass)
1181 * NB: APB would also match as PCI-PCI bridges.
1183 if (pci_get_vendor(cdev) == 0x108e &&
1184 pci_get_device(cdev) == 0x5000) {
1188 if (pci_get_class(cdev) == PCIC_BRIDGE &&
1189 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI)
1192 if (found.apb && found.ppb && pcidev != NULL) {
1196 device_get_parent(device_get_parent(pcidev));
1197 pds->pds_bus = pci_get_bus(pcidev);
1198 pds->pds_slot = pci_get_slot(pcidev);
1199 pds->pds_func = pci_get_function(pcidev);
1201 device_printf(dev, "installed DMA sync "
1202 "wrapper for device %d.%d on bus %d\n",
1203 pds->pds_slot, pds->pds_func,
1206 pds->pds_handler = filt;
1207 error = bus_generic_setup_intr(dev, child,
1208 ires, flags, psycho_dma_sync_stub, intr,
1211 pds->pds_handler = (driver_filter_t *)intr;
1212 error = bus_generic_setup_intr(dev, child,
1214 (driver_intr_t *)psycho_dma_sync_stub,
1218 error = bus_generic_setup_intr(dev, child, ires,
1219 flags, filt, intr, arg, cookiep);
1221 free(pds, M_DEVBUF);
1224 pds->pds_cookie = *cookiep;
1228 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1233 psycho_teardown_intr(device_t dev, device_t child, struct resource *vec,
1236 struct psycho_softc *sc;
1237 struct psycho_dma_sync *pds;
1240 sc = device_get_softc(dev);
1241 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
1243 error = bus_generic_teardown_intr(dev, child, vec,
1246 free(pds, M_DEVBUF);
1249 return (bus_generic_teardown_intr(dev, child, vec, cookie));
1252 static struct resource *
1253 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1254 u_long start, u_long end, u_long count, u_int flags)
1256 struct psycho_softc *sc;
1257 struct resource *rv;
1260 bus_space_handle_t bh;
1261 int needactivate = flags & RF_ACTIVE;
1263 flags &= ~RF_ACTIVE;
1265 sc = device_get_softc(bus);
1266 if (type == SYS_RES_IRQ) {
1268 * XXX: Don't accept blank ranges for now, only single
1269 * interrupts. The other case should not happen with
1270 * the MI PCI code...
1271 * XXX: This may return a resource that is out of the
1272 * range that was specified. Is this correct...?
1275 panic("%s: XXX: interrupt range", __func__);
1276 start = end = INTMAP_VEC(sc->sc_ign, end);
1277 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
1278 rid, start, end, count, flags));
1281 case SYS_RES_MEMORY:
1282 rm = &sc->sc_pci_mem_rman;
1283 bt = sc->sc_pci_memt;
1284 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
1286 case SYS_RES_IOPORT:
1287 rm = &sc->sc_pci_io_rman;
1288 bt = sc->sc_pci_iot;
1289 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1296 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1299 rman_set_rid(rv, *rid);
1300 bh += rman_get_start(rv);
1301 rman_set_bustag(rv, bt);
1302 rman_set_bushandle(rv, bh);
1305 if (bus_activate_resource(child, type, *rid, rv)) {
1306 rman_release_resource(rv);
1314 psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1320 if (type == SYS_RES_IRQ)
1321 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
1323 if (type == SYS_RES_MEMORY) {
1325 * Need to memory-map the device space, as some drivers
1326 * depend on the virtual address being set and usable.
1328 error = sparc64_bus_mem_map(rman_get_bustag(r),
1329 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
1332 rman_set_virtual(r, p);
1334 return (rman_activate_resource(r));
1338 psycho_deactivate_resource(device_t bus, device_t child, int type, int rid,
1342 if (type == SYS_RES_IRQ)
1343 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
1345 if (type == SYS_RES_MEMORY) {
1346 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
1347 rman_set_virtual(r, NULL);
1349 return (rman_deactivate_resource(r));
1353 psycho_release_resource(device_t bus, device_t child, int type, int rid,
1358 if (type == SYS_RES_IRQ)
1359 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
1361 if (rman_get_flags(r) & RF_ACTIVE) {
1362 error = bus_deactivate_resource(child, type, rid, r);
1366 return (rman_release_resource(r));
1369 static bus_dma_tag_t
1370 psycho_get_dma_tag(device_t bus, device_t child)
1372 struct psycho_softc *sc;
1374 sc = device_get_softc(bus);
1375 return (sc->sc_pci_dmat);
1379 psycho_get_node(device_t bus, device_t dev)
1381 struct psycho_softc *sc;
1383 sc = device_get_softc(bus);
1384 /* We only have one child, the PCI bus, which needs our own node. */
1385 return (sc->sc_node);
1388 static bus_space_tag_t
1389 psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
1393 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO);
1395 panic("%s: out of memory", __func__);
1397 bt->bst_cookie = sc;
1398 bt->bst_parent = rman_get_bustag(sc->sc_mem_res);
1399 bt->bst_type = type;