2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to
42 #include "opt_ofw_pci.h"
43 #include "opt_schizo.h"
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
56 #include <sys/timetc.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_pci.h>
60 #include <dev/ofw/openfirm.h>
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/fsr.h>
66 #include <machine/iommureg.h>
67 #include <machine/iommuvar.h>
68 #include <machine/ofw_bus.h>
69 #include <machine/resource.h>
71 #include <dev/pci/pcireg.h>
72 #include <dev/pci/pcivar.h>
74 #include <sparc64/pci/ofw_pci.h>
75 #include <sparc64/pci/schizoreg.h>
76 #include <sparc64/pci/schizovar.h>
80 static const struct schizo_desc *schizo_get_desc(device_t);
81 static void schizo_set_intr(struct schizo_softc *, u_int, u_int,
83 static driver_filter_t schizo_dma_sync_stub;
84 static driver_filter_t ichip_dma_sync_stub;
85 static void schizo_intr_enable(void *);
86 static void schizo_intr_disable(void *);
87 static void schizo_intr_assign(void *);
88 static void schizo_intr_clear(void *);
89 static int schizo_intr_register(struct schizo_softc *sc, u_int ino);
90 static int schizo_get_intrmap(struct schizo_softc *, u_int,
91 bus_addr_t *, bus_addr_t *);
92 static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int);
93 static timecounter_get_t schizo_get_timecount;
95 /* Interrupt handlers */
96 static driver_filter_t schizo_pci_bus;
97 static driver_filter_t schizo_ue;
98 static driver_filter_t schizo_ce;
99 static driver_filter_t schizo_host_bus;
100 static driver_filter_t schizo_cdma;
103 static void schizo_iommu_init(struct schizo_softc *, int, uint32_t);
108 static device_probe_t schizo_probe;
109 static device_attach_t schizo_attach;
110 static bus_read_ivar_t schizo_read_ivar;
111 static bus_setup_intr_t schizo_setup_intr;
112 static bus_teardown_intr_t schizo_teardown_intr;
113 static bus_alloc_resource_t schizo_alloc_resource;
114 static bus_activate_resource_t schizo_activate_resource;
115 static bus_deactivate_resource_t schizo_deactivate_resource;
116 static bus_release_resource_t schizo_release_resource;
117 static bus_get_dma_tag_t schizo_get_dma_tag;
118 static pcib_maxslots_t schizo_maxslots;
119 static pcib_read_config_t schizo_read_config;
120 static pcib_write_config_t schizo_write_config;
121 static pcib_route_interrupt_t schizo_route_interrupt;
122 static ofw_bus_get_node_t schizo_get_node;
124 static device_method_t schizo_methods[] = {
125 /* Device interface */
126 DEVMETHOD(device_probe, schizo_probe),
127 DEVMETHOD(device_attach, schizo_attach),
128 DEVMETHOD(device_shutdown, bus_generic_shutdown),
129 DEVMETHOD(device_suspend, bus_generic_suspend),
130 DEVMETHOD(device_resume, bus_generic_resume),
133 DEVMETHOD(bus_print_child, bus_generic_print_child),
134 DEVMETHOD(bus_read_ivar, schizo_read_ivar),
135 DEVMETHOD(bus_setup_intr, schizo_setup_intr),
136 DEVMETHOD(bus_teardown_intr, schizo_teardown_intr),
137 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource),
138 DEVMETHOD(bus_activate_resource, schizo_activate_resource),
139 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource),
140 DEVMETHOD(bus_release_resource, schizo_release_resource),
141 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag),
144 DEVMETHOD(pcib_maxslots, schizo_maxslots),
145 DEVMETHOD(pcib_read_config, schizo_read_config),
146 DEVMETHOD(pcib_write_config, schizo_write_config),
147 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt),
149 /* ofw_bus interface */
150 DEVMETHOD(ofw_bus_get_node, schizo_get_node),
155 static devclass_t schizo_devclass;
157 DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods,
158 sizeof(struct schizo_softc));
159 DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0);
161 static SLIST_HEAD(, schizo_softc) schizo_softcs =
162 SLIST_HEAD_INITIALIZER(schizo_softcs);
164 static const struct intr_controller schizo_ic = {
171 struct schizo_icarg {
172 struct schizo_softc *sica_sc;
177 struct schizo_dma_sync {
178 struct schizo_softc *sds_sc;
179 driver_filter_t *sds_handler;
182 uint64_t sds_syncval;
183 device_t sds_ppb; /* farest PCI-PCI bridge */
184 uint8_t sds_bus; /* bus of farest PCI device */
185 uint8_t sds_slot; /* slot of farest PCI device */
186 uint8_t sds_func; /* func. of farest PCI device */
189 #define SCHIZO_PERF_CNT_QLTY 100
191 #define SCHIZO_SPC_READ_8(spc, sc, offs) \
192 bus_read_8((sc)->sc_mem_res[(spc)], (offs))
193 #define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \
194 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v))
196 #define SCHIZO_PCI_READ_8(sc, offs) \
197 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs))
198 #define SCHIZO_PCI_WRITE_8(sc, offs, v) \
199 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v))
200 #define SCHIZO_CTRL_READ_8(sc, offs) \
201 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs))
202 #define SCHIZO_CTRL_WRITE_8(sc, offs, v) \
203 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v))
204 #define SCHIZO_PCICFG_READ_8(sc, offs) \
205 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs))
206 #define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \
207 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v))
208 #define SCHIZO_ICON_READ_8(sc, offs) \
209 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs))
210 #define SCHIZO_ICON_WRITE_8(sc, offs, v) \
211 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v))
213 #define OFW_PCI_TYPE "pci"
216 const char *sd_string;
221 static const struct schizo_desc const schizo_compats[] = {
222 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" },
223 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" },
227 static const struct schizo_desc *
228 schizo_get_desc(device_t dev)
230 const struct schizo_desc *desc;
233 compat = ofw_bus_get_compat(dev);
236 for (desc = schizo_compats; desc->sd_string != NULL; desc++)
237 if (strcmp(desc->sd_string, compat) == 0)
243 schizo_probe(device_t dev)
247 dtype = ofw_bus_get_type(dev);
248 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 &&
249 schizo_get_desc(dev) != NULL) {
250 device_set_desc(dev, "Sun Host-PCI bridge");
257 schizo_attach(device_t dev)
259 struct ofw_pci_ranges *range;
260 const struct schizo_desc *desc;
261 struct schizo_softc *asc, *sc, *osc;
262 struct timecounter *tc;
263 uint64_t ino_bitmap, reg;
265 uint32_t prop, prop_array[2];
266 int i, mode, n, nrange, rid, tsbsize;
268 sc = device_get_softc(dev);
269 node = ofw_bus_get_node(dev);
270 desc = schizo_get_desc(dev);
271 mode = desc->sd_mode;
279 * The Schizo has three register banks:
280 * (0) per-PBM PCI configuration and status registers, but for bus B
281 * shared with the UPA64s interrupt mapping register banks
282 * (1) shared Schizo controller configuration and status registers
283 * (2) per-PBM PCI configuration space
285 * The Tomatillo has four register banks:
286 * (0) per-PBM PCI configuration and status registers
287 * (1) per-PBM Tomatillo controller configuration registers, but on
288 * machines having the `jbusppm' device shared with its Estar
289 * register bank for bus A
290 * (2) per-PBM PCI configuration space
291 * (3) per-PBM interrupt concentrator registers
293 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >>
295 for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG);
298 sc->sc_mem_res[n] = bus_alloc_resource_any(dev,
299 SYS_RES_MEMORY, &rid,
300 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 &&
301 n == STX_PCI) || n == STX_CTRL)) ||
302 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 &&
303 n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE);
304 if (sc->sc_mem_res[n] == NULL)
305 panic("%s: could not allocate register bank %d",
310 * Match other Schizos that are already configured against
311 * the controller base physical address. This will be the
312 * same for a pair of devices that share register space.
315 SLIST_FOREACH(asc, &schizo_softcs, sc_link) {
316 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) ==
317 rman_get_start(sc->sc_mem_res[STX_CTRL])) {
324 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
326 if (sc->sc_mtx == NULL)
327 panic("%s: could not malloc mutex", __func__);
328 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
330 if (sc->sc_mode != SCHIZO_MODE_SCZ)
331 panic("%s: no partner expected", __func__);
332 if (mtx_initialized(osc->sc_mtx) == 0)
333 panic("%s: mutex not initialized", __func__);
334 sc->sc_mtx = osc->sc_mtx;
337 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1)
338 panic("%s: could not determine IGN", __func__);
339 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1)
340 panic("%s: could not determine version", __func__);
341 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
344 device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n",
345 desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half,
348 /* Set up the PCI interrupt retry timer. */
350 device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long)
351 SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM));
353 SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5);
355 /* Set up the PCI control register. */
356 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
357 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN |
358 STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK;
359 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK);
360 if (OF_getproplen(node, "no-bus-parking") < 0)
361 reg |= STX_PCI_CTRL_ARB_PARK;
362 if (mode == SCHIZO_MODE_TOM) {
363 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL;
364 if (sc->sc_ver <= 1) /* revision <= 2.0 */
365 reg |= TOM_PCI_CTRL_DTO_IEN;
367 reg |= STX_PCI_CTRL_PTO;
370 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
371 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL),
372 (unsigned long long)reg);
374 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg);
376 /* Set up the PCI diagnostic register. */
377 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG);
378 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS |
379 STX_PCI_DIAG_INTRSYNC_DIS);
381 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
382 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG),
383 (unsigned long long)reg);
385 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg);
388 * On Tomatillo clear the I/O prefetch lengths (workaround for a
391 if (mode == SCHIZO_MODE_TOM)
392 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW |
393 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM |
394 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL);
397 * Hunt through all the interrupt mapping regs and register
398 * the interrupt controller for our interrupt vectors. We do
399 * this early in order to be able to catch stray interrupts.
400 * This is complicated by the fact that a pair of Schizo PBMs
403 n = OF_getprop(node, "ino-bitmap", (void *)prop_array,
406 panic("%s: could not get ino-bitmap", __func__);
407 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0];
408 for (n = 0; n <= STX_MAX_INO; n++) {
409 if ((ino_bitmap & (1ULL << n)) == 0)
411 if (n == STX_FB0_INO || n == STX_FB1_INO)
412 /* Leave for upa(4). */
414 i = schizo_intr_register(sc, n);
416 device_printf(dev, "could not register interrupt "
417 "controller for INO %d (%d)\n", n, i);
421 * Setup Safari/JBus performance counter 0 in bus cycle counting
422 * mode as timecounter. Unfortunately, this is broken with at
423 * least the version 4 Tomatillos found in Fire V120 and Blade
424 * 1500, which apparently actually count some different event at
425 * ~0.5 and 3MHz respectively instead (also when running in full
426 * power mode). Besides, one counter seems to be shared by a
427 * "pair" of Tomatillos, too.
429 if (sc->sc_half == 0) {
430 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF,
431 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) |
432 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT));
433 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO);
435 panic("%s: could not malloc timecounter", __func__);
436 tc->tc_get_timecount = schizo_get_timecount;
437 tc->tc_poll_pps = NULL;
438 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK;
439 if (OF_getprop(OF_peer(0), "clock-frequency", &prop,
441 panic("%s: could not determine clock frequency",
443 tc->tc_frequency = prop;
444 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF);
445 if (mode == SCHIZO_MODE_SCZ)
446 tc->tc_quality = SCHIZO_PERF_CNT_QLTY;
448 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY;
454 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have
455 * one per PBM. Schizo and XMITS additionally have a streaming
456 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's
457 * affected by several errata and basically unusable though.
459 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS);
460 sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0;
461 if (OF_getproplen(node, "no-streaming-cache") < 0 &&
462 !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5))
463 sc->sc_is.is_sb[0] = STX_PCI_STRBUF;
466 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \
470 n = OF_getprop(node, "virtual-dma", (void *)prop_array,
472 if (n == -1 || n != sizeof(prop_array))
473 schizo_iommu_init(sc, 7, -1);
475 switch (prop_array[1]) {
485 panic("%s: unsupported DVMA size 0x%x",
486 __func__, prop_array[1]);
489 schizo_iommu_init(sc, tsbsize, prop_array[0]);
494 /* Initialize memory and I/O rmans. */
495 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
496 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports";
497 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
498 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0)
499 panic("%s: failed to set up I/O rman", __func__);
500 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
501 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory";
502 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
503 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0)
504 panic("%s: failed to set up memory rman", __func__);
506 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range),
509 * Make sure that the expected ranges are present. The
510 * OFW_PCI_CS_MEM64 one is not currently used though.
512 if (nrange != STX_NRANGE)
513 panic("%s: unsupported number of ranges", __func__);
515 * Find the addresses of the various bus spaces.
516 * There should not be multiple ones of one kind.
517 * The physical start addresses of the ranges are the configuration,
518 * memory and I/O handles.
520 for (n = 0; n < STX_NRANGE; n++) {
521 i = OFW_PCI_RANGE_CS(&range[n]);
522 if (sc->sc_pci_bh[i] != 0)
523 panic("%s: duplicate range for space %d", __func__, i);
524 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]);
526 free(range, M_OFWPROP);
528 /* Register the softc, this is needed for paired Schizos. */
529 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link);
531 /* Allocate our tags. */
532 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
533 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
534 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
535 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
536 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr,
537 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
538 panic("%s: bus_dma_tag_create failed", __func__);
539 /* Customize the tag. */
540 sc->sc_pci_dmat->dt_cookie = &sc->sc_is;
541 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods;
544 * Get the bus range from the firmware.
545 * NB: Tomatillos don't support PCI bus reenumeration.
547 n = OF_getprop(node, "bus-range", (void *)prop_array,
550 panic("%s: could not get bus-range", __func__);
551 if (n != sizeof(prop_array))
552 panic("%s: broken bus-range (%d)", __func__, n);
554 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
555 prop_array[0], prop_array[1], prop_array[0]);
556 sc->sc_pci_secbus = prop_array[0];
558 /* Clear any pending PCI error bits. */
559 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
560 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
561 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2);
562 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL,
563 SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL));
564 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR,
565 SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR));
568 * Establish handlers for interesting interrupts...
569 * Someone at Sun clearly was smoking crack; with Schizos PCI
570 * bus error interrupts for one PBM can be routed to the other
571 * PBM though we obviously need to use the softc of the former
572 * as the argument for the interrupt handler and the softc of
573 * the latter as the argument for the interrupt controller.
575 if (sc->sc_half == 0) {
576 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 ||
577 (osc != NULL && ((struct schizo_icarg *)intr_vectors[
578 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)->
581 * We are the driver for PBM A and either also
582 * registered the interrupt controller for us or
583 * the driver for PBM B has probed first and
584 * registered it for us.
586 schizo_set_intr(sc, 0, STX_PCIERR_A_INO,
588 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 &&
591 * We are the driver for PBM A but registered
592 * the interrupt controller for PBM B, i.e. the
593 * driver for PBM B attached first but couldn't
594 * set up a handler for PBM B.
596 schizo_set_intr(osc, 0, STX_PCIERR_B_INO,
599 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 ||
600 (osc != NULL && ((struct schizo_icarg *)intr_vectors[
601 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)->
604 * We are the driver for PBM B and either also
605 * registered the interrupt controller for us or
606 * the driver for PBM A has probed first and
607 * registered it for us.
609 schizo_set_intr(sc, 0, STX_PCIERR_B_INO,
611 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 &&
614 * We are the driver for PBM B but registered
615 * the interrupt controller for PBM A, i.e. the
616 * driver for PBM A attached first but couldn't
617 * set up a handler for PBM A.
619 schizo_set_intr(osc, 0, STX_PCIERR_A_INO,
622 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0)
623 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue);
624 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0)
625 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce);
626 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0)
627 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus);
630 * According to the Schizo Errata I-13, consistent DMA flushing/
631 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges,
632 * so we can't use it and need to live with the consequences.
633 * With Schizo version >= 5, CDMA flushing/syncing is usable
634 * but requires the the workaround described in Schizo Errata
635 * I-23. With Tomatillo and XMITS, CDMA flushing/syncing works
636 * as expected, Tomatillo version <= 4 (i.e. revision <= 2.3)
637 * bridges additionally require a block store after a write to
638 * TOMXMS_PCI_DMA_SYNC_PEND though.
640 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) ||
641 sc->sc_mode == SCHIZO_MODE_TOM || sc->sc_mode == SCHIZO_MODE_XMS) {
642 sc->sc_flags |= SCHIZO_FLAGS_CDMA;
643 if (sc->sc_mode == SCHIZO_MODE_SCZ) {
644 n = STX_CDMA_A_INO + sc->sc_half;
645 if (bus_set_resource(dev, SYS_RES_IRQ, 5,
646 INTMAP_VEC(sc->sc_ign, n), 1) != 0)
647 panic("%s: failed to add CDMA interrupt",
649 i = schizo_intr_register(sc, n);
651 panic("%s: could not register interrupt "
652 "controller for CDMA (%d)", __func__, i);
653 (void)schizo_get_intrmap(sc, n, NULL,
655 sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE;
656 schizo_set_intr(sc, 5, n, schizo_cdma);
658 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4)
659 sc->sc_flags |= SCHIZO_FLAGS_BSWAR;
663 * Set the latency timer register as this isn't always done by the
666 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
667 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
669 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
671 device_add_child(dev, "pci", -1);
672 return (bus_generic_attach(dev));
676 schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino,
677 driver_filter_t handler)
683 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ,
685 if (sc->sc_irq_res[index] == NULL ||
686 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign ||
687 INTINO(vec) != ino ||
688 intr_vectors[vec].iv_ic != &schizo_ic ||
689 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
690 INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc,
691 &sc->sc_ihand[index]) != 0)
692 panic("%s: failed to set up interrupt %d", __func__, index);
696 schizo_intr_register(struct schizo_softc *sc, u_int ino)
698 struct schizo_icarg *sica;
699 bus_addr_t intrclr, intrmap;
702 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0)
704 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT);
708 sica->sica_map = intrmap;
709 sica->sica_clr = intrclr;
711 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n",
712 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap),
715 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino),
718 free(sica, M_DEVBUF);
723 schizo_get_intrmap(struct schizo_softc *sc, u_int ino, bus_addr_t *intrmapptr,
724 bus_addr_t *intrclrptr)
726 bus_addr_t intrclr, intrmap;
730 * XXX we only look for INOs rather than INRs since the firmware
731 * may not provide the IGN and the IGN is constant for all devices
732 * on that PCI controller.
735 if (ino > STX_MAX_INO) {
736 device_printf(sc->sc_dev, "out of range INO %d requested\n",
741 intrmap = STX_PCI_IMAP_BASE + (ino << 3);
742 intrclr = STX_PCI_ICLR_BASE + (ino << 3);
743 mr = SCHIZO_PCI_READ_8(sc, intrmap);
744 if (INTINO(mr) != ino) {
745 device_printf(sc->sc_dev,
746 "interrupt map entry does not match INO (%d != %d)\n",
747 (int)INTINO(mr), ino);
751 if (intrmapptr != NULL)
752 *intrmapptr = intrmap;
753 if (intrclrptr != NULL)
754 *intrclrptr = intrclr;
762 schizo_pci_bus(void *arg)
764 struct schizo_softc *sc = arg;
765 uint64_t afar, afsr, csr, iommu;
768 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
769 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
770 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
771 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
772 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus,
773 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
774 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) {
775 if ((iommu & TOM_PCI_IOMMU_ERR) == 0)
778 /* These are non-fatal if target abort was signaled. */
779 if ((status & PCIM_STATUS_STABORT) != 0 &&
780 ((iommu & TOM_PCI_IOMMU_ERRMASK) ==
781 TOM_PCI_IOMMU_INVALID_ERR ||
782 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 ||
783 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) {
784 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
789 panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx "
790 "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev),
791 'A' + sc->sc_half, (unsigned long long)afar,
792 (unsigned long long)afsr, (unsigned long long)csr,
793 (unsigned long long)iommu, (unsigned long long)status);
797 device_printf(sc->sc_dev,
798 "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx "
799 "STATUS %#llx", 'A' + sc->sc_half,
800 (unsigned long long)afar, (unsigned long long)afsr,
801 (unsigned long long)csr, (unsigned long long)status);
802 /* Clear the error bits that we caught. */
803 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE,
804 STX_CS_FUNC, PCIR_STATUS, status, 2);
805 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
806 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
807 return (FILTER_HANDLED);
813 struct schizo_softc *sc = arg;
817 mtx_lock_spin(sc->sc_mtx);
818 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR);
819 for (i = 0; i < 1000; i++)
820 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
821 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
823 mtx_unlock_spin(sc->sc_mtx);
824 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx",
825 device_get_name(sc->sc_dev), (unsigned long long)afar,
826 (unsigned long long)afsr);
827 return (FILTER_HANDLED);
833 struct schizo_softc *sc = arg;
837 mtx_lock_spin(sc->sc_mtx);
838 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR);
839 for (i = 0; i < 1000; i++)
840 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
841 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
843 device_printf(sc->sc_dev,
844 "correctable DMA error AFAR %#llx AFSR %#llx\n",
845 (unsigned long long)afar, (unsigned long long)afsr);
846 /* Clear the error bits that we caught. */
847 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr);
848 mtx_unlock_spin(sc->sc_mtx);
849 return (FILTER_HANDLED);
853 schizo_host_bus(void *arg)
855 struct schizo_softc *sc = arg;
858 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG);
859 panic("%s: %s error %#llx", device_get_name(sc->sc_dev),
860 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari",
861 (unsigned long long)errlog);
862 return (FILTER_HANDLED);
866 schizo_cdma(void *arg)
868 struct schizo_softc *sc = arg;
870 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE);
871 return (FILTER_HANDLED);
875 schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase)
878 /* Punch in our copies. */
879 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
880 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]);
881 sc->sc_is.is_iommu = STX_PCI_IOMMU;
882 sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG;
883 sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG;
884 sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG;
885 sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG;
886 sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG;
888 iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize,
893 schizo_maxslots(device_t dev)
895 struct schizo_softc *sc;
897 sc = device_get_softc(dev);
898 if (sc->sc_mode == SCHIZO_MODE_SCZ)
899 return (sc->sc_half == 0 ? 4 : 6);
901 /* XXX: is this correct? */
902 return (PCI_SLOTMAX);
906 schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
909 struct schizo_softc *sc;
910 bus_space_handle_t bh;
917 sc = device_get_softc(dev);
920 * The Schizo bridges contain a dupe of their header at 0x80.
922 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus &&
923 slot == STX_CS_DEVICE && func == STX_CS_FUNC &&
927 offset = STX_CONF_OFF(bus, slot, func, reg);
928 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
931 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
935 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
939 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
943 panic("%s: bad width", __func__);
949 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
950 __func__, bus, slot, func, reg);
958 schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
959 uint32_t val, int width)
961 struct schizo_softc *sc;
962 bus_space_handle_t bh;
965 sc = device_get_softc(dev);
966 offset = STX_CONF_OFF(bus, slot, func, reg);
967 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
970 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
973 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
976 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
979 panic("%s: bad width", __func__);
985 schizo_route_interrupt(device_t bridge, device_t dev, int pin)
987 struct schizo_softc *sc;
988 struct ofw_pci_register reg;
989 ofw_pci_intr_t pintr, mintr;
990 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
992 sc = device_get_softc(bridge);
994 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®,
995 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf))
998 device_printf(bridge, "could not route pin %d for device %d.%d\n",
999 pin, pci_get_slot(dev), pci_get_function(dev));
1000 return (PCI_INVALID_IRQ);
1004 schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1006 struct schizo_softc *sc;
1008 sc = device_get_softc(dev);
1010 case PCIB_IVAR_DOMAIN:
1011 *result = device_get_unit(dev);
1014 *result = sc->sc_pci_secbus;
1021 schizo_dma_sync_stub(void *arg)
1023 struct timeval cur, end;
1024 struct schizo_dma_sync *sds = arg;
1025 struct schizo_softc *sc = sds->sds_sc;
1028 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot,
1029 sds->sds_func, PCIR_VENDOR, 2);
1030 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE,
1031 SCHIZO_CDMA_STATE_PENDING) == 0;)
1033 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1);
1037 timevaladd(&end, &cur);
1038 for (; (state = atomic_load_32(&sc->sc_cdma_state)) !=
1039 SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);)
1041 if (state != SCHIZO_CDMA_STATE_DONE)
1042 panic("%s: DMA does not sync", __func__);
1043 return (sds->sds_handler(sds->sds_arg));
1046 #define VIS_BLOCKSIZE 64
1049 ichip_dma_sync_stub(void *arg)
1051 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE);
1052 struct timeval cur, end;
1053 struct schizo_dma_sync *sds = arg;
1054 struct schizo_softc *sc = sds->sds_sc;
1057 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot,
1058 sds->sds_func, PCIR_VENDOR, 2);
1059 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval);
1063 timevaladd(&end, &cur);
1064 for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) &
1065 sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);)
1067 if ((reg & sds->sds_syncval) != 0)
1068 panic("%s: DMA does not sync", __func__);
1070 if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) {
1073 wr(fprs, reg | FPRS_FEF, 0);
1074 __asm __volatile("stda %%f0, [%0] %1"
1075 : : "r" (buf), "n" (ASI_BLK_COMMIT_S));
1080 return (sds->sds_handler(sds->sds_arg));
1084 schizo_intr_enable(void *arg)
1086 struct intr_vector *iv = arg;
1087 struct schizo_icarg *sica = iv->iv_icarg;
1089 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map,
1090 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1094 schizo_intr_disable(void *arg)
1096 struct intr_vector *iv = arg;
1097 struct schizo_icarg *sica = iv->iv_icarg;
1099 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec);
1103 schizo_intr_assign(void *arg)
1105 struct intr_vector *iv = arg;
1106 struct schizo_icarg *sica = iv->iv_icarg;
1108 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID(
1109 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid));
1113 schizo_intr_clear(void *arg)
1115 struct intr_vector *iv = arg;
1116 struct schizo_icarg *sica = iv->iv_icarg;
1118 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0);
1122 schizo_setup_intr(device_t dev, device_t child, struct resource *ires,
1123 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1126 devclass_t pci_devclass;
1127 device_t cdev, pdev, pcidev;
1128 struct schizo_dma_sync *sds;
1129 struct schizo_softc *sc;
1133 sc = device_get_softc(dev);
1135 * Make sure the vector is fully specified.
1137 vec = rman_get_start(ires);
1138 if (INTIGN(vec) != sc->sc_ign) {
1139 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1143 if (intr_vectors[vec].iv_ic == &schizo_ic) {
1145 * Ensure we use the right softc in case the interrupt
1146 * is routed to our companion PBM for some odd reason.
1148 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)->
1150 } else if (intr_vectors[vec].iv_ic == NULL) {
1152 * Work around broken firmware which misses entries in
1155 error = schizo_intr_register(sc, INTINO(vec));
1157 device_printf(dev, "could not register interrupt "
1158 "controller for vector 0x%lx (%d)\n", vec, error);
1162 device_printf(dev, "belatedly registered as "
1163 "interrupt controller for vector 0x%lx\n", vec);
1166 "invalid interrupt controller for vector 0x%lx\n", vec);
1171 * Install a a wrapper for CDMA flushing/syncing for devices
1172 * behind PCI-PCI bridges if possible.
1176 pci_devclass = devclass_find("pci");
1177 for (cdev = child; cdev != dev; cdev = pdev) {
1178 pdev = device_get_parent(cdev);
1179 if (pcidev == NULL) {
1180 if (device_get_devclass(pdev) != pci_devclass)
1185 if (pci_get_class(cdev) == PCIC_BRIDGE &&
1186 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI)
1189 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) {
1190 sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO);
1193 if (found != 0 && pcidev != NULL) {
1197 device_get_parent(device_get_parent(pcidev));
1198 sds->sds_bus = pci_get_bus(pcidev);
1199 sds->sds_slot = pci_get_slot(pcidev);
1200 sds->sds_func = pci_get_function(pcidev);
1201 sds->sds_syncval = 1ULL << INTINO(vec);
1203 device_printf(dev, "installed DMA sync "
1204 "wrapper for device %d.%d on bus %d\n",
1205 sds->sds_slot, sds->sds_func,
1208 #define DMA_SYNC_STUB \
1209 (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \
1210 ichip_dma_sync_stub)
1213 sds->sds_handler = filt;
1214 error = bus_generic_setup_intr(dev, child,
1215 ires, flags, DMA_SYNC_STUB, intr, sds,
1218 sds->sds_handler = (driver_filter_t *)intr;
1219 error = bus_generic_setup_intr(dev, child,
1220 ires, flags, filt, (driver_intr_t *)
1221 DMA_SYNC_STUB, sds, cookiep);
1224 #undef DMA_SYNC_STUB
1227 error = bus_generic_setup_intr(dev, child, ires,
1228 flags, filt, intr, arg, cookiep);
1230 free(sds, M_DEVBUF);
1233 sds->sds_cookie = *cookiep;
1236 } else if (found != 0)
1237 device_printf(dev, "WARNING: using devices behind PCI-PCI "
1238 "bridges may cause data corruption\n");
1239 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1244 schizo_teardown_intr(device_t dev, device_t child, struct resource *vec,
1247 struct schizo_dma_sync *sds;
1248 struct schizo_softc *sc;
1251 sc = device_get_softc(dev);
1252 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) {
1254 error = bus_generic_teardown_intr(dev, child, vec,
1257 free(sds, M_DEVBUF);
1260 return (bus_generic_teardown_intr(dev, child, vec, cookie));
1263 static struct resource *
1264 schizo_alloc_resource(device_t bus, device_t child, int type, int *rid,
1265 u_long start, u_long end, u_long count, u_int flags)
1267 struct schizo_softc *sc;
1268 struct resource *rv;
1271 bus_space_handle_t bh;
1272 int needactivate = flags & RF_ACTIVE;
1274 flags &= ~RF_ACTIVE;
1276 sc = device_get_softc(bus);
1277 if (type == SYS_RES_IRQ) {
1279 * XXX: Don't accept blank ranges for now, only single
1280 * interrupts. The other case should not happen with
1281 * the MI PCI code...
1282 * XXX: This may return a resource that is out of the
1283 * range that was specified. Is this correct...?
1286 panic("%s: XXX: interrupt range", __func__);
1287 start = end = INTMAP_VEC(sc->sc_ign, end);
1288 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
1289 rid, start, end, count, flags));
1292 case SYS_RES_MEMORY:
1293 rm = &sc->sc_pci_mem_rman;
1294 bt = sc->sc_pci_memt;
1295 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
1297 case SYS_RES_IOPORT:
1298 rm = &sc->sc_pci_io_rman;
1299 bt = sc->sc_pci_iot;
1300 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1307 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1310 rman_set_rid(rv, *rid);
1311 bh += rman_get_start(rv);
1312 rman_set_bustag(rv, bt);
1313 rman_set_bushandle(rv, bh);
1316 if (bus_activate_resource(child, type, *rid, rv)) {
1317 rman_release_resource(rv);
1325 schizo_activate_resource(device_t bus, device_t child, int type, int rid,
1331 if (type == SYS_RES_IRQ)
1332 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
1334 if (type == SYS_RES_MEMORY) {
1336 * Need to memory-map the device space, as some drivers
1337 * depend on the virtual address being set and usable.
1339 error = sparc64_bus_mem_map(rman_get_bustag(r),
1340 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
1343 rman_set_virtual(r, p);
1345 return (rman_activate_resource(r));
1349 schizo_deactivate_resource(device_t bus, device_t child, int type, int rid,
1353 if (type == SYS_RES_IRQ)
1354 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
1356 if (type == SYS_RES_MEMORY) {
1357 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
1358 rman_set_virtual(r, NULL);
1360 return (rman_deactivate_resource(r));
1364 schizo_release_resource(device_t bus, device_t child, int type, int rid,
1369 if (type == SYS_RES_IRQ)
1370 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
1372 if (rman_get_flags(r) & RF_ACTIVE) {
1373 error = bus_deactivate_resource(child, type, rid, r);
1377 return (rman_release_resource(r));
1380 static bus_dma_tag_t
1381 schizo_get_dma_tag(device_t bus, device_t child)
1383 struct schizo_softc *sc;
1385 sc = device_get_softc(bus);
1386 return (sc->sc_pci_dmat);
1390 schizo_get_node(device_t bus, device_t dev)
1392 struct schizo_softc *sc;
1394 sc = device_get_softc(bus);
1395 /* We only have one child, the PCI bus, which needs our own node. */
1396 return (sc->sc_node);
1399 static bus_space_tag_t
1400 schizo_alloc_bus_tag(struct schizo_softc *sc, int type)
1404 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF,
1407 panic("%s: out of memory", __func__);
1409 bt->bst_cookie = sc;
1410 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
1411 bt->bst_type = type;
1416 schizo_get_timecount(struct timecounter *tc)
1418 struct schizo_softc *sc;
1421 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) &
1422 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT));