2 * Copyright (c) 1991 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 4. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Copyright (c) 2001 Jake Burkholder.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
58 * form: src/sys/i386/isa/intr_machdep.c,v 1.57 2001/07/20
61 #include <sys/cdefs.h>
62 __FBSDID("$FreeBSD$");
64 #include <sys/param.h>
65 #include <sys/systm.h>
67 #include <sys/errno.h>
68 #include <sys/interrupt.h>
69 #include <sys/kernel.h>
72 #include <sys/mutex.h>
78 #include <machine/frame.h>
79 #include <machine/intr_machdep.h>
81 #define MAX_STRAY_LOG 5
83 CTASSERT((1 << IV_SHIFT) == sizeof(struct intr_vector));
85 ih_func_t *intr_handlers[PIL_MAX];
86 uint16_t pil_countp[PIL_MAX];
88 struct intr_vector intr_vectors[IV_MAX];
89 uint16_t intr_countp[IV_MAX];
90 static u_long intr_stray_count[IV_MAX];
92 static const char *const pil_names[] = {
95 "ithrd", /* PIL_ITHREAD */
96 "rndzvs", /* PIL_RENDEZVOUS */
98 "stop", /* PIL_STOP */
99 "preempt", /* PIL_PREEMPT */
100 "stray", "stray", "stray", "stray", "stray",
101 "filter", /* PIL_FILTER */
102 "fast", /* PIL_FAST */
103 "tick", /* PIL_TICK */
106 /* protect the intr_vectors table */
107 static struct sx intr_table_lock;
108 /* protect intrcnt_index */
109 static struct mtx intrcnt_lock;
112 static int assign_cpu;
114 static void intr_assign_next_cpu(struct intr_vector *iv);
115 static void intr_shuffle_irqs(void *arg __unused);
118 static int intr_assign_cpu(void *arg, u_char cpu);
119 static void intr_execute_handlers(void *);
120 static void intr_stray_level(struct trapframe *);
121 static void intr_stray_vector(void *);
122 static int intrcnt_setname(const char *, int);
123 static void intrcnt_updatename(int, const char *, int);
126 intrcnt_updatename(int vec, const char *name, int ispil)
128 static int intrcnt_index, stray_pil_index, stray_vec_index;
131 mtx_lock_spin(&intrcnt_lock);
132 if (intrnames[0] == '\0') {
135 printf("initalizing intr_countp\n");
136 intrcnt_setname("???", intrcnt_index++);
138 stray_vec_index = intrcnt_index++;
139 intrcnt_setname("stray", stray_vec_index);
140 for (name_index = 0; name_index < IV_MAX; name_index++)
141 intr_countp[name_index] = stray_vec_index;
143 stray_pil_index = intrcnt_index++;
144 intrcnt_setname("pil", stray_pil_index);
145 for (name_index = 0; name_index < PIL_MAX; name_index++)
146 pil_countp[name_index] = stray_pil_index;
152 if (!ispil && intr_countp[vec] != stray_vec_index)
153 name_index = intr_countp[vec];
154 else if (ispil && pil_countp[vec] != stray_pil_index)
155 name_index = pil_countp[vec];
157 name_index = intrcnt_index++;
159 if (intrcnt_setname(name, name_index))
163 intr_countp[vec] = name_index;
165 pil_countp[vec] = name_index;
166 mtx_unlock_spin(&intrcnt_lock);
170 intrcnt_setname(const char *name, int index)
173 if (intrnames + (MAXCOMLEN + 1) * index >= eintrnames)
175 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
181 intr_setup(int pri, ih_func_t *ihf, int vec, iv_func_t *ivf, void *iva)
183 char pilname[MAXCOMLEN + 1];
188 intr_vectors[vec].iv_func = ivf;
189 intr_vectors[vec].iv_arg = iva;
190 intr_vectors[vec].iv_pri = pri;
191 intr_vectors[vec].iv_vec = vec;
193 intr_handlers[pri] = ihf;
195 snprintf(pilname, MAXCOMLEN + 1, "pil%d: %s", pri, pil_names[pri]);
196 intrcnt_updatename(pri, pilname, 1);
200 intr_stray_level(struct trapframe *tf)
203 printf("stray level interrupt %ld\n", tf->tf_level);
207 intr_stray_vector(void *cookie)
209 struct intr_vector *iv;
212 if (intr_stray_count[iv->iv_vec] < MAX_STRAY_LOG) {
213 printf("stray vector interrupt %d\n", iv->iv_vec);
214 intr_stray_count[iv->iv_vec]++;
215 if (intr_stray_count[iv->iv_vec] >= MAX_STRAY_LOG)
216 printf("got %d stray interrupt %d's: not logging "
217 "anymore\n", MAX_STRAY_LOG, iv->iv_vec);
226 /* Mark all interrupts as being stray. */
227 for (i = 0; i < PIL_MAX; i++)
228 intr_handlers[i] = intr_stray_level;
229 for (i = 0; i < IV_MAX; i++) {
230 intr_vectors[i].iv_func = intr_stray_vector;
231 intr_vectors[i].iv_arg = &intr_vectors[i];
232 intr_vectors[i].iv_pri = PIL_LOW;
233 intr_vectors[i].iv_vec = i;
234 intr_vectors[i].iv_refcnt = 0;
236 intr_handlers[PIL_LOW] = intr_fast;
243 sx_init(&intr_table_lock, "intr sources");
244 mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
248 intr_assign_cpu(void *arg, u_char cpu)
252 struct intr_vector *iv;
255 * Don't do anything during early boot. We will pick up the
256 * assignment once the APs are started.
258 if (assign_cpu && cpu != NOCPU) {
263 sx_xlock(&intr_table_lock);
264 iv->iv_mid = pc->pc_mid;
265 iv->iv_ic->ic_assign(iv);
266 sx_xunlock(&intr_table_lock);
275 intr_execute_handlers(void *cookie)
277 struct intr_vector *iv;
279 struct intr_event *ie;
280 struct intr_handler *ih;
281 int error, thread, ret;
287 if (iv->iv_ic == NULL || ie == NULL) {
288 intr_stray_vector(iv);
292 /* Execute fast interrupt handlers directly. */
296 TAILQ_FOREACH(ih, &ie->ie_handlers, ih_next) {
297 if (ih->ih_filter == NULL) {
301 MPASS(ih->ih_filter != NULL && ih->ih_argument != NULL);
302 CTR3(KTR_INTR, "%s: executing handler %p(%p)", __func__,
303 ih->ih_filter, ih->ih_argument);
304 ret = ih->ih_filter(ih->ih_argument);
306 * Wrapper handler special case: see
307 * i386/intr_machdep.c::intr_execute_handlers()
310 if (ret == FILTER_SCHEDULE_THREAD)
315 iv->iv_ic->ic_clear(iv);
317 /* Schedule a heavyweight interrupt process. */
319 error = intr_event_schedule_thread(ie);
320 else if (TAILQ_EMPTY(&ie->ie_handlers))
327 if (iv->iv_ic == NULL || intr_event_handle(iv->iv_event, NULL) != 0)
329 intr_stray_vector(iv);
333 intr_controller_register(int vec, const struct intr_controller *ic,
336 struct intr_event *ie;
337 struct intr_vector *iv;
340 if (vec < 0 || vec >= IV_MAX)
342 sx_xlock(&intr_table_lock);
343 iv = &intr_vectors[vec];
345 sx_xunlock(&intr_table_lock);
348 error = intr_event_create(&ie, iv, 0, ic->ic_clear,
350 ic->ic_clear, NULL, intr_assign_cpu, "vec%d:", vec);
352 intr_assign_cpu, "vec%d:", vec);
356 sx_xlock(&intr_table_lock);
357 if (iv->iv_event != NULL) {
358 sx_xunlock(&intr_table_lock);
359 intr_event_destroy(ie);
363 iv->iv_icarg = icarg;
365 iv->iv_mid = PCPU_GET(mid);
366 sx_xunlock(&intr_table_lock);
371 inthand_add(const char *name, int vec, driver_filter_t *filt,
372 driver_intr_t *handler, void *arg, int flags, void **cookiep)
374 const struct intr_controller *ic;
375 struct intr_event *ie;
376 struct intr_handler *ih;
377 struct intr_vector *iv;
380 if (vec < 0 || vec >= IV_MAX)
383 * INTR_FAST filters/handlers are special purpose only, allowing
384 * them to be shared just would complicate things unnecessarily.
386 if ((flags & INTR_FAST) != 0 && (flags & INTR_EXCL) == 0)
388 sx_xlock(&intr_table_lock);
389 iv = &intr_vectors[vec];
392 sx_xunlock(&intr_table_lock);
393 if (ic == NULL || ie == NULL)
395 error = intr_event_add_handler(ie, name, filt, handler, arg,
396 intr_priority(flags), flags, cookiep);
399 sx_xlock(&intr_table_lock);
400 /* Disable the interrupt while we fiddle with it. */
403 if (iv->iv_refcnt == 1)
404 intr_setup((flags & INTR_FAST) != 0 ? PIL_FAST :
405 filt != NULL ? PIL_FILTER : PIL_ITHREAD, intr_fast,
406 vec, intr_execute_handlers, iv);
407 else if (filt != NULL) {
409 * Check if we need to upgrade from PIL_ITHREAD to PIL_FILTER.
410 * Given that apart from the on-board SCCs and UARTs shared
411 * interrupts are rather uncommon on sparc64 this sould be
412 * pretty rare in practice.
415 TAILQ_FOREACH(ih, &ie->ie_handlers, ih_next) {
416 if (ih->ih_filter != NULL && ih->ih_filter != filt) {
422 intr_setup(PIL_FILTER, intr_fast, vec,
423 intr_execute_handlers, iv);
425 intr_stray_count[vec] = 0;
426 intrcnt_updatename(vec, ie->ie_fullname, 0);
429 intr_assign_next_cpu(iv);
432 /* Ensure the interrupt is cleared, it might have triggered before. */
434 sx_xunlock(&intr_table_lock);
439 inthand_remove(int vec, void *cookie)
441 struct intr_vector *iv;
444 if (vec < 0 || vec >= IV_MAX)
446 error = intr_event_remove_handler(cookie);
449 * XXX: maybe this should be done regardless of whether
450 * intr_event_remove_handler() succeeded?
452 sx_xlock(&intr_table_lock);
453 iv = &intr_vectors[vec];
455 if (iv->iv_refcnt == 0) {
457 * Don't disable the interrupt for now, so that
458 * stray interrupts get detected...
460 intr_setup(PIL_LOW, intr_fast, vec,
461 intr_stray_vector, iv);
463 sx_xunlock(&intr_table_lock);
470 * Support for balancing interrupt sources across CPUs. For now we just
471 * allocate CPUs round-robin.
474 /* The BSP is always a valid target. */
475 static cpumask_t intr_cpus = (1 << 0);
476 static int current_cpu;
479 intr_assign_next_cpu(struct intr_vector *iv)
483 sx_assert(&intr_table_lock, SA_XLOCKED);
486 * Assign this source to a CPU in a round-robin fashion.
488 pc = pcpu_find(current_cpu);
491 iv->iv_mid = pc->pc_mid;
492 iv->iv_ic->ic_assign(iv);
495 if (current_cpu > mp_maxid)
497 } while (!(intr_cpus & (1 << current_cpu)));
500 /* Attempt to bind the specified IRQ to the specified CPU. */
502 intr_bind(int vec, u_char cpu)
504 struct intr_vector *iv;
506 if (vec < 0 || vec >= IV_MAX)
508 iv = &intr_vectors[vec];
511 return (intr_event_bind(iv->iv_event, cpu));
515 * Add a CPU to our mask of valid CPUs that can be destinations of
519 intr_add_cpu(u_int cpu)
523 panic("%s: Invalid CPU ID", __func__);
525 printf("INTR: Adding CPU %d as a target\n", cpu);
527 intr_cpus |= (1 << cpu);
531 * Distribute all the interrupt sources among the available CPUs once the
532 * APs have been launched.
535 intr_shuffle_irqs(void *arg __unused)
538 struct intr_vector *iv;
541 /* Don't bother on UP. */
545 sx_xlock(&intr_table_lock);
547 for (i = 0; i < IV_MAX; i++) {
548 iv = &intr_vectors[i];
549 if (iv != NULL && iv->iv_refcnt > 0) {
551 * If this event is already bound to a CPU,
552 * then assign the source to that CPU instead
553 * of picking one via round-robin.
555 if (iv->iv_event->ie_cpu != NOCPU &&
556 (pc = pcpu_find(iv->iv_event->ie_cpu)) != NULL) {
557 iv->iv_mid = pc->pc_mid;
558 iv->iv_ic->ic_assign(iv);
560 intr_assign_next_cpu(iv);
563 sx_xunlock(&intr_table_lock);
565 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,