2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department and William Jolitz of UUNET Technologies Inc.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed by the University of
24 * California, Berkeley and its contributors.
25 * 4. Neither the name of the University nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
48 * Manages physical address maps.
50 * In addition to hardware address maps, this module is called upon to
51 * provide software-use-only maps which may or may not be stored in the
52 * same form as hardware maps. These pseudo-maps are used to store
53 * intermediate results from copy operations to and from address spaces.
55 * Since the information managed by this module is also stored by the
56 * logical address mapping module, this module may throw away valid virtual
57 * to physical mappings at almost any time. However, invalidations of
58 * mappings must be done as requested.
60 * In order to cope with hardware architectures which make virtual to
61 * physical map invalidates expensive, this module may delay invalidate
62 * reduced protection operations until such time as they are actually
63 * necessary. This module is given full information as to which processors
64 * are currently using which maps, and to when physical maps must be made
68 #include "opt_kstack_pages.h"
69 #include "opt_msgbuf.h"
72 #include <sys/param.h>
73 #include <sys/kernel.h>
76 #include <sys/msgbuf.h>
77 #include <sys/mutex.h>
80 #include <sys/sysctl.h>
81 #include <sys/systm.h>
82 #include <sys/vmmeter.h>
84 #include <dev/ofw/openfirm.h>
87 #include <vm/vm_param.h>
88 #include <vm/vm_kern.h>
89 #include <vm/vm_page.h>
90 #include <vm/vm_map.h>
91 #include <vm/vm_object.h>
92 #include <vm/vm_extern.h>
93 #include <vm/vm_pageout.h>
94 #include <vm/vm_pager.h>
96 #include <machine/cache.h>
97 #include <machine/frame.h>
98 #include <machine/instr.h>
99 #include <machine/md_var.h>
100 #include <machine/metadata.h>
101 #include <machine/ofw_mem.h>
102 #include <machine/smp.h>
103 #include <machine/tlb.h>
104 #include <machine/tte.h>
105 #include <machine/tsb.h>
106 #include <machine/ver.h>
110 #ifndef PMAP_SHPGPERPROC
111 #define PMAP_SHPGPERPROC 200
115 #include "opt_sched.h"
117 #error "sparc64 only works with SCHED_4BSD which uses a global scheduler lock."
119 extern struct mtx sched_lock;
122 * Virtual and physical address of message buffer
124 struct msgbuf *msgbufp;
125 vm_paddr_t msgbuf_phys;
128 * Map of physical memory reagions
130 vm_paddr_t phys_avail[128];
131 static struct ofw_mem_region mra[128];
132 struct ofw_mem_region sparc64_memreg[128];
134 static struct ofw_map translations[128];
135 static int translations_size;
137 static vm_offset_t pmap_idle_map;
138 static vm_offset_t pmap_temp_map_1;
139 static vm_offset_t pmap_temp_map_2;
142 * First and last available kernel virtual addresses
144 vm_offset_t virtual_avail;
145 vm_offset_t virtual_end;
146 vm_offset_t kernel_vm_end;
148 vm_offset_t vm_max_kernel_address;
153 struct pmap kernel_pmap_store;
156 * Allocate physical memory for use in pmap_bootstrap.
158 static vm_paddr_t pmap_bootstrap_alloc(vm_size_t size);
161 * Map the given physical page at the specified virtual address in the
162 * target pmap with the protection requested. If specified the page
163 * will be wired down.
165 * The page queues and pmap must be locked.
167 static void pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m,
168 vm_prot_t prot, boolean_t wired);
170 extern int tl1_immu_miss_patch_1[];
171 extern int tl1_immu_miss_patch_2[];
172 extern int tl1_dmmu_miss_patch_1[];
173 extern int tl1_dmmu_miss_patch_2[];
174 extern int tl1_dmmu_prot_patch_1[];
175 extern int tl1_dmmu_prot_patch_2[];
178 * If user pmap is processed with pmap_remove and with pmap_remove and the
179 * resident count drops to 0, there are no more pages to remove, so we
182 #define PMAP_REMOVE_DONE(pm) \
183 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0)
186 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove()
187 * and pmap_protect() instead of trying each virtual address.
189 #define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE)
191 SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, "");
193 PMAP_STATS_VAR(pmap_nenter);
194 PMAP_STATS_VAR(pmap_nenter_update);
195 PMAP_STATS_VAR(pmap_nenter_replace);
196 PMAP_STATS_VAR(pmap_nenter_new);
197 PMAP_STATS_VAR(pmap_nkenter);
198 PMAP_STATS_VAR(pmap_nkenter_oc);
199 PMAP_STATS_VAR(pmap_nkenter_stupid);
200 PMAP_STATS_VAR(pmap_nkremove);
201 PMAP_STATS_VAR(pmap_nqenter);
202 PMAP_STATS_VAR(pmap_nqremove);
203 PMAP_STATS_VAR(pmap_ncache_enter);
204 PMAP_STATS_VAR(pmap_ncache_enter_c);
205 PMAP_STATS_VAR(pmap_ncache_enter_oc);
206 PMAP_STATS_VAR(pmap_ncache_enter_cc);
207 PMAP_STATS_VAR(pmap_ncache_enter_coc);
208 PMAP_STATS_VAR(pmap_ncache_enter_nc);
209 PMAP_STATS_VAR(pmap_ncache_enter_cnc);
210 PMAP_STATS_VAR(pmap_ncache_remove);
211 PMAP_STATS_VAR(pmap_ncache_remove_c);
212 PMAP_STATS_VAR(pmap_ncache_remove_oc);
213 PMAP_STATS_VAR(pmap_ncache_remove_cc);
214 PMAP_STATS_VAR(pmap_ncache_remove_coc);
215 PMAP_STATS_VAR(pmap_ncache_remove_nc);
216 PMAP_STATS_VAR(pmap_nzero_page);
217 PMAP_STATS_VAR(pmap_nzero_page_c);
218 PMAP_STATS_VAR(pmap_nzero_page_oc);
219 PMAP_STATS_VAR(pmap_nzero_page_nc);
220 PMAP_STATS_VAR(pmap_nzero_page_area);
221 PMAP_STATS_VAR(pmap_nzero_page_area_c);
222 PMAP_STATS_VAR(pmap_nzero_page_area_oc);
223 PMAP_STATS_VAR(pmap_nzero_page_area_nc);
224 PMAP_STATS_VAR(pmap_nzero_page_idle);
225 PMAP_STATS_VAR(pmap_nzero_page_idle_c);
226 PMAP_STATS_VAR(pmap_nzero_page_idle_oc);
227 PMAP_STATS_VAR(pmap_nzero_page_idle_nc);
228 PMAP_STATS_VAR(pmap_ncopy_page);
229 PMAP_STATS_VAR(pmap_ncopy_page_c);
230 PMAP_STATS_VAR(pmap_ncopy_page_oc);
231 PMAP_STATS_VAR(pmap_ncopy_page_nc);
232 PMAP_STATS_VAR(pmap_ncopy_page_dc);
233 PMAP_STATS_VAR(pmap_ncopy_page_doc);
234 PMAP_STATS_VAR(pmap_ncopy_page_sc);
235 PMAP_STATS_VAR(pmap_ncopy_page_soc);
237 PMAP_STATS_VAR(pmap_nnew_thread);
238 PMAP_STATS_VAR(pmap_nnew_thread_oc);
241 * Quick sort callout for comparing memory regions
243 static int mr_cmp(const void *a, const void *b);
244 static int om_cmp(const void *a, const void *b);
246 mr_cmp(const void *a, const void *b)
248 const struct ofw_mem_region *mra;
249 const struct ofw_mem_region *mrb;
253 if (mra->mr_start < mrb->mr_start)
255 else if (mra->mr_start > mrb->mr_start)
261 om_cmp(const void *a, const void *b)
263 const struct ofw_map *oma;
264 const struct ofw_map *omb;
268 if (oma->om_start < omb->om_start)
270 else if (oma->om_start > omb->om_start)
277 * Bootstrap the system enough to run with virtual memory.
280 pmap_bootstrap(vm_offset_t ekva)
296 * Find out what physical memory is available from the PROM and
297 * initialize the phys_avail array. This must be done before
298 * pmap_bootstrap_alloc is called.
300 if ((pmem = OF_finddevice("/memory")) == -1)
301 panic("pmap_bootstrap: finddevice /memory");
302 if ((sz = OF_getproplen(pmem, "available")) == -1)
303 panic("pmap_bootstrap: getproplen /memory/available");
304 if (sizeof(phys_avail) < sz)
305 panic("pmap_bootstrap: phys_avail too small");
306 if (sizeof(mra) < sz)
307 panic("pmap_bootstrap: mra too small");
309 if (OF_getprop(pmem, "available", mra, sz) == -1)
310 panic("pmap_bootstrap: getprop /memory/available");
312 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory");
313 qsort(mra, sz, sizeof (*mra), mr_cmp);
315 getenv_quad("hw.physmem", &physmem);
316 physmem = btoc(physmem);
317 for (i = 0, j = 0; i < sz; i++, j += 2) {
318 CTR2(KTR_PMAP, "start=%#lx size=%#lx", mra[i].mr_start,
320 if (physmem != 0 && btoc(physsz + mra[i].mr_size) >= physmem) {
321 if (btoc(physsz) < physmem) {
322 phys_avail[j] = mra[i].mr_start;
323 phys_avail[j + 1] = mra[i].mr_start +
324 (ctob(physmem) - physsz);
325 physsz = ctob(physmem);
329 phys_avail[j] = mra[i].mr_start;
330 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size;
331 physsz += mra[i].mr_size;
333 physmem = btoc(physsz);
336 * Calculate the size of kernel virtual memory, and the size and mask
337 * for the kernel TSB based on the phsyical memory size but limited
338 * by letting the kernel TSB take up no more than half of the dTLB
339 * slots available for locked entries.
341 virtsz = roundup(physsz, PAGE_SIZE_4M << (PAGE_SHIFT - TTE_SHIFT));
343 (dtlb_slots / 2 * PAGE_SIZE_4M) << (PAGE_SHIFT - TTE_SHIFT));
344 vm_max_kernel_address = VM_MIN_KERNEL_ADDRESS + virtsz;
345 tsb_kernel_size = virtsz >> (PAGE_SHIFT - TTE_SHIFT);
346 tsb_kernel_mask = (tsb_kernel_size >> TTE_SHIFT) - 1;
348 if (kernel_tlb_slots + PCPU_PAGES + tsb_kernel_size / PAGE_SIZE_4M +
349 1 /* PROM page */ + 1 /* spare */ > dtlb_slots)
350 panic("pmap_bootstrap: insufficient dTLB entries");
351 if (kernel_tlb_slots + 1 /* PROM page */ + 1 /* spare */ > itlb_slots)
352 panic("pmap_bootstrap: insufficient iTLB entries");
355 * Allocate the kernel TSB and lock it in the TLB.
357 pa = pmap_bootstrap_alloc(tsb_kernel_size);
358 if (pa & PAGE_MASK_4M)
359 panic("pmap_bootstrap: tsb unaligned\n");
360 tsb_kernel_phys = pa;
361 tsb_kernel = (struct tte *)(VM_MIN_KERNEL_ADDRESS - tsb_kernel_size);
363 bzero(tsb_kernel, tsb_kernel_size);
366 * Allocate and map the message buffer.
368 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE);
369 msgbufp = (struct msgbuf *)TLB_PHYS_TO_DIRECT(msgbuf_phys);
372 * Patch the virtual address and the tsb mask into the trap table.
375 #define SETHI(rd, imm22) \
376 (EIF_OP(IOP_FORM2) | EIF_F2_RD(rd) | EIF_F2_OP2(INS0_SETHI) | \
377 EIF_IMM((imm22) >> 10, 22))
378 #define OR_R_I_R(rd, imm13, rs1) \
379 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_OR) | \
380 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
382 #define PATCH(addr) do { \
383 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
384 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, IF_F3_RS1(addr[1])) || \
385 addr[2] != SETHI(IF_F2_RD(addr[2]), 0x0)) \
386 panic("pmap_boostrap: patched instructions have changed"); \
387 addr[0] |= EIF_IMM((tsb_kernel_mask) >> 10, 22); \
388 addr[1] |= EIF_IMM(tsb_kernel_mask, 10); \
389 addr[2] |= EIF_IMM(((vm_offset_t)tsb_kernel) >> 10, 22); \
395 PATCH(tl1_immu_miss_patch_1);
396 PATCH(tl1_immu_miss_patch_2);
397 PATCH(tl1_dmmu_miss_patch_1);
398 PATCH(tl1_dmmu_miss_patch_2);
399 PATCH(tl1_dmmu_prot_patch_1);
400 PATCH(tl1_dmmu_prot_patch_2);
403 * Enter fake 8k pages for the 4MB kernel pages, so that
404 * pmap_kextract() will work for them.
406 for (i = 0; i < kernel_tlb_slots; i++) {
407 pa = kernel_tlbs[i].te_pa;
408 va = kernel_tlbs[i].te_va;
409 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) {
410 tp = tsb_kvtotte(va + off);
411 tp->tte_vpn = TV_VPN(va + off, TS_8K);
412 tp->tte_data = TD_V | TD_8K | TD_PA(pa + off) |
413 TD_REF | TD_SW | TD_CP | TD_CV | TD_P | TD_W;
418 * Set the start and end of KVA. The kernel is loaded at the first
419 * available 4MB super page, so round up to the end of the page.
421 virtual_avail = roundup2(ekva, PAGE_SIZE_4M);
422 virtual_end = vm_max_kernel_address;
423 kernel_vm_end = vm_max_kernel_address;
426 * Allocate kva space for temporary mappings.
428 pmap_idle_map = virtual_avail;
429 virtual_avail += PAGE_SIZE * DCACHE_COLORS;
430 pmap_temp_map_1 = virtual_avail;
431 virtual_avail += PAGE_SIZE * DCACHE_COLORS;
432 pmap_temp_map_2 = virtual_avail;
433 virtual_avail += PAGE_SIZE * DCACHE_COLORS;
436 * Allocate a kernel stack with guard page for thread0 and map it
437 * into the kernel TSB. We must ensure that the virtual address is
438 * coloured properly, since we're allocating from phys_avail so the
439 * memory won't have an associated vm_page_t.
441 pa = pmap_bootstrap_alloc(roundup(KSTACK_PAGES, DCACHE_COLORS) *
444 virtual_avail += roundup(KSTACK_GUARD_PAGES, DCACHE_COLORS) *
446 kstack0 = virtual_avail;
447 virtual_avail += roundup(KSTACK_PAGES, DCACHE_COLORS) * PAGE_SIZE;
448 KASSERT(DCACHE_COLOR(kstack0) == DCACHE_COLOR(kstack0_phys),
449 ("pmap_bootstrap: kstack0 miscoloured"));
450 for (i = 0; i < KSTACK_PAGES; i++) {
451 pa = kstack0_phys + i * PAGE_SIZE;
452 va = kstack0 + i * PAGE_SIZE;
453 tp = tsb_kvtotte(va);
454 tp->tte_vpn = TV_VPN(va, TS_8K);
455 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW |
456 TD_CP | TD_CV | TD_P | TD_W;
460 * Calculate the last available physical address.
462 for (i = 0; phys_avail[i + 2] != 0; i += 2)
464 Maxmem = sparc64_btop(phys_avail[i + 1]);
467 * Add the PROM mappings to the kernel TSB.
469 if ((vmem = OF_finddevice("/virtual-memory")) == -1)
470 panic("pmap_bootstrap: finddevice /virtual-memory");
471 if ((sz = OF_getproplen(vmem, "translations")) == -1)
472 panic("pmap_bootstrap: getproplen translations");
473 if (sizeof(translations) < sz)
474 panic("pmap_bootstrap: translations too small");
475 bzero(translations, sz);
476 if (OF_getprop(vmem, "translations", translations, sz) == -1)
477 panic("pmap_bootstrap: getprop /virtual-memory/translations");
478 sz /= sizeof(*translations);
479 translations_size = sz;
480 CTR0(KTR_PMAP, "pmap_bootstrap: translations");
481 qsort(translations, sz, sizeof (*translations), om_cmp);
482 for (i = 0; i < sz; i++) {
484 "translation: start=%#lx size=%#lx tte=%#lx",
485 translations[i].om_start, translations[i].om_size,
486 translations[i].om_tte);
487 if ((translations[i].om_tte & TD_V) == 0)
489 if (translations[i].om_start < VM_MIN_PROM_ADDRESS ||
490 translations[i].om_start > VM_MAX_PROM_ADDRESS)
492 for (off = 0; off < translations[i].om_size;
494 va = translations[i].om_start + off;
495 tp = tsb_kvtotte(va);
496 tp->tte_vpn = TV_VPN(va, TS_8K);
498 ((translations[i].om_tte &
499 ~((TD_SOFT2_MASK << TD_SOFT2_SHIFT) |
500 (cpu_impl < CPU_IMPL_ULTRASPARCIII ?
501 (TD_DIAG_SF_MASK << TD_DIAG_SF_SHIFT) :
502 (TD_RSVD_CH_MASK << TD_RSVD_CH_SHIFT)) |
503 (TD_SOFT_MASK << TD_SOFT_SHIFT))) | TD_EXEC) +
509 * Get the available physical memory ranges from /memory/reg. These
510 * are only used for kernel dumps, but it may not be wise to do PROM
511 * calls in that situation.
513 if ((sz = OF_getproplen(pmem, "reg")) == -1)
514 panic("pmap_bootstrap: getproplen /memory/reg");
515 if (sizeof(sparc64_memreg) < sz)
516 panic("pmap_bootstrap: sparc64_memreg too small");
517 if (OF_getprop(pmem, "reg", sparc64_memreg, sz) == -1)
518 panic("pmap_bootstrap: getprop /memory/reg");
519 sparc64_nmemreg = sz / sizeof(*sparc64_memreg);
522 * Initialize the kernel pmap (which is statically allocated).
523 * NOTE: PMAP_LOCK_INIT() is needed as part of the initialization
524 * but sparc64 start up is not ready to initialize mutexes yet.
525 * It is called in machdep.c.
528 for (i = 0; i < MAXCPU; i++)
529 pm->pm_context[i] = TLB_CTX_KERNEL;
533 * Flush all non-locked TLB entries possibly left over by the
536 tlb_flush_nonlocked();
551 * Map the 4MB TSB pages.
553 for (i = 0; i < tsb_kernel_size; i += PAGE_SIZE_4M) {
554 va = (vm_offset_t)tsb_kernel + i;
555 pa = tsb_kernel_phys + i;
556 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV |
558 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) |
559 TLB_TAR_CTX(TLB_CTX_KERNEL));
560 stxa_sync(0, ASI_DTLB_DATA_IN_REG, data);
564 * Set the secondary context to be the kernel context (needed for
565 * FP block operations in the kernel).
567 stxa(AA_DMMU_SCXR, ASI_DMMU, (ldxa(AA_DMMU_SCXR, ASI_DMMU) &
568 TLB_SCXR_PGSZ_MASK) | TLB_CTX_KERNEL);
575 * Allocate a physical page of memory directly from the phys_avail map.
576 * Can only be called from pmap_bootstrap before avail start and end are
580 pmap_bootstrap_alloc(vm_size_t size)
585 size = round_page(size);
586 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
587 if (phys_avail[i + 1] - phys_avail[i] < size)
590 phys_avail[i] += size;
593 panic("pmap_bootstrap_alloc");
597 * Initialize a vm_page's machine-dependent fields.
600 pmap_page_init(vm_page_t m)
603 TAILQ_INIT(&m->md.tte_list);
604 m->md.color = DCACHE_COLOR(VM_PAGE_TO_PHYS(m));
610 * Initialize the pmap module.
620 for (i = 0; i < translations_size; i++) {
621 addr = translations[i].om_start;
622 size = translations[i].om_size;
623 if ((translations[i].om_tte & TD_V) == 0)
625 if (addr < VM_MIN_PROM_ADDRESS || addr > VM_MAX_PROM_ADDRESS)
627 result = vm_map_find(kernel_map, NULL, 0, &addr, size, FALSE,
628 VM_PROT_ALL, VM_PROT_ALL, 0);
629 if (result != KERN_SUCCESS || addr != translations[i].om_start)
630 panic("pmap_init: vm_map_find");
635 * Extract the physical page address associated with the given
636 * map/virtual_address pair.
639 pmap_extract(pmap_t pm, vm_offset_t va)
644 if (pm == kernel_pmap)
645 return (pmap_kextract(va));
647 tp = tsb_tte_lookup(pm, va);
651 pa = TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp));
657 * Atomically extract and hold the physical page with the given
658 * pmap and virtual address pair if that mapping permits the given
662 pmap_extract_and_hold(pmap_t pm, vm_offset_t va, vm_prot_t prot)
668 vm_page_lock_queues();
669 if (pm == kernel_pmap) {
670 if (va >= VM_MIN_DIRECT_ADDRESS) {
672 m = PHYS_TO_VM_PAGE(TLB_DIRECT_TO_PHYS(va));
675 tp = tsb_kvtotte(va);
676 if ((tp->tte_data & TD_V) == 0)
681 tp = tsb_tte_lookup(pm, va);
683 if (tp != NULL && ((tp->tte_data & TD_SW) ||
684 (prot & VM_PROT_WRITE) == 0)) {
685 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
688 vm_page_unlock_queues();
689 if (pm != kernel_pmap)
695 * Extract the physical page address associated with the given kernel virtual
699 pmap_kextract(vm_offset_t va)
703 if (va >= VM_MIN_DIRECT_ADDRESS)
704 return (TLB_DIRECT_TO_PHYS(va));
705 tp = tsb_kvtotte(va);
706 if ((tp->tte_data & TD_V) == 0)
708 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp)));
712 pmap_cache_enter(vm_page_t m, vm_offset_t va)
717 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
718 KASSERT((m->flags & PG_FICTITIOUS) == 0,
719 ("pmap_cache_enter: fake page"));
720 PMAP_STATS_INC(pmap_ncache_enter);
723 * Find the color for this virtual address and note the added mapping.
725 color = DCACHE_COLOR(va);
726 m->md.colors[color]++;
729 * If all existing mappings have the same color, the mapping is
732 if (m->md.color == color) {
733 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] == 0,
734 ("pmap_cache_enter: cacheable, mappings of other color"));
735 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
736 PMAP_STATS_INC(pmap_ncache_enter_c);
738 PMAP_STATS_INC(pmap_ncache_enter_oc);
743 * If there are no mappings of the other color, and the page still has
744 * the wrong color, this must be a new mapping. Change the color to
745 * match the new mapping, which is cacheable. We must flush the page
746 * from the cache now.
748 if (m->md.colors[DCACHE_OTHER_COLOR(color)] == 0) {
749 KASSERT(m->md.colors[color] == 1,
750 ("pmap_cache_enter: changing color, not new mapping"));
751 dcache_page_inval(VM_PAGE_TO_PHYS(m));
753 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
754 PMAP_STATS_INC(pmap_ncache_enter_cc);
756 PMAP_STATS_INC(pmap_ncache_enter_coc);
761 * If the mapping is already non-cacheable, just return.
763 if (m->md.color == -1) {
764 PMAP_STATS_INC(pmap_ncache_enter_nc);
768 PMAP_STATS_INC(pmap_ncache_enter_cnc);
771 * Mark all mappings as uncacheable, flush any lines with the other
772 * color out of the dcache, and set the color to none (-1).
774 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
775 atomic_clear_long(&tp->tte_data, TD_CV);
776 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
778 dcache_page_inval(VM_PAGE_TO_PHYS(m));
784 pmap_cache_remove(vm_page_t m, vm_offset_t va)
789 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
790 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va,
791 m->md.colors[DCACHE_COLOR(va)]);
792 KASSERT((m->flags & PG_FICTITIOUS) == 0,
793 ("pmap_cache_remove: fake page"));
794 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0,
795 ("pmap_cache_remove: no mappings %d <= 0",
796 m->md.colors[DCACHE_COLOR(va)]));
797 PMAP_STATS_INC(pmap_ncache_remove);
800 * Find the color for this virtual address and note the removal of
803 color = DCACHE_COLOR(va);
804 m->md.colors[color]--;
807 * If the page is cacheable, just return and keep the same color, even
808 * if there are no longer any mappings.
810 if (m->md.color != -1) {
811 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
812 PMAP_STATS_INC(pmap_ncache_remove_c);
814 PMAP_STATS_INC(pmap_ncache_remove_oc);
818 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] != 0,
819 ("pmap_cache_remove: uncacheable, no mappings of other color"));
822 * If the page is not cacheable (color is -1), and the number of
823 * mappings for this color is not zero, just return. There are
824 * mappings of the other color still, so remain non-cacheable.
826 if (m->md.colors[color] != 0) {
827 PMAP_STATS_INC(pmap_ncache_remove_nc);
832 * The number of mappings for this color is now zero. Recache the
833 * other colored mappings, and change the page color to the other
834 * color. There should be no lines in the data cache for this page,
835 * so flushing should not be needed.
837 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
838 atomic_set_long(&tp->tte_data, TD_CV);
839 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
841 m->md.color = DCACHE_OTHER_COLOR(color);
843 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
844 PMAP_STATS_INC(pmap_ncache_remove_cc);
846 PMAP_STATS_INC(pmap_ncache_remove_coc);
850 * Map a wired page into kernel virtual address space.
853 pmap_kenter(vm_offset_t va, vm_page_t m)
860 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
861 PMAP_STATS_INC(pmap_nkenter);
862 tp = tsb_kvtotte(va);
863 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx",
864 va, VM_PAGE_TO_PHYS(m), tp, tp->tte_data);
865 if (DCACHE_COLOR(VM_PAGE_TO_PHYS(m)) != DCACHE_COLOR(va)) {
867 "pmap_kenter: off colour va=%#lx pa=%#lx o=%p oc=%#lx ot=%d pi=%#lx",
868 va, VM_PAGE_TO_PHYS(m), m->object,
869 m->object ? m->object->pg_color : -1,
870 m->object ? m->object->type : -1,
872 PMAP_STATS_INC(pmap_nkenter_oc);
874 if ((tp->tte_data & TD_V) != 0) {
875 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
876 ova = TTE_GET_VA(tp);
877 if (m == om && va == ova) {
878 PMAP_STATS_INC(pmap_nkenter_stupid);
881 TAILQ_REMOVE(&om->md.tte_list, tp, tte_link);
882 pmap_cache_remove(om, ova);
884 tlb_page_demap(kernel_pmap, ova);
886 data = TD_V | TD_8K | VM_PAGE_TO_PHYS(m) | TD_REF | TD_SW | TD_CP |
888 if (pmap_cache_enter(m, va) != 0)
890 tp->tte_vpn = TV_VPN(va, TS_8K);
892 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
896 * Map a wired page into kernel virtual address space. This additionally
897 * takes a flag argument wich is or'ed to the TTE data. This is used by
898 * sparc64_bus_mem_map().
899 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility
900 * to flush entries that might still be in the cache, if applicable.
903 pmap_kenter_flags(vm_offset_t va, vm_paddr_t pa, u_long flags)
907 tp = tsb_kvtotte(va);
908 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx",
909 va, pa, tp, tp->tte_data);
910 tp->tte_vpn = TV_VPN(va, TS_8K);
911 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags;
915 * Remove a wired page from kernel virtual address space.
918 pmap_kremove(vm_offset_t va)
923 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
924 PMAP_STATS_INC(pmap_nkremove);
925 tp = tsb_kvtotte(va);
926 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp,
928 if ((tp->tte_data & TD_V) == 0)
930 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
931 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
932 pmap_cache_remove(m, va);
937 * Inverse of pmap_kenter_flags, used by bus_space_unmap().
940 pmap_kremove_flags(vm_offset_t va)
944 tp = tsb_kvtotte(va);
945 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp,
951 * Map a range of physical addresses into kernel virtual address space.
953 * The value passed in *virt is a suggested virtual address for the mapping.
954 * Architectures which can support a direct-mapped physical to virtual region
955 * can return the appropriate address within that region, leaving '*virt'
959 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
962 return (TLB_PHYS_TO_DIRECT(start));
966 * Map a list of wired pages into kernel virtual address space. This is
967 * intended for temporary mappings which do not need page modification or
968 * references recorded. Existing mappings in the region are overwritten.
971 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count)
976 PMAP_STATS_INC(pmap_nqenter);
978 if (!(locked = mtx_owned(&vm_page_queue_mtx)))
979 vm_page_lock_queues();
980 while (count-- > 0) {
986 vm_page_unlock_queues();
987 tlb_range_demap(kernel_pmap, sva, va);
991 * Remove page mappings from kernel virtual address space. Intended for
992 * temporary mappings entered by pmap_qenter.
995 pmap_qremove(vm_offset_t sva, int count)
1000 PMAP_STATS_INC(pmap_nqremove);
1002 if (!(locked = mtx_owned(&vm_page_queue_mtx)))
1003 vm_page_lock_queues();
1004 while (count-- > 0) {
1009 vm_page_unlock_queues();
1010 tlb_range_demap(kernel_pmap, sva, va);
1014 * Initialize the pmap associated with process 0.
1017 pmap_pinit0(pmap_t pm)
1022 for (i = 0; i < MAXCPU; i++)
1023 pm->pm_context[i] = 0;
1026 pm->pm_tsb_obj = NULL;
1027 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1031 * Initialize a preallocated and zeroed pmap structure, such as one in a
1032 * vmspace structure.
1035 pmap_pinit(pmap_t pm)
1037 vm_page_t ma[TSB_PAGES];
1044 * Allocate KVA space for the TSB.
1046 if (pm->pm_tsb == NULL) {
1047 pm->pm_tsb = (struct tte *)kmem_alloc_nofault(kernel_map,
1049 if (pm->pm_tsb == NULL) {
1050 PMAP_LOCK_DESTROY(pm);
1056 * Allocate an object for it.
1058 if (pm->pm_tsb_obj == NULL)
1059 pm->pm_tsb_obj = vm_object_allocate(OBJT_DEFAULT, TSB_PAGES);
1061 VM_OBJECT_LOCK(pm->pm_tsb_obj);
1062 for (i = 0; i < TSB_PAGES; i++) {
1063 m = vm_page_grab(pm->pm_tsb_obj, i, VM_ALLOC_NOBUSY |
1064 VM_ALLOC_RETRY | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1065 m->valid = VM_PAGE_BITS_ALL;
1069 VM_OBJECT_UNLOCK(pm->pm_tsb_obj);
1070 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES);
1072 for (i = 0; i < MAXCPU; i++)
1073 pm->pm_context[i] = -1;
1075 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1080 * Release any resources held by the given physical map.
1081 * Called when a pmap initialized by pmap_pinit is being released.
1082 * Should only be called if the map contains no valid mappings.
1085 pmap_release(pmap_t pm)
1091 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p",
1092 pm->pm_context[curcpu], pm->pm_tsb);
1093 KASSERT(pmap_resident_count(pm) == 0,
1094 ("pmap_release: resident pages %ld != 0",
1095 pmap_resident_count(pm)));
1098 * After the pmap was freed, it might be reallocated to a new process.
1099 * When switching, this might lead us to wrongly assume that we need
1100 * not switch contexts because old and new pmap pointer are equal.
1101 * Therefore, make sure that this pmap is not referenced by any PCPU
1102 * pointer any more. This could happen in two cases:
1103 * - A process that referenced the pmap is currently exiting on a CPU.
1104 * However, it is guaranteed to not switch in any more after setting
1105 * its state to PRS_ZOMBIE.
1106 * - A process that referenced this pmap ran on a CPU, but we switched
1107 * to a kernel thread, leaving the pmap pointer unchanged.
1109 mtx_lock_spin(&sched_lock);
1110 SLIST_FOREACH(pc, &cpuhead, pc_allcpu) {
1111 if (pc->pc_pmap == pm)
1114 mtx_unlock_spin(&sched_lock);
1116 obj = pm->pm_tsb_obj;
1117 VM_OBJECT_LOCK(obj);
1118 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1"));
1119 while (!TAILQ_EMPTY(&obj->memq)) {
1120 m = TAILQ_FIRST(&obj->memq);
1121 vm_page_lock_queues();
1122 if (vm_page_sleep_if_busy(m, FALSE, "pmaprl"))
1124 KASSERT(m->hold_count == 0,
1125 ("pmap_release: freeing held tsb page"));
1128 atomic_subtract_int(&cnt.v_wire_count, 1);
1129 vm_page_free_zero(m);
1130 vm_page_unlock_queues();
1132 VM_OBJECT_UNLOCK(obj);
1133 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES);
1134 PMAP_LOCK_DESTROY(pm);
1138 * Grow the number of kernel page table entries. Unneeded.
1141 pmap_growkernel(vm_offset_t addr)
1144 panic("pmap_growkernel: can't grow kernel");
1148 pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1154 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1155 data = atomic_readandclear_long(&tp->tte_data);
1156 if ((data & TD_FAKE) == 0) {
1157 m = PHYS_TO_VM_PAGE(TD_PA(data));
1158 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1159 if ((data & TD_WIRED) != 0)
1160 pm->pm_stats.wired_count--;
1161 if ((data & TD_PV) != 0) {
1162 if ((data & TD_W) != 0)
1164 if ((data & TD_REF) != 0)
1165 vm_page_flag_set(m, PG_REFERENCED);
1166 if (TAILQ_EMPTY(&m->md.tte_list))
1167 vm_page_flag_clear(m, PG_WRITEABLE);
1168 pm->pm_stats.resident_count--;
1170 pmap_cache_remove(m, va);
1173 if (PMAP_REMOVE_DONE(pm))
1179 * Remove the given range of addresses from the specified map.
1182 pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end)
1187 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx",
1188 pm->pm_context[curcpu], start, end);
1189 if (PMAP_REMOVE_DONE(pm))
1191 vm_page_lock_queues();
1193 if (end - start > PMAP_TSB_THRESH) {
1194 tsb_foreach(pm, NULL, start, end, pmap_remove_tte);
1195 tlb_context_demap(pm);
1197 for (va = start; va < end; va += PAGE_SIZE) {
1198 if ((tp = tsb_tte_lookup(pm, va)) != NULL) {
1199 if (!pmap_remove_tte(pm, NULL, tp, va))
1203 tlb_range_demap(pm, start, end - 1);
1206 vm_page_unlock_queues();
1210 pmap_remove_all(vm_page_t m)
1217 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1218 for (tp = TAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) {
1219 tpn = TAILQ_NEXT(tp, tte_link);
1220 if ((tp->tte_data & TD_PV) == 0)
1222 pm = TTE_GET_PMAP(tp);
1223 va = TTE_GET_VA(tp);
1225 if ((tp->tte_data & TD_WIRED) != 0)
1226 pm->pm_stats.wired_count--;
1227 if ((tp->tte_data & TD_REF) != 0)
1228 vm_page_flag_set(m, PG_REFERENCED);
1229 if ((tp->tte_data & TD_W) != 0)
1231 tp->tte_data &= ~TD_V;
1232 tlb_page_demap(pm, va);
1233 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1234 pm->pm_stats.resident_count--;
1235 pmap_cache_remove(m, va);
1239 vm_page_flag_clear(m, PG_WRITEABLE);
1243 pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1249 data = atomic_clear_long(&tp->tte_data, TD_REF | TD_SW | TD_W);
1250 if ((data & TD_PV) != 0) {
1251 m = PHYS_TO_VM_PAGE(TD_PA(data));
1252 if ((data & TD_REF) != 0)
1253 vm_page_flag_set(m, PG_REFERENCED);
1254 if ((data & TD_W) != 0)
1261 * Set the physical protection on the specified range of this map as requested.
1264 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1269 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx",
1270 pm->pm_context[curcpu], sva, eva, prot);
1272 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1273 pmap_remove(pm, sva, eva);
1277 if (prot & VM_PROT_WRITE)
1280 vm_page_lock_queues();
1282 if (eva - sva > PMAP_TSB_THRESH) {
1283 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte);
1284 tlb_context_demap(pm);
1286 for (va = sva; va < eva; va += PAGE_SIZE) {
1287 if ((tp = tsb_tte_lookup(pm, va)) != NULL)
1288 pmap_protect_tte(pm, NULL, tp, va);
1290 tlb_range_demap(pm, sva, eva - 1);
1293 vm_page_unlock_queues();
1297 * Map the given physical page at the specified virtual address in the
1298 * target pmap with the protection requested. If specified the page
1299 * will be wired down.
1302 pmap_enter(pmap_t pm, vm_offset_t va, vm_prot_t access, vm_page_t m,
1303 vm_prot_t prot, boolean_t wired)
1306 vm_page_lock_queues();
1308 pmap_enter_locked(pm, va, m, prot, wired);
1309 vm_page_unlock_queues();
1314 * Map the given physical page at the specified virtual address in the
1315 * target pmap with the protection requested. If specified the page
1316 * will be wired down.
1318 * The page queues and pmap must be locked.
1321 pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1329 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1330 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1331 PMAP_STATS_INC(pmap_nenter);
1332 pa = VM_PAGE_TO_PHYS(m);
1335 * If this is a fake page from the device_pager, but it covers actual
1336 * physical memory, convert to the real backing page.
1338 if ((m->flags & PG_FICTITIOUS) != 0) {
1339 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1340 if (pa >= phys_avail[i] && pa <= phys_avail[i + 1]) {
1341 m = PHYS_TO_VM_PAGE(pa);
1348 "pmap_enter: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d",
1349 pm->pm_context[curcpu], m, va, pa, prot, wired);
1352 * If there is an existing mapping, and the physical address has not
1353 * changed, must be protection or wiring change.
1355 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) {
1356 CTR0(KTR_PMAP, "pmap_enter: update");
1357 PMAP_STATS_INC(pmap_nenter_update);
1360 * Wiring change, just update stats.
1363 if ((tp->tte_data & TD_WIRED) == 0) {
1364 tp->tte_data |= TD_WIRED;
1365 pm->pm_stats.wired_count++;
1368 if ((tp->tte_data & TD_WIRED) != 0) {
1369 tp->tte_data &= ~TD_WIRED;
1370 pm->pm_stats.wired_count--;
1375 * Save the old bits and clear the ones we're interested in.
1377 data = tp->tte_data;
1378 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W);
1381 * If we're turning off write permissions, sense modify status.
1383 if ((prot & VM_PROT_WRITE) != 0) {
1384 tp->tte_data |= TD_SW;
1386 tp->tte_data |= TD_W;
1388 vm_page_flag_set(m, PG_WRITEABLE);
1389 } else if ((data & TD_W) != 0) {
1394 * If we're turning on execute permissions, flush the icache.
1396 if ((prot & VM_PROT_EXECUTE) != 0) {
1397 if ((data & TD_EXEC) == 0) {
1398 icache_page_inval(pa);
1400 tp->tte_data |= TD_EXEC;
1404 * Delete the old mapping.
1406 tlb_page_demap(pm, TTE_GET_VA(tp));
1409 * If there is an existing mapping, but its for a different
1410 * phsyical address, delete the old mapping.
1413 CTR0(KTR_PMAP, "pmap_enter: replace");
1414 PMAP_STATS_INC(pmap_nenter_replace);
1415 pmap_remove_tte(pm, NULL, tp, va);
1416 tlb_page_demap(pm, va);
1418 CTR0(KTR_PMAP, "pmap_enter: new");
1419 PMAP_STATS_INC(pmap_nenter_new);
1423 * Now set up the data and install the new mapping.
1425 data = TD_V | TD_8K | TD_PA(pa);
1426 if (pm == kernel_pmap)
1428 if ((prot & VM_PROT_WRITE) != 0) {
1430 vm_page_flag_set(m, PG_WRITEABLE);
1432 if (prot & VM_PROT_EXECUTE) {
1434 icache_page_inval(pa);
1438 * If its wired update stats. We also don't need reference or
1439 * modify tracking for wired mappings, so set the bits now.
1442 pm->pm_stats.wired_count++;
1443 data |= TD_REF | TD_WIRED;
1444 if ((prot & VM_PROT_WRITE) != 0)
1448 tsb_tte_enter(pm, m, va, TS_8K, data);
1453 * Maps a sequence of resident pages belonging to the same object.
1454 * The sequence begins with the given page m_start. This page is
1455 * mapped at the given virtual address start. Each subsequent page is
1456 * mapped at a virtual address that is offset from start by the same
1457 * amount as the page is offset from m_start within the object. The
1458 * last page in the sequence is the page with the largest offset from
1459 * m_start that can be mapped at a virtual address less than the given
1460 * virtual address end. Not every virtual page between start and end
1461 * is mapped; only those for which a resident page exists with the
1462 * corresponding offset from m_start are mapped.
1465 pmap_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end,
1466 vm_page_t m_start, vm_prot_t prot)
1469 vm_pindex_t diff, psize;
1471 psize = atop(end - start);
1474 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1475 pmap_enter_locked(pm, start + ptoa(diff), m, prot &
1476 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1477 m = TAILQ_NEXT(m, listq);
1483 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot)
1487 pmap_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1493 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object,
1494 vm_pindex_t pindex, vm_size_t size)
1497 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
1498 KASSERT(object->type == OBJT_DEVICE,
1499 ("pmap_object_init_pt: non-device object"));
1503 * Change the wiring attribute for a map/virtual-address pair.
1504 * The mapping must already exist in the pmap.
1507 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired)
1513 if ((tp = tsb_tte_lookup(pm, va)) != NULL) {
1515 data = atomic_set_long(&tp->tte_data, TD_WIRED);
1516 if ((data & TD_WIRED) == 0)
1517 pm->pm_stats.wired_count++;
1519 data = atomic_clear_long(&tp->tte_data, TD_WIRED);
1520 if ((data & TD_WIRED) != 0)
1521 pm->pm_stats.wired_count--;
1528 pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp, vm_offset_t va)
1533 if ((tp->tte_data & TD_FAKE) != 0)
1535 if (tsb_tte_lookup(dst_pmap, va) == NULL) {
1536 data = tp->tte_data &
1537 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W);
1538 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1539 tsb_tte_enter(dst_pmap, m, va, TS_8K, data);
1545 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
1546 vm_size_t len, vm_offset_t src_addr)
1551 if (dst_addr != src_addr)
1553 vm_page_lock_queues();
1554 if (dst_pmap < src_pmap) {
1555 PMAP_LOCK(dst_pmap);
1556 PMAP_LOCK(src_pmap);
1558 PMAP_LOCK(src_pmap);
1559 PMAP_LOCK(dst_pmap);
1561 if (len > PMAP_TSB_THRESH) {
1562 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len,
1564 tlb_context_demap(dst_pmap);
1566 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE) {
1567 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL)
1568 pmap_copy_tte(src_pmap, dst_pmap, tp, va);
1570 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1);
1572 vm_page_unlock_queues();
1573 PMAP_UNLOCK(src_pmap);
1574 PMAP_UNLOCK(dst_pmap);
1578 pmap_zero_page(vm_page_t m)
1584 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1585 ("pmap_zero_page: fake page"));
1586 PMAP_STATS_INC(pmap_nzero_page);
1587 pa = VM_PAGE_TO_PHYS(m);
1588 if (m->md.color == -1) {
1589 PMAP_STATS_INC(pmap_nzero_page_nc);
1590 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1591 } else if (m->md.color == DCACHE_COLOR(pa)) {
1592 PMAP_STATS_INC(pmap_nzero_page_c);
1593 va = TLB_PHYS_TO_DIRECT(pa);
1594 cpu_block_zero((void *)va, PAGE_SIZE);
1596 PMAP_STATS_INC(pmap_nzero_page_oc);
1597 PMAP_LOCK(kernel_pmap);
1598 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1599 tp = tsb_kvtotte(va);
1600 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1601 tp->tte_vpn = TV_VPN(va, TS_8K);
1602 cpu_block_zero((void *)va, PAGE_SIZE);
1603 tlb_page_demap(kernel_pmap, va);
1604 PMAP_UNLOCK(kernel_pmap);
1609 pmap_zero_page_area(vm_page_t m, int off, int size)
1615 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1616 ("pmap_zero_page_area: fake page"));
1617 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size"));
1618 PMAP_STATS_INC(pmap_nzero_page_area);
1619 pa = VM_PAGE_TO_PHYS(m);
1620 if (m->md.color == -1) {
1621 PMAP_STATS_INC(pmap_nzero_page_area_nc);
1622 aszero(ASI_PHYS_USE_EC, pa + off, size);
1623 } else if (m->md.color == DCACHE_COLOR(pa)) {
1624 PMAP_STATS_INC(pmap_nzero_page_area_c);
1625 va = TLB_PHYS_TO_DIRECT(pa);
1626 bzero((void *)(va + off), size);
1628 PMAP_STATS_INC(pmap_nzero_page_area_oc);
1629 PMAP_LOCK(kernel_pmap);
1630 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1631 tp = tsb_kvtotte(va);
1632 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1633 tp->tte_vpn = TV_VPN(va, TS_8K);
1634 bzero((void *)(va + off), size);
1635 tlb_page_demap(kernel_pmap, va);
1636 PMAP_UNLOCK(kernel_pmap);
1641 pmap_zero_page_idle(vm_page_t m)
1647 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1648 ("pmap_zero_page_idle: fake page"));
1649 PMAP_STATS_INC(pmap_nzero_page_idle);
1650 pa = VM_PAGE_TO_PHYS(m);
1651 if (m->md.color == -1) {
1652 PMAP_STATS_INC(pmap_nzero_page_idle_nc);
1653 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1654 } else if (m->md.color == DCACHE_COLOR(pa)) {
1655 PMAP_STATS_INC(pmap_nzero_page_idle_c);
1656 va = TLB_PHYS_TO_DIRECT(pa);
1657 cpu_block_zero((void *)va, PAGE_SIZE);
1659 PMAP_STATS_INC(pmap_nzero_page_idle_oc);
1660 va = pmap_idle_map + (m->md.color * PAGE_SIZE);
1661 tp = tsb_kvtotte(va);
1662 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1663 tp->tte_vpn = TV_VPN(va, TS_8K);
1664 cpu_block_zero((void *)va, PAGE_SIZE);
1665 tlb_page_demap(kernel_pmap, va);
1670 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
1678 KASSERT((mdst->flags & PG_FICTITIOUS) == 0,
1679 ("pmap_copy_page: fake dst page"));
1680 KASSERT((msrc->flags & PG_FICTITIOUS) == 0,
1681 ("pmap_copy_page: fake src page"));
1682 PMAP_STATS_INC(pmap_ncopy_page);
1683 pdst = VM_PAGE_TO_PHYS(mdst);
1684 psrc = VM_PAGE_TO_PHYS(msrc);
1685 if (msrc->md.color == -1 && mdst->md.color == -1) {
1686 PMAP_STATS_INC(pmap_ncopy_page_nc);
1687 ascopy(ASI_PHYS_USE_EC, psrc, pdst, PAGE_SIZE);
1688 } else if (msrc->md.color == DCACHE_COLOR(psrc) &&
1689 mdst->md.color == DCACHE_COLOR(pdst)) {
1690 PMAP_STATS_INC(pmap_ncopy_page_c);
1691 vdst = TLB_PHYS_TO_DIRECT(pdst);
1692 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1693 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1694 } else if (msrc->md.color == -1) {
1695 if (mdst->md.color == DCACHE_COLOR(pdst)) {
1696 PMAP_STATS_INC(pmap_ncopy_page_dc);
1697 vdst = TLB_PHYS_TO_DIRECT(pdst);
1698 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1701 PMAP_STATS_INC(pmap_ncopy_page_doc);
1702 PMAP_LOCK(kernel_pmap);
1703 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1704 tp = tsb_kvtotte(vdst);
1706 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1707 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1708 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1710 tlb_page_demap(kernel_pmap, vdst);
1711 PMAP_UNLOCK(kernel_pmap);
1713 } else if (mdst->md.color == -1) {
1714 if (msrc->md.color == DCACHE_COLOR(psrc)) {
1715 PMAP_STATS_INC(pmap_ncopy_page_sc);
1716 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1717 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1720 PMAP_STATS_INC(pmap_ncopy_page_soc);
1721 PMAP_LOCK(kernel_pmap);
1722 vsrc = pmap_temp_map_1 + (msrc->md.color * PAGE_SIZE);
1723 tp = tsb_kvtotte(vsrc);
1725 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1726 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1727 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1729 tlb_page_demap(kernel_pmap, vsrc);
1730 PMAP_UNLOCK(kernel_pmap);
1733 PMAP_STATS_INC(pmap_ncopy_page_oc);
1734 PMAP_LOCK(kernel_pmap);
1735 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1736 tp = tsb_kvtotte(vdst);
1738 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1739 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1740 vsrc = pmap_temp_map_2 + (msrc->md.color * PAGE_SIZE);
1741 tp = tsb_kvtotte(vsrc);
1743 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1744 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1745 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1746 tlb_page_demap(kernel_pmap, vdst);
1747 tlb_page_demap(kernel_pmap, vsrc);
1748 PMAP_UNLOCK(kernel_pmap);
1753 * Returns true if the pmap's pv is one of the first
1754 * 16 pvs linked to from this page. This count may
1755 * be changed upwards or downwards in the future; it
1756 * is only necessary that true be returned for a small
1757 * subset of pmaps for proper page aging.
1760 pmap_page_exists_quick(pmap_t pm, vm_page_t m)
1765 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1766 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1769 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1770 if ((tp->tte_data & TD_PV) == 0)
1772 if (TTE_GET_PMAP(tp) == pm)
1781 * Remove all pages from specified address space, this aids process exit
1782 * speeds. This is much faster than pmap_remove n the case of running down
1783 * an entire address space. Only works for the current pmap.
1786 pmap_remove_pages(pmap_t pm)
1792 * Returns TRUE if the given page has a managed mapping.
1795 pmap_page_is_mapped(vm_page_t m)
1799 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1801 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1802 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1803 if ((tp->tte_data & TD_PV) != 0)
1810 * Return a count of reference bits for a page, clearing those bits.
1811 * It is not necessary for every reference bit to be cleared, but it
1812 * is necessary that 0 only be returned when there are truly no
1813 * reference bits set.
1815 * XXX: The exact number of bits to check and clear is a matter that
1816 * should be tested and standardized at some point in the future for
1817 * optimal aging of shared pages.
1820 pmap_ts_referenced(vm_page_t m)
1828 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1829 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1832 if ((tp = TAILQ_FIRST(&m->md.tte_list)) != NULL) {
1835 tpn = TAILQ_NEXT(tp, tte_link);
1836 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1837 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
1838 if ((tp->tte_data & TD_PV) == 0)
1840 data = atomic_clear_long(&tp->tte_data, TD_REF);
1841 if ((data & TD_REF) != 0 && ++count > 4)
1843 } while ((tp = tpn) != NULL && tp != tpf);
1849 pmap_is_modified(vm_page_t m)
1853 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1854 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1856 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1857 if ((tp->tte_data & TD_PV) == 0)
1859 if ((tp->tte_data & TD_W) != 0)
1866 * pmap_is_prefaultable:
1868 * Return whether or not the specified virtual address is elgible
1872 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1879 pmap_clear_modify(vm_page_t m)
1884 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1885 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1887 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1888 if ((tp->tte_data & TD_PV) == 0)
1890 data = atomic_clear_long(&tp->tte_data, TD_W);
1891 if ((data & TD_W) != 0)
1892 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1897 pmap_clear_reference(vm_page_t m)
1902 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1903 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1905 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1906 if ((tp->tte_data & TD_PV) == 0)
1908 data = atomic_clear_long(&tp->tte_data, TD_REF);
1909 if ((data & TD_REF) != 0)
1910 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1915 pmap_remove_write(vm_page_t m)
1920 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1921 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
1922 (m->flags & PG_WRITEABLE) == 0)
1924 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1925 if ((tp->tte_data & TD_PV) == 0)
1927 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
1928 if ((data & TD_W) != 0) {
1930 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1933 vm_page_flag_clear(m, PG_WRITEABLE);
1937 pmap_mincore(pmap_t pm, vm_offset_t addr)
1945 * Activate a user pmap. The pmap must be activated before its address space
1946 * can be accessed in any way.
1949 pmap_activate(struct thread *td)
1955 vm = td->td_proc->p_vmspace;
1956 pm = vmspace_pmap(vm);
1958 mtx_lock_spin(&sched_lock);
1960 context = PCPU_GET(tlb_ctx);
1961 if (context == PCPU_GET(tlb_ctx_max)) {
1963 context = PCPU_GET(tlb_ctx_min);
1965 PCPU_SET(tlb_ctx, context + 1);
1967 pm->pm_context[curcpu] = context;
1968 pm->pm_active |= PCPU_GET(cpumask);
1971 stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb);
1972 stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb);
1973 stxa(AA_DMMU_PCXR, ASI_DMMU, (ldxa(AA_DMMU_PCXR, ASI_DMMU) &
1974 TLB_PCXR_PGSZ_MASK) | context);
1977 mtx_unlock_spin(&sched_lock);
1981 pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size)
1988 * Increase the starting virtual address of the given mapping if a
1989 * different alignment might result in more superpage mappings.
1992 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
1993 vm_offset_t *addr, vm_size_t size)