2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
61 * o TCP/IP checksum offload for both RX and TX
63 * o High and normal priority transmit DMA rings
65 * o VLAN tag insertion and extraction
67 * o TCP large send (segmentation offload)
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
82 * o GMII and TBI ports/registers for interfacing with copper
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
88 * o Slight differences in register layout from the 8139C+
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/sysctl.h>
127 #include <sys/taskqueue.h>
130 #include <net/if_arp.h>
131 #include <net/ethernet.h>
132 #include <net/if_dl.h>
133 #include <net/if_media.h>
134 #include <net/if_types.h>
135 #include <net/if_vlan_var.h>
139 #include <machine/bus.h>
140 #include <machine/resource.h>
142 #include <sys/rman.h>
144 #include <dev/mii/mii.h>
145 #include <dev/mii/miivar.h>
147 #include <dev/pci/pcireg.h>
148 #include <dev/pci/pcivar.h>
150 #include <pci/if_rlreg.h>
152 MODULE_DEPEND(re, pci, 1, 1, 1);
153 MODULE_DEPEND(re, ether, 1, 1, 1);
154 MODULE_DEPEND(re, miibus, 1, 1, 1);
156 /* "device miibus" required. See GENERIC if you get errors here. */
157 #include "miibus_if.h"
160 static int msi_disable = 0;
161 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
162 static int prefer_iomap = 0;
163 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
165 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
168 * Various supported device vendors/types and their names.
170 static struct rl_type re_devs[] = {
171 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
172 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
173 { RT_VENDORID, RT_DEVICEID_8139, 0,
174 "RealTek 8139C+ 10/100BaseTX" },
175 { RT_VENDORID, RT_DEVICEID_8101E, 0,
176 "RealTek 8101E/8102E/8102EL/8103E PCIe 10/100baseTX" },
177 { RT_VENDORID, RT_DEVICEID_8168, 0,
178 "RealTek 8168/8111 B/C/CP/D/DP/E PCIe Gigabit Ethernet" },
179 { RT_VENDORID, RT_DEVICEID_8169, 0,
180 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
181 { RT_VENDORID, RT_DEVICEID_8169SC, 0,
182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
183 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
184 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
185 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
186 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
187 { USR_VENDORID, USR_DEVICEID_997902, 0,
188 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
191 static struct rl_hwrev re_hwrevs[] = {
192 { RL_HWREV_8139, RL_8139, "" },
193 { RL_HWREV_8139A, RL_8139, "A" },
194 { RL_HWREV_8139AG, RL_8139, "A-G" },
195 { RL_HWREV_8139B, RL_8139, "B" },
196 { RL_HWREV_8130, RL_8139, "8130" },
197 { RL_HWREV_8139C, RL_8139, "C" },
198 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
199 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
200 { RL_HWREV_8168_SPIN1, RL_8169, "8168"},
201 { RL_HWREV_8169, RL_8169, "8169"},
202 { RL_HWREV_8169S, RL_8169, "8169S"},
203 { RL_HWREV_8110S, RL_8169, "8110S"},
204 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"},
205 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"},
206 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"},
207 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"},
208 { RL_HWREV_8100, RL_8139, "8100"},
209 { RL_HWREV_8101, RL_8139, "8101"},
210 { RL_HWREV_8100E, RL_8169, "8100E"},
211 { RL_HWREV_8101E, RL_8169, "8101E"},
212 { RL_HWREV_8102E, RL_8169, "8102E"},
213 { RL_HWREV_8102EL, RL_8169, "8102EL"},
214 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL"},
215 { RL_HWREV_8103E, RL_8169, "8103E"},
216 { RL_HWREV_8168_SPIN2, RL_8169, "8168"},
217 { RL_HWREV_8168_SPIN3, RL_8169, "8168"},
218 { RL_HWREV_8168C, RL_8169, "8168C/8111C"},
219 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"},
220 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"},
221 { RL_HWREV_8168D, RL_8169, "8168D/8111D"},
222 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP"},
223 { RL_HWREV_8168E, RL_8169, "8168E/8111E"},
227 static int re_probe (device_t);
228 static int re_attach (device_t);
229 static int re_detach (device_t);
231 static int re_encap (struct rl_softc *, struct mbuf **);
233 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
234 static int re_allocmem (device_t, struct rl_softc *);
235 static __inline void re_discard_rxbuf
236 (struct rl_softc *, int);
237 static int re_newbuf (struct rl_softc *, int);
238 static int re_rx_list_init (struct rl_softc *);
239 static int re_tx_list_init (struct rl_softc *);
241 static __inline void re_fixup_rx
244 static int re_rxeof (struct rl_softc *, int *);
245 static void re_txeof (struct rl_softc *);
246 #ifdef DEVICE_POLLING
247 static int re_poll (struct ifnet *, enum poll_cmd, int);
248 static int re_poll_locked (struct ifnet *, enum poll_cmd, int);
250 static int re_intr (void *);
251 static void re_tick (void *);
252 static void re_tx_task (void *, int);
253 static void re_int_task (void *, int);
254 static void re_start (struct ifnet *);
255 static int re_ioctl (struct ifnet *, u_long, caddr_t);
256 static void re_init (void *);
257 static void re_init_locked (struct rl_softc *);
258 static void re_stop (struct rl_softc *);
259 static void re_watchdog (struct rl_softc *);
260 static int re_suspend (device_t);
261 static int re_resume (device_t);
262 static int re_shutdown (device_t);
263 static int re_ifmedia_upd (struct ifnet *);
264 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
266 static void re_eeprom_putbyte (struct rl_softc *, int);
267 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
268 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
269 static int re_gmii_readreg (device_t, int, int);
270 static int re_gmii_writereg (device_t, int, int, int);
272 static int re_miibus_readreg (device_t, int, int);
273 static int re_miibus_writereg (device_t, int, int, int);
274 static void re_miibus_statchg (device_t);
276 static void re_set_rxmode (struct rl_softc *);
277 static void re_reset (struct rl_softc *);
278 static void re_setwol (struct rl_softc *);
279 static void re_clrwol (struct rl_softc *);
282 static int re_diag (struct rl_softc *);
285 static void re_add_sysctls (struct rl_softc *);
286 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS);
288 static device_method_t re_methods[] = {
289 /* Device interface */
290 DEVMETHOD(device_probe, re_probe),
291 DEVMETHOD(device_attach, re_attach),
292 DEVMETHOD(device_detach, re_detach),
293 DEVMETHOD(device_suspend, re_suspend),
294 DEVMETHOD(device_resume, re_resume),
295 DEVMETHOD(device_shutdown, re_shutdown),
298 DEVMETHOD(bus_print_child, bus_generic_print_child),
299 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
302 DEVMETHOD(miibus_readreg, re_miibus_readreg),
303 DEVMETHOD(miibus_writereg, re_miibus_writereg),
304 DEVMETHOD(miibus_statchg, re_miibus_statchg),
309 static driver_t re_driver = {
312 sizeof(struct rl_softc)
315 static devclass_t re_devclass;
317 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
318 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
321 CSR_WRITE_1(sc, RL_EECMD, \
322 CSR_READ_1(sc, RL_EECMD) | x)
325 CSR_WRITE_1(sc, RL_EECMD, \
326 CSR_READ_1(sc, RL_EECMD) & ~x)
329 * Send a read command and address to the EEPROM, check for ACK.
332 re_eeprom_putbyte(struct rl_softc *sc, int addr)
336 d = addr | (RL_9346_READ << sc->rl_eewidth);
339 * Feed in each bit and strobe the clock.
342 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
344 EE_SET(RL_EE_DATAIN);
346 EE_CLR(RL_EE_DATAIN);
357 * Read a word of data stored in the EEPROM at address 'addr.'
360 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
366 * Send address of word we want to read.
368 re_eeprom_putbyte(sc, addr);
371 * Start reading bits from EEPROM.
373 for (i = 0x8000; i; i >>= 1) {
376 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
386 * Read a sequence of words from the EEPROM.
389 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
392 u_int16_t word = 0, *ptr;
394 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
398 for (i = 0; i < cnt; i++) {
399 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
400 re_eeprom_getword(sc, off + i, &word);
401 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
402 ptr = (u_int16_t *)(dest + (i * 2));
406 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
410 re_gmii_readreg(device_t dev, int phy, int reg)
416 sc = device_get_softc(dev);
418 /* Let the rgephy driver read the GMEDIASTAT register */
420 if (reg == RL_GMEDIASTAT) {
421 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
425 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
427 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
428 rval = CSR_READ_4(sc, RL_PHYAR);
429 if (rval & RL_PHYAR_BUSY)
434 if (i == RL_PHY_TIMEOUT) {
435 device_printf(sc->rl_dev, "PHY read failed\n");
440 * Controller requires a 20us delay to process next MDIO request.
444 return (rval & RL_PHYAR_PHYDATA);
448 re_gmii_writereg(device_t dev, int phy, int reg, int data)
454 sc = device_get_softc(dev);
456 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
457 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
459 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
460 rval = CSR_READ_4(sc, RL_PHYAR);
461 if (!(rval & RL_PHYAR_BUSY))
466 if (i == RL_PHY_TIMEOUT) {
467 device_printf(sc->rl_dev, "PHY write failed\n");
472 * Controller requires a 20us delay to process next MDIO request.
480 re_miibus_readreg(device_t dev, int phy, int reg)
484 u_int16_t re8139_reg = 0;
486 sc = device_get_softc(dev);
488 if (sc->rl_type == RL_8169) {
489 rval = re_gmii_readreg(dev, phy, reg);
495 re8139_reg = RL_BMCR;
498 re8139_reg = RL_BMSR;
501 re8139_reg = RL_ANAR;
504 re8139_reg = RL_ANER;
507 re8139_reg = RL_LPAR;
513 * Allow the rlphy driver to read the media status
514 * register. If we have a link partner which does not
515 * support NWAY, this is the register which will tell
516 * us the results of parallel detection.
519 rval = CSR_READ_1(sc, RL_MEDIASTAT);
522 device_printf(sc->rl_dev, "bad phy register\n");
525 rval = CSR_READ_2(sc, re8139_reg);
526 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
527 /* 8139C+ has different bit layout. */
528 rval &= ~(BMCR_LOOP | BMCR_ISO);
534 re_miibus_writereg(device_t dev, int phy, int reg, int data)
537 u_int16_t re8139_reg = 0;
540 sc = device_get_softc(dev);
542 if (sc->rl_type == RL_8169) {
543 rval = re_gmii_writereg(dev, phy, reg, data);
549 re8139_reg = RL_BMCR;
550 if (sc->rl_type == RL_8139CPLUS) {
551 /* 8139C+ has different bit layout. */
552 data &= ~(BMCR_LOOP | BMCR_ISO);
556 re8139_reg = RL_BMSR;
559 re8139_reg = RL_ANAR;
562 re8139_reg = RL_ANER;
565 re8139_reg = RL_LPAR;
572 device_printf(sc->rl_dev, "bad phy register\n");
575 CSR_WRITE_2(sc, re8139_reg, data);
580 re_miibus_statchg(device_t dev)
584 struct mii_data *mii;
586 sc = device_get_softc(dev);
587 mii = device_get_softc(sc->rl_miibus);
589 if (mii == NULL || ifp == NULL ||
590 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
593 sc->rl_flags &= ~RL_FLAG_LINK;
594 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
595 (IFM_ACTIVE | IFM_AVALID)) {
596 switch (IFM_SUBTYPE(mii->mii_media_active)) {
599 sc->rl_flags |= RL_FLAG_LINK;
602 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
604 sc->rl_flags |= RL_FLAG_LINK;
611 * RealTek controllers does not provide any interface to
612 * Tx/Rx MACs for resolved speed, duplex and flow-control
618 * Set the RX configuration and 64-bit multicast hash filter.
621 re_set_rxmode(struct rl_softc *sc)
624 struct ifmultiaddr *ifma;
625 uint32_t hashes[2] = { 0, 0 };
632 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
634 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
635 if (ifp->if_flags & IFF_PROMISC)
636 rxfilt |= RL_RXCFG_RX_ALLPHYS;
638 * Unlike other hardwares, we have to explicitly set
639 * RL_RXCFG_RX_MULTI to receive multicast frames in
642 rxfilt |= RL_RXCFG_RX_MULTI;
643 hashes[0] = hashes[1] = 0xffffffff;
648 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
649 if (ifma->ifma_addr->sa_family != AF_LINK)
651 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
652 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
654 hashes[0] |= (1 << h);
656 hashes[1] |= (1 << (h - 32));
658 if_maddr_runlock(ifp);
660 if (hashes[0] != 0 || hashes[1] != 0) {
662 * For some unfathomable reason, RealTek decided to
663 * reverse the order of the multicast hash registers
664 * in the PCI Express parts. This means we have to
665 * write the hash pattern in reverse order for those
668 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
669 h = bswap32(hashes[0]);
670 hashes[0] = bswap32(hashes[1]);
673 rxfilt |= RL_RXCFG_RX_MULTI;
677 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
678 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
679 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
683 re_reset(struct rl_softc *sc)
689 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
691 for (i = 0; i < RL_TIMEOUT; i++) {
693 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
697 device_printf(sc->rl_dev, "reset never completed!\n");
699 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
700 CSR_WRITE_1(sc, 0x82, 1);
701 if (sc->rl_hwrev == RL_HWREV_8169S)
702 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
708 * The following routine is designed to test for a defect on some
709 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
710 * lines connected to the bus, however for a 32-bit only card, they
711 * should be pulled high. The result of this defect is that the
712 * NIC will not work right if you plug it into a 64-bit slot: DMA
713 * operations will be done with 64-bit transfers, which will fail
714 * because the 64-bit data lines aren't connected.
716 * There's no way to work around this (short of talking a soldering
717 * iron to the board), however we can detect it. The method we use
718 * here is to put the NIC into digital loopback mode, set the receiver
719 * to promiscuous mode, and then try to send a frame. We then compare
720 * the frame data we sent to what was received. If the data matches,
721 * then the NIC is working correctly, otherwise we know the user has
722 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
723 * slot. In the latter case, there's no way the NIC can work correctly,
724 * so we print out a message on the console and abort the device attach.
728 re_diag(struct rl_softc *sc)
730 struct ifnet *ifp = sc->rl_ifp;
732 struct ether_header *eh;
733 struct rl_desc *cur_rx;
736 int total_len, i, error = 0, phyaddr;
737 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
738 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
740 /* Allocate a single mbuf */
741 MGETHDR(m0, M_DONTWAIT, MT_DATA);
748 * Initialize the NIC in test mode. This sets the chip up
749 * so that it can send and receive frames, but performs the
750 * following special functions:
751 * - Puts receiver in promiscuous mode
752 * - Enables digital loopback mode
753 * - Leaves interrupts turned off
756 ifp->if_flags |= IFF_PROMISC;
758 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
760 sc->rl_flags |= RL_FLAG_LINK;
761 if (sc->rl_type == RL_8169)
766 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
767 for (i = 0; i < RL_TIMEOUT; i++) {
768 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
769 if (!(status & BMCR_RESET))
773 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
774 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
778 /* Put some data in the mbuf */
780 eh = mtod(m0, struct ether_header *);
781 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
782 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
783 eh->ether_type = htons(ETHERTYPE_IP);
784 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
787 * Queue the packet, start transmission.
788 * Note: IF_HANDOFF() ultimately calls re_start() for us.
791 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
793 /* XXX: re_diag must not be called when in ALTQ mode */
794 IF_HANDOFF(&ifp->if_snd, m0, ifp);
798 /* Wait for it to propagate through the chip */
801 for (i = 0; i < RL_TIMEOUT; i++) {
802 status = CSR_READ_2(sc, RL_ISR);
803 CSR_WRITE_2(sc, RL_ISR, status);
804 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
805 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
810 if (i == RL_TIMEOUT) {
811 device_printf(sc->rl_dev,
812 "diagnostic failed, failed to receive packet in"
819 * The packet should have been dumped into the first
820 * entry in the RX DMA ring. Grab it from there.
823 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
824 sc->rl_ldata.rl_rx_list_map,
825 BUS_DMASYNC_POSTREAD);
826 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
827 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
828 BUS_DMASYNC_POSTREAD);
829 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
830 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
832 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
833 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
834 eh = mtod(m0, struct ether_header *);
836 cur_rx = &sc->rl_ldata.rl_rx_list[0];
837 total_len = RL_RXBYTES(cur_rx);
838 rxstat = le32toh(cur_rx->rl_cmdstat);
840 if (total_len != ETHER_MIN_LEN) {
841 device_printf(sc->rl_dev,
842 "diagnostic failed, received short packet\n");
847 /* Test that the received packet data matches what we sent. */
849 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
850 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
851 ntohs(eh->ether_type) != ETHERTYPE_IP) {
852 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
853 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
854 dst, ":", src, ":", ETHERTYPE_IP);
855 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
856 eh->ether_dhost, ":", eh->ether_shost, ":",
857 ntohs(eh->ether_type));
858 device_printf(sc->rl_dev, "You may have a defective 32-bit "
859 "NIC plugged into a 64-bit PCI slot.\n");
860 device_printf(sc->rl_dev, "Please re-install the NIC in a "
861 "32-bit slot for proper operation.\n");
862 device_printf(sc->rl_dev, "Read the re(4) man page for more "
868 /* Turn interface off, release resources */
871 sc->rl_flags &= ~RL_FLAG_LINK;
872 ifp->if_flags &= ~IFF_PROMISC;
885 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
886 * IDs against our list and return a device name if we find a match.
889 re_probe(device_t dev)
892 uint16_t devid, vendor;
893 uint16_t revid, sdevid;
896 vendor = pci_get_vendor(dev);
897 devid = pci_get_device(dev);
898 revid = pci_get_revid(dev);
899 sdevid = pci_get_subdevice(dev);
901 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
902 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
904 * Only attach to rev. 3 of the Linksys EG1032 adapter.
905 * Rev. 2 is supported by sk(4).
911 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
913 /* 8139, let rl(4) take care of this device. */
919 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
920 if (vendor == t->rl_vid && devid == t->rl_did) {
921 device_set_desc(dev, t->rl_name);
922 return (BUS_PROBE_DEFAULT);
930 * Map a single buffer address.
934 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
941 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
943 *addr = segs->ds_addr;
947 re_allocmem(device_t dev, struct rl_softc *sc)
950 bus_size_t rx_list_size, tx_list_size;
954 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
955 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
958 * Allocate the parent bus DMA tag appropriate for PCI.
959 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
960 * register should be set. However some RealTek chips are known
961 * to be buggy on DAC handling, therefore disable DAC by limiting
962 * DMA address space to 32bit. PCIe variants of RealTek chips
963 * may not have the limitation.
965 lowaddr = BUS_SPACE_MAXADDR;
966 if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
967 lowaddr = BUS_SPACE_MAXADDR_32BIT;
968 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
969 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
970 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
971 NULL, NULL, &sc->rl_parent_tag);
973 device_printf(dev, "could not allocate parent DMA tag\n");
978 * Allocate map for TX mbufs.
980 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
981 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
982 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
983 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
985 device_printf(dev, "could not allocate TX DMA tag\n");
990 * Allocate map for RX mbufs.
993 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
994 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
995 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
997 device_printf(dev, "could not allocate RX DMA tag\n");
1002 * Allocate map for TX descriptor list.
1004 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1005 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1006 NULL, tx_list_size, 1, tx_list_size, 0,
1007 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1009 device_printf(dev, "could not allocate TX DMA ring tag\n");
1013 /* Allocate DMA'able memory for the TX ring */
1015 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1016 (void **)&sc->rl_ldata.rl_tx_list,
1017 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1018 &sc->rl_ldata.rl_tx_list_map);
1020 device_printf(dev, "could not allocate TX DMA ring\n");
1024 /* Load the map for the TX ring. */
1026 sc->rl_ldata.rl_tx_list_addr = 0;
1027 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1028 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1029 tx_list_size, re_dma_map_addr,
1030 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1031 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1032 device_printf(dev, "could not load TX DMA ring\n");
1036 /* Create DMA maps for TX buffers */
1038 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1039 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1040 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1042 device_printf(dev, "could not create DMA map for TX\n");
1048 * Allocate map for RX descriptor list.
1050 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1051 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1052 NULL, rx_list_size, 1, rx_list_size, 0,
1053 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1055 device_printf(dev, "could not create RX DMA ring tag\n");
1059 /* Allocate DMA'able memory for the RX ring */
1061 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1062 (void **)&sc->rl_ldata.rl_rx_list,
1063 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1064 &sc->rl_ldata.rl_rx_list_map);
1066 device_printf(dev, "could not allocate RX DMA ring\n");
1070 /* Load the map for the RX ring. */
1072 sc->rl_ldata.rl_rx_list_addr = 0;
1073 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1074 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1075 rx_list_size, re_dma_map_addr,
1076 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1077 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1078 device_printf(dev, "could not load RX DMA ring\n");
1082 /* Create DMA maps for RX buffers */
1084 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1085 &sc->rl_ldata.rl_rx_sparemap);
1087 device_printf(dev, "could not create spare DMA map for RX\n");
1090 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1091 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1092 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1094 device_printf(dev, "could not create DMA map for RX\n");
1099 /* Create DMA map for statistics. */
1100 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1101 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1102 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
1103 &sc->rl_ldata.rl_stag);
1105 device_printf(dev, "could not create statistics DMA tag\n");
1108 /* Allocate DMA'able memory for statistics. */
1109 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1110 (void **)&sc->rl_ldata.rl_stats,
1111 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1112 &sc->rl_ldata.rl_smap);
1115 "could not allocate statistics DMA memory\n");
1118 /* Load the map for statistics. */
1119 sc->rl_ldata.rl_stats_addr = 0;
1120 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1121 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1122 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1123 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1124 device_printf(dev, "could not load statistics DMA memory\n");
1132 * Attach the interface. Allocate softc structures, do ifmedia
1133 * setup and ethernet/BPF attach.
1136 re_attach(device_t dev)
1138 u_char eaddr[ETHER_ADDR_LEN];
1139 u_int16_t as[ETHER_ADDR_LEN / 2];
1140 struct rl_softc *sc;
1142 struct rl_hwrev *hw_rev;
1144 u_int16_t devid, re_did = 0;
1145 int error = 0, i, phy, rid;
1149 sc = device_get_softc(dev);
1152 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1154 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1157 * Map control/status registers.
1159 pci_enable_busmaster(dev);
1161 devid = pci_get_device(dev);
1163 * Prefer memory space register mapping over IO space.
1164 * Because RTL8169SC does not seem to work when memory mapping
1165 * is used always activate io mapping.
1167 if (devid == RT_DEVICEID_8169SC)
1169 if (prefer_iomap == 0) {
1170 sc->rl_res_id = PCIR_BAR(1);
1171 sc->rl_res_type = SYS_RES_MEMORY;
1172 /* RTL8168/8101E seems to use different BARs. */
1173 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1174 sc->rl_res_id = PCIR_BAR(2);
1176 sc->rl_res_id = PCIR_BAR(0);
1177 sc->rl_res_type = SYS_RES_IOPORT;
1179 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1180 &sc->rl_res_id, RF_ACTIVE);
1181 if (sc->rl_res == NULL && prefer_iomap == 0) {
1182 sc->rl_res_id = PCIR_BAR(0);
1183 sc->rl_res_type = SYS_RES_IOPORT;
1184 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1185 &sc->rl_res_id, RF_ACTIVE);
1187 if (sc->rl_res == NULL) {
1188 device_printf(dev, "couldn't map ports/memory\n");
1193 sc->rl_btag = rman_get_bustag(sc->rl_res);
1194 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1197 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
1198 sc->rl_flags |= RL_FLAG_PCIE;
1199 if (devid != RT_DEVICEID_8101E) {
1200 /* Set PCIe maximum read request size to 2048. */
1201 if (pci_get_max_read_req(dev) < 2048)
1202 pci_set_max_read_req(dev, 2048);
1204 msic = pci_msi_count(dev);
1206 device_printf(dev, "MSI count : %d\n", msic);
1208 if (msic > 0 && msi_disable == 0) {
1210 if (pci_alloc_msi(dev, &msic) == 0) {
1211 if (msic == RL_MSI_MESSAGES) {
1212 device_printf(dev, "Using %d MSI messages\n",
1214 sc->rl_flags |= RL_FLAG_MSI;
1215 /* Explicitly set MSI enable bit. */
1216 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1217 cfg = CSR_READ_1(sc, RL_CFG2);
1219 CSR_WRITE_1(sc, RL_CFG2, cfg);
1220 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1222 pci_release_msi(dev);
1226 /* Allocate interrupt */
1227 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1229 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1230 RF_SHAREABLE | RF_ACTIVE);
1231 if (sc->rl_irq[0] == NULL) {
1232 device_printf(dev, "couldn't allocate IRQ resources\n");
1237 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1238 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1239 SYS_RES_IRQ, &rid, RF_ACTIVE);
1240 if (sc->rl_irq[i] == NULL) {
1242 "couldn't llocate IRQ resources for "
1243 "message %d\n", rid);
1250 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1251 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1252 cfg = CSR_READ_1(sc, RL_CFG2);
1253 if ((cfg & RL_CFG2_MSI) != 0) {
1254 device_printf(dev, "turning off MSI enable bit.\n");
1255 cfg &= ~RL_CFG2_MSI;
1256 CSR_WRITE_1(sc, RL_CFG2, cfg);
1258 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1261 /* Reset the adapter. */
1267 hwrev = CSR_READ_4(sc, RL_TXCFG);
1268 switch (hwrev & 0x70000000) {
1271 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1272 hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1275 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1276 hwrev &= RL_TXCFG_HWREV;
1279 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000);
1280 while (hw_rev->rl_desc != NULL) {
1281 if (hw_rev->rl_rev == hwrev) {
1282 sc->rl_type = hw_rev->rl_type;
1283 sc->rl_hwrev = hw_rev->rl_rev;
1288 if (hw_rev->rl_desc == NULL) {
1289 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1294 switch (hw_rev->rl_rev) {
1295 case RL_HWREV_8139CPLUS:
1296 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER |
1299 case RL_HWREV_8100E:
1300 case RL_HWREV_8101E:
1301 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE |
1304 case RL_HWREV_8102E:
1305 case RL_HWREV_8102EL:
1306 case RL_HWREV_8102EL_SPIN1:
1307 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE |
1308 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1309 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
1311 case RL_HWREV_8103E:
1312 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE |
1313 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1314 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
1317 case RL_HWREV_8168_SPIN1:
1318 case RL_HWREV_8168_SPIN2:
1319 sc->rl_flags |= RL_FLAG_WOLRXENB;
1321 case RL_HWREV_8168_SPIN3:
1322 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1324 case RL_HWREV_8168C_SPIN2:
1325 sc->rl_flags |= RL_FLAG_MACSLEEP;
1327 case RL_HWREV_8168C:
1328 if ((hwrev & 0x00700000) == 0x00200000)
1329 sc->rl_flags |= RL_FLAG_MACSLEEP;
1331 case RL_HWREV_8168CP:
1332 case RL_HWREV_8168D:
1333 case RL_HWREV_8168DP:
1334 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1335 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1338 * These controllers support jumbo frame but it seems
1339 * that enabling it requires touching additional magic
1340 * registers. Depending on MAC revisions some
1341 * controllers need to disable checksum offload. So
1342 * disable jumbo frame until I have better idea what
1343 * it really requires to make it support.
1344 * RTL8168C/CP : supports up to 6KB jumbo frame.
1345 * RTL8111C/CP : supports up to 9KB jumbo frame.
1347 sc->rl_flags |= RL_FLAG_NOJUMBO;
1349 case RL_HWREV_8168E:
1350 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1351 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1352 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_NOJUMBO;
1354 case RL_HWREV_8169_8110SB:
1355 case RL_HWREV_8169_8110SBL:
1356 case RL_HWREV_8169_8110SC:
1357 case RL_HWREV_8169_8110SCE:
1358 sc->rl_flags |= RL_FLAG_PHYWAKE;
1361 case RL_HWREV_8169S:
1362 case RL_HWREV_8110S:
1363 sc->rl_flags |= RL_FLAG_MACRESET;
1370 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1371 cfg = CSR_READ_1(sc, RL_CFG1);
1373 CSR_WRITE_1(sc, RL_CFG1, cfg);
1374 cfg = CSR_READ_1(sc, RL_CFG5);
1375 cfg &= RL_CFG5_PME_STS;
1376 CSR_WRITE_1(sc, RL_CFG5, cfg);
1377 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1379 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1381 * XXX Should have a better way to extract station
1382 * address from EEPROM.
1384 for (i = 0; i < ETHER_ADDR_LEN; i++)
1385 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1387 sc->rl_eewidth = RL_9356_ADDR_LEN;
1388 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1389 if (re_did != 0x8129)
1390 sc->rl_eewidth = RL_9346_ADDR_LEN;
1393 * Get station address from the EEPROM.
1395 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1396 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1397 as[i] = le16toh(as[i]);
1398 bcopy(as, eaddr, sizeof(eaddr));
1401 if (sc->rl_type == RL_8169) {
1402 /* Set RX length mask and number of descriptors. */
1403 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1404 sc->rl_txstart = RL_GTXSTART;
1405 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1406 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1408 /* Set RX length mask and number of descriptors. */
1409 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1410 sc->rl_txstart = RL_TXSTART;
1411 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1412 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1415 error = re_allocmem(dev, sc);
1420 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1422 device_printf(dev, "can not if_alloc()\n");
1427 /* Take controller out of deep sleep mode. */
1428 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1429 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1430 CSR_WRITE_1(sc, RL_GPIO,
1431 CSR_READ_1(sc, RL_GPIO) | 0x01);
1433 CSR_WRITE_1(sc, RL_GPIO,
1434 CSR_READ_1(sc, RL_GPIO) & ~0x01);
1437 /* Take PHY out of power down mode. */
1438 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
1439 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1440 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1441 re_gmii_writereg(dev, 1, 0x1f, 0);
1442 re_gmii_writereg(dev, 1, 0x0e, 0);
1445 #define RE_PHYAD_INTERNAL 0
1448 phy = RE_PHYAD_INTERNAL;
1449 if (sc->rl_type == RL_8169)
1451 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1452 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1454 device_printf(dev, "attaching PHYs failed\n");
1459 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1460 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1461 ifp->if_ioctl = re_ioctl;
1462 ifp->if_start = re_start;
1463 ifp->if_hwassist = RE_CSUM_FEATURES;
1464 ifp->if_capabilities = IFCAP_HWCSUM;
1465 ifp->if_capenable = ifp->if_capabilities;
1466 ifp->if_init = re_init;
1467 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1468 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1469 IFQ_SET_READY(&ifp->if_snd);
1471 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp);
1472 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1476 * Still have no idea how to make TSO work on 8168C, 8168CP,
1479 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
1480 ifp->if_hwassist |= CSUM_TSO;
1481 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
1485 * Call MI attach routine.
1487 ether_ifattach(ifp, eaddr);
1489 /* VLAN capability setup */
1490 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1491 if (ifp->if_capabilities & IFCAP_HWCSUM)
1492 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1493 /* Enable WOL if PM is supported. */
1494 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0)
1495 ifp->if_capabilities |= IFCAP_WOL;
1496 ifp->if_capenable = ifp->if_capabilities;
1498 * Don't enable TSO by default. Under certain
1499 * circumtances the controller generated corrupted
1500 * packets in TSO size.
1502 ifp->if_hwassist &= ~CSUM_TSO;
1503 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1504 #ifdef DEVICE_POLLING
1505 ifp->if_capabilities |= IFCAP_POLLING;
1508 * Tell the upper layer(s) we support long frames.
1509 * Must appear after the call to ether_ifattach() because
1510 * ether_ifattach() sets ifi_hdrlen to the default value.
1512 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1516 * Perform hardware diagnostic on the original RTL8169.
1517 * Some 32-bit cards were incorrectly wired and would
1518 * malfunction if plugged into a 64-bit slot.
1521 if (hwrev == RL_HWREV_8169) {
1522 error = re_diag(sc);
1525 "attach aborted due to hardware diag failure\n");
1526 ether_ifdetach(ifp);
1532 /* Hook interrupt last to avoid having to lock softc */
1533 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1534 error = bus_setup_intr(dev, sc->rl_irq[0],
1535 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1536 &sc->rl_intrhand[0]);
1538 for (i = 0; i < RL_MSI_MESSAGES; i++) {
1539 error = bus_setup_intr(dev, sc->rl_irq[i],
1540 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1541 &sc->rl_intrhand[i]);
1547 device_printf(dev, "couldn't set up irq\n");
1548 ether_ifdetach(ifp);
1560 * Shutdown hardware and free up resources. This can be called any
1561 * time after the mutex has been initialized. It is called in both
1562 * the error case in attach and the normal detach case so it needs
1563 * to be careful about only freeing resources that have actually been
1567 re_detach(device_t dev)
1569 struct rl_softc *sc;
1573 sc = device_get_softc(dev);
1575 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1577 /* These should only be active if attach succeeded */
1578 if (device_is_attached(dev)) {
1579 #ifdef DEVICE_POLLING
1580 if (ifp->if_capenable & IFCAP_POLLING)
1581 ether_poll_deregister(ifp);
1589 callout_drain(&sc->rl_stat_callout);
1590 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1591 taskqueue_drain(taskqueue_fast, &sc->rl_txtask);
1593 * Force off the IFF_UP flag here, in case someone
1594 * still had a BPF descriptor attached to this
1595 * interface. If they do, ether_ifdetach() will cause
1596 * the BPF code to try and clear the promisc mode
1597 * flag, which will bubble down to re_ioctl(),
1598 * which will try to call re_init() again. This will
1599 * turn the NIC back on and restart the MII ticker,
1600 * which will panic the system when the kernel tries
1601 * to invoke the re_tick() function that isn't there
1604 ifp->if_flags &= ~IFF_UP;
1605 ether_ifdetach(ifp);
1608 device_delete_child(dev, sc->rl_miibus);
1609 bus_generic_detach(dev);
1612 * The rest is resource deallocation, so we should already be
1616 for (i = 0; i < RL_MSI_MESSAGES; i++) {
1617 if (sc->rl_intrhand[i] != NULL) {
1618 bus_teardown_intr(dev, sc->rl_irq[i],
1619 sc->rl_intrhand[i]);
1620 sc->rl_intrhand[i] = NULL;
1625 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1626 if (sc->rl_irq[0] != NULL) {
1627 bus_release_resource(dev, SYS_RES_IRQ, 0,
1629 sc->rl_irq[0] = NULL;
1632 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1633 if (sc->rl_irq[i] != NULL) {
1634 bus_release_resource(dev, SYS_RES_IRQ, rid,
1636 sc->rl_irq[i] = NULL;
1639 pci_release_msi(dev);
1642 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1645 /* Unload and free the RX DMA ring memory and map */
1647 if (sc->rl_ldata.rl_rx_list_tag) {
1648 if (sc->rl_ldata.rl_rx_list_map)
1649 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1650 sc->rl_ldata.rl_rx_list_map);
1651 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list)
1652 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1653 sc->rl_ldata.rl_rx_list,
1654 sc->rl_ldata.rl_rx_list_map);
1655 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1658 /* Unload and free the TX DMA ring memory and map */
1660 if (sc->rl_ldata.rl_tx_list_tag) {
1661 if (sc->rl_ldata.rl_tx_list_map)
1662 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1663 sc->rl_ldata.rl_tx_list_map);
1664 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list)
1665 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1666 sc->rl_ldata.rl_tx_list,
1667 sc->rl_ldata.rl_tx_list_map);
1668 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1671 /* Destroy all the RX and TX buffer maps */
1673 if (sc->rl_ldata.rl_tx_mtag) {
1674 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
1675 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1676 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1677 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1679 if (sc->rl_ldata.rl_rx_mtag) {
1680 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++)
1681 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1682 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1683 if (sc->rl_ldata.rl_rx_sparemap)
1684 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1685 sc->rl_ldata.rl_rx_sparemap);
1686 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1689 /* Unload and free the stats buffer and map */
1691 if (sc->rl_ldata.rl_stag) {
1692 if (sc->rl_ldata.rl_smap)
1693 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1694 sc->rl_ldata.rl_smap);
1695 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats)
1696 bus_dmamem_free(sc->rl_ldata.rl_stag,
1697 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1698 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1701 if (sc->rl_parent_tag)
1702 bus_dma_tag_destroy(sc->rl_parent_tag);
1704 mtx_destroy(&sc->rl_mtx);
1709 static __inline void
1710 re_discard_rxbuf(struct rl_softc *sc, int idx)
1712 struct rl_desc *desc;
1713 struct rl_rxdesc *rxd;
1716 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1717 desc = &sc->rl_ldata.rl_rx_list[idx];
1718 desc->rl_vlanctl = 0;
1719 cmdstat = rxd->rx_size;
1720 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1721 cmdstat |= RL_RDESC_CMD_EOR;
1722 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1726 re_newbuf(struct rl_softc *sc, int idx)
1729 struct rl_rxdesc *rxd;
1730 bus_dma_segment_t segs[1];
1732 struct rl_desc *desc;
1736 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1740 m->m_len = m->m_pkthdr.len = MCLBYTES;
1743 * This is part of an evil trick to deal with non-x86 platforms.
1744 * The RealTek chip requires RX buffers to be aligned on 64-bit
1745 * boundaries, but that will hose non-x86 machines. To get around
1746 * this, we leave some empty space at the start of each buffer
1747 * and for non-x86 hosts, we copy the buffer back six bytes
1748 * to achieve word alignment. This is slightly more efficient
1749 * than allocating a new buffer, copying the contents, and
1750 * discarding the old buffer.
1752 m_adj(m, RE_ETHER_ALIGN);
1754 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1755 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1760 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1762 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1763 if (rxd->rx_m != NULL) {
1764 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1765 BUS_DMASYNC_POSTREAD);
1766 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1770 map = rxd->rx_dmamap;
1771 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1772 rxd->rx_size = segs[0].ds_len;
1773 sc->rl_ldata.rl_rx_sparemap = map;
1774 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1775 BUS_DMASYNC_PREREAD);
1777 desc = &sc->rl_ldata.rl_rx_list[idx];
1778 desc->rl_vlanctl = 0;
1779 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1780 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1781 cmdstat = segs[0].ds_len;
1782 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1783 cmdstat |= RL_RDESC_CMD_EOR;
1784 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1790 static __inline void
1791 re_fixup_rx(struct mbuf *m)
1794 uint16_t *src, *dst;
1796 src = mtod(m, uint16_t *);
1797 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1799 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1802 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1807 re_tx_list_init(struct rl_softc *sc)
1809 struct rl_desc *desc;
1814 bzero(sc->rl_ldata.rl_tx_list,
1815 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
1816 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
1817 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
1819 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
1820 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
1822 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1823 sc->rl_ldata.rl_tx_list_map,
1824 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1826 sc->rl_ldata.rl_tx_prodidx = 0;
1827 sc->rl_ldata.rl_tx_considx = 0;
1828 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
1834 re_rx_list_init(struct rl_softc *sc)
1838 bzero(sc->rl_ldata.rl_rx_list,
1839 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
1840 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1841 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
1842 if ((error = re_newbuf(sc, i)) != 0)
1846 /* Flush the RX descriptors */
1848 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1849 sc->rl_ldata.rl_rx_list_map,
1850 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1852 sc->rl_ldata.rl_rx_prodidx = 0;
1853 sc->rl_head = sc->rl_tail = NULL;
1859 * RX handler for C+ and 8169. For the gigE chips, we support
1860 * the reception of jumbo frames that have been fragmented
1861 * across multiple 2K mbuf cluster buffers.
1864 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
1869 struct rl_desc *cur_rx;
1870 u_int32_t rxstat, rxvlan;
1871 int maxpkt = 16, rx_npkts = 0;
1877 /* Invalidate the descriptor memory */
1879 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1880 sc->rl_ldata.rl_rx_list_map,
1881 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1883 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
1884 i = RL_RX_DESC_NXT(sc, i)) {
1885 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1887 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1888 rxstat = le32toh(cur_rx->rl_cmdstat);
1889 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
1891 total_len = rxstat & sc->rl_rxlenmask;
1892 rxvlan = le32toh(cur_rx->rl_vlanctl);
1893 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
1895 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1896 if (re_newbuf(sc, i) != 0) {
1898 * If this is part of a multi-fragment packet,
1899 * discard all the pieces.
1901 if (sc->rl_head != NULL) {
1902 m_freem(sc->rl_head);
1903 sc->rl_head = sc->rl_tail = NULL;
1905 re_discard_rxbuf(sc, i);
1908 m->m_len = RE_RX_DESC_BUFLEN;
1909 if (sc->rl_head == NULL)
1910 sc->rl_head = sc->rl_tail = m;
1912 m->m_flags &= ~M_PKTHDR;
1913 sc->rl_tail->m_next = m;
1920 * NOTE: for the 8139C+, the frame length field
1921 * is always 12 bits in size, but for the gigE chips,
1922 * it is 13 bits (since the max RX frame length is 16K).
1923 * Unfortunately, all 32 bits in the status word
1924 * were already used, so to make room for the extra
1925 * length bit, RealTek took out the 'frame alignment
1926 * error' bit and shifted the other status bits
1927 * over one slot. The OWN, EOR, FS and LS bits are
1928 * still in the same places. We have already extracted
1929 * the frame length and checked the OWN bit, so rather
1930 * than using an alternate bit mapping, we shift the
1931 * status bits one space to the right so we can evaluate
1932 * them using the 8169 status as though it was in the
1933 * same format as that of the 8139C+.
1935 if (sc->rl_type == RL_8169)
1939 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1940 * set, but if CRC is clear, it will still be a valid frame.
1942 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1943 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1946 * If this is part of a multi-fragment packet,
1947 * discard all the pieces.
1949 if (sc->rl_head != NULL) {
1950 m_freem(sc->rl_head);
1951 sc->rl_head = sc->rl_tail = NULL;
1953 re_discard_rxbuf(sc, i);
1958 * If allocating a replacement mbuf fails,
1959 * reload the current one.
1962 if (re_newbuf(sc, i) != 0) {
1964 if (sc->rl_head != NULL) {
1965 m_freem(sc->rl_head);
1966 sc->rl_head = sc->rl_tail = NULL;
1968 re_discard_rxbuf(sc, i);
1972 if (sc->rl_head != NULL) {
1973 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1975 m->m_len = RE_RX_DESC_BUFLEN;
1977 * Special case: if there's 4 bytes or less
1978 * in this buffer, the mbuf can be discarded:
1979 * the last 4 bytes is the CRC, which we don't
1980 * care about anyway.
1982 if (m->m_len <= ETHER_CRC_LEN) {
1983 sc->rl_tail->m_len -=
1984 (ETHER_CRC_LEN - m->m_len);
1987 m->m_len -= ETHER_CRC_LEN;
1988 m->m_flags &= ~M_PKTHDR;
1989 sc->rl_tail->m_next = m;
1992 sc->rl_head = sc->rl_tail = NULL;
1993 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1995 m->m_pkthdr.len = m->m_len =
1996 (total_len - ETHER_CRC_LEN);
2002 m->m_pkthdr.rcvif = ifp;
2004 /* Do RX checksumming if enabled */
2006 if (ifp->if_capenable & IFCAP_RXCSUM) {
2007 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2008 /* Check IP header checksum */
2009 if (rxstat & RL_RDESC_STAT_PROTOID)
2010 m->m_pkthdr.csum_flags |=
2012 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2013 m->m_pkthdr.csum_flags |=
2016 /* Check TCP/UDP checksum */
2017 if ((RL_TCPPKT(rxstat) &&
2018 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2019 (RL_UDPPKT(rxstat) &&
2020 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2021 m->m_pkthdr.csum_flags |=
2022 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2023 m->m_pkthdr.csum_data = 0xffff;
2027 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2029 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2030 (rxvlan & RL_RDESC_IPV4))
2031 m->m_pkthdr.csum_flags |=
2033 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2034 (rxvlan & RL_RDESC_IPV4))
2035 m->m_pkthdr.csum_flags |=
2037 if (((rxstat & RL_RDESC_STAT_TCP) &&
2038 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2039 ((rxstat & RL_RDESC_STAT_UDP) &&
2040 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2041 m->m_pkthdr.csum_flags |=
2042 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2043 m->m_pkthdr.csum_data = 0xffff;
2048 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
2049 m->m_pkthdr.ether_vtag =
2050 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
2051 m->m_flags |= M_VLANTAG;
2054 (*ifp->if_input)(ifp, m);
2059 /* Flush the RX DMA ring */
2061 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2062 sc->rl_ldata.rl_rx_list_map,
2063 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2065 sc->rl_ldata.rl_rx_prodidx = i;
2067 if (rx_npktsp != NULL)
2068 *rx_npktsp = rx_npkts;
2076 re_txeof(struct rl_softc *sc)
2079 struct rl_txdesc *txd;
2083 cons = sc->rl_ldata.rl_tx_considx;
2084 if (cons == sc->rl_ldata.rl_tx_prodidx)
2088 /* Invalidate the TX descriptor list */
2089 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2090 sc->rl_ldata.rl_tx_list_map,
2091 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2093 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2094 cons = RL_TX_DESC_NXT(sc, cons)) {
2095 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2096 if (txstat & RL_TDESC_STAT_OWN)
2099 * We only stash mbufs in the last descriptor
2100 * in a fragment chain, which also happens to
2101 * be the only place where the TX status bits
2104 if (txstat & RL_TDESC_CMD_EOF) {
2105 txd = &sc->rl_ldata.rl_tx_desc[cons];
2106 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2107 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2108 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2110 KASSERT(txd->tx_m != NULL,
2111 ("%s: freeing NULL mbufs!", __func__));
2114 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2115 RL_TDESC_STAT_COLCNT))
2116 ifp->if_collisions++;
2117 if (txstat & RL_TDESC_STAT_TXERRSUM)
2122 sc->rl_ldata.rl_tx_free++;
2123 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2125 sc->rl_ldata.rl_tx_considx = cons;
2127 /* No changes made to the TX ring, so no flush needed */
2129 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2130 #ifdef RE_TX_MODERATION
2132 * If not all descriptors have been reaped yet, reload
2133 * the timer so that we will eventually get another
2134 * interrupt that will cause us to re-enter this routine.
2135 * This is done in case the transmitter has gone idle.
2137 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2140 sc->rl_watchdog_timer = 0;
2146 struct rl_softc *sc;
2147 struct mii_data *mii;
2153 mii = device_get_softc(sc->rl_miibus);
2155 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2156 re_miibus_statchg(sc->rl_dev);
2158 * Reclaim transmitted frames here. Technically it is not
2159 * necessary to do here but it ensures periodic reclamation
2160 * regardless of Tx completion interrupt which seems to be
2161 * lost on PCIe based controllers under certain situations.
2165 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2168 #ifdef DEVICE_POLLING
2170 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2172 struct rl_softc *sc = ifp->if_softc;
2176 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2177 rx_npkts = re_poll_locked(ifp, cmd, count);
2183 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2185 struct rl_softc *sc = ifp->if_softc;
2190 sc->rxcycles = count;
2191 re_rxeof(sc, &rx_npkts);
2194 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2195 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
2197 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2200 status = CSR_READ_2(sc, RL_ISR);
2201 if (status == 0xffff)
2204 CSR_WRITE_2(sc, RL_ISR, status);
2205 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2206 (sc->rl_flags & RL_FLAG_PCIE))
2207 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2210 * XXX check behaviour on receiver stalls.
2213 if (status & RL_ISR_SYSTEM_ERR) {
2214 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2220 #endif /* DEVICE_POLLING */
2225 struct rl_softc *sc;
2230 status = CSR_READ_2(sc, RL_ISR);
2231 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2232 return (FILTER_STRAY);
2233 CSR_WRITE_2(sc, RL_IMR, 0);
2235 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2237 return (FILTER_HANDLED);
2241 re_int_task(void *arg, int npending)
2243 struct rl_softc *sc;
2253 status = CSR_READ_2(sc, RL_ISR);
2254 CSR_WRITE_2(sc, RL_ISR, status);
2256 if (sc->suspended ||
2257 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2262 #ifdef DEVICE_POLLING
2263 if (ifp->if_capenable & IFCAP_POLLING) {
2269 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2270 rval = re_rxeof(sc, NULL);
2273 * Some chips will ignore a second TX request issued
2274 * while an existing transmission is in progress. If
2275 * the transmitter goes idle but there are still
2276 * packets waiting to be sent, we need to restart the
2277 * channel here to flush them out. This only seems to
2278 * be required with the PCIe devices.
2280 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2281 (sc->rl_flags & RL_FLAG_PCIE))
2282 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2284 #ifdef RE_TX_MODERATION
2285 RL_ISR_TIMEOUT_EXPIRED|
2289 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2292 if (status & RL_ISR_SYSTEM_ERR) {
2293 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2297 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2298 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
2302 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2303 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2307 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2311 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2313 struct rl_txdesc *txd, *txd_last;
2314 bus_dma_segment_t segs[RL_NTXSEGS];
2317 struct rl_desc *desc;
2319 int i, error, ei, si;
2321 uint32_t cmdstat, csum_flags, vlanctl;
2324 M_ASSERTPKTHDR((*m_head));
2327 * With some of the RealTek chips, using the checksum offload
2328 * support in conjunction with the autopadding feature results
2329 * in the transmission of corrupt frames. For example, if we
2330 * need to send a really small IP fragment that's less than 60
2331 * bytes in size, and IP header checksumming is enabled, the
2332 * resulting ethernet frame that appears on the wire will
2333 * have garbled payload. To work around this, if TX IP checksum
2334 * offload is enabled, we always manually pad short frames out
2335 * to the minimum ethernet frame size.
2337 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2338 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2339 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2340 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2341 if (M_WRITABLE(*m_head) == 0) {
2342 /* Get a writable copy. */
2343 m_new = m_dup(*m_head, M_DONTWAIT);
2345 if (m_new == NULL) {
2351 if ((*m_head)->m_next != NULL ||
2352 M_TRAILINGSPACE(*m_head) < padlen) {
2353 m_new = m_defrag(*m_head, M_DONTWAIT);
2354 if (m_new == NULL) {
2363 * Manually pad short frames, and zero the pad space
2364 * to avoid leaking data.
2366 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2367 m_new->m_pkthdr.len += padlen;
2368 m_new->m_len = m_new->m_pkthdr.len;
2372 prod = sc->rl_ldata.rl_tx_prodidx;
2373 txd = &sc->rl_ldata.rl_tx_desc[prod];
2374 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2375 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2376 if (error == EFBIG) {
2377 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS);
2378 if (m_new == NULL) {
2384 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2385 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2391 } else if (error != 0)
2399 /* Check for number of available descriptors. */
2400 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2401 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2405 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2406 BUS_DMASYNC_PREWRITE);
2409 * Set up checksum offload. Note: checksum offload bits must
2410 * appear in all descriptors of a multi-descriptor transmit
2411 * attempt. This is according to testing done with an 8169
2412 * chip. This is a requirement.
2416 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0)
2417 csum_flags = RL_TDESC_CMD_LGSEND |
2418 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2419 RL_TDESC_CMD_MSSVAL_SHIFT);
2422 * Unconditionally enable IP checksum if TCP or UDP
2423 * checksum is required. Otherwise, TCP/UDP checksum
2424 * does't make effects.
2426 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2427 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2428 csum_flags |= RL_TDESC_CMD_IPCSUM;
2429 if (((*m_head)->m_pkthdr.csum_flags &
2431 csum_flags |= RL_TDESC_CMD_TCPCSUM;
2432 if (((*m_head)->m_pkthdr.csum_flags &
2434 csum_flags |= RL_TDESC_CMD_UDPCSUM;
2436 vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2437 if (((*m_head)->m_pkthdr.csum_flags &
2439 vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2440 if (((*m_head)->m_pkthdr.csum_flags &
2442 vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2448 * Set up hardware VLAN tagging. Note: vlan tag info must
2449 * appear in all descriptors of a multi-descriptor
2450 * transmission attempt.
2452 if ((*m_head)->m_flags & M_VLANTAG)
2453 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2454 RL_TDESC_VLANCTL_TAG;
2457 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2458 desc = &sc->rl_ldata.rl_tx_list[prod];
2459 desc->rl_vlanctl = htole32(vlanctl);
2460 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2461 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2462 cmdstat = segs[i].ds_len;
2464 cmdstat |= RL_TDESC_CMD_OWN;
2465 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2466 cmdstat |= RL_TDESC_CMD_EOR;
2467 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2468 sc->rl_ldata.rl_tx_free--;
2470 /* Update producer index. */
2471 sc->rl_ldata.rl_tx_prodidx = prod;
2473 /* Set EOF on the last descriptor. */
2474 ei = RL_TX_DESC_PRV(sc, prod);
2475 desc = &sc->rl_ldata.rl_tx_list[ei];
2476 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2478 desc = &sc->rl_ldata.rl_tx_list[si];
2479 /* Set SOF and transfer ownership of packet to the chip. */
2480 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2483 * Insure that the map for this transmission
2484 * is placed at the array index of the last descriptor
2485 * in this chain. (Swap last and first dmamaps.)
2487 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2488 map = txd->tx_dmamap;
2489 txd->tx_dmamap = txd_last->tx_dmamap;
2490 txd_last->tx_dmamap = map;
2491 txd_last->tx_m = *m_head;
2497 re_tx_task(void *arg, int npending)
2506 * Main transmit routine for C+ and gigE NICs.
2509 re_start(struct ifnet *ifp)
2511 struct rl_softc *sc;
2512 struct mbuf *m_head;
2519 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2520 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) {
2525 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2526 sc->rl_ldata.rl_tx_free > 1;) {
2527 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2531 if (re_encap(sc, &m_head) != 0) {
2534 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2535 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2540 * If there's a BPF listener, bounce a copy of this frame
2543 ETHER_BPF_MTAP(ifp, m_head);
2549 #ifdef RE_TX_MODERATION
2550 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2551 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2557 /* Flush the TX descriptors */
2559 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2560 sc->rl_ldata.rl_tx_list_map,
2561 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2563 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2565 #ifdef RE_TX_MODERATION
2567 * Use the countdown timer for interrupt moderation.
2568 * 'TX done' interrupts are disabled. Instead, we reset the
2569 * countdown timer, which will begin counting until it hits
2570 * the value in the TIMERINT register, and then trigger an
2571 * interrupt. Each time we write to the TIMERCNT register,
2572 * the timer count is reset to 0.
2574 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2578 * Set a timeout in case the chip goes out to lunch.
2580 sc->rl_watchdog_timer = 5;
2588 struct rl_softc *sc = xsc;
2596 re_init_locked(struct rl_softc *sc)
2598 struct ifnet *ifp = sc->rl_ifp;
2599 struct mii_data *mii;
2603 uint32_t align_dummy;
2604 u_char eaddr[ETHER_ADDR_LEN];
2609 mii = device_get_softc(sc->rl_miibus);
2611 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2615 * Cancel pending I/O and free all RX/TX buffers.
2619 /* Put controller into known state. */
2623 * Enable C+ RX and TX mode, as well as VLAN stripping and
2624 * RX checksum offload. We must configure the C+ register
2625 * before all others.
2627 cfg = RL_CPLUSCMD_PCI_MRW;
2628 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2629 cfg |= RL_CPLUSCMD_RXCSUM_ENB;
2630 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2631 cfg |= RL_CPLUSCMD_VLANSTRIP;
2632 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
2633 cfg |= RL_CPLUSCMD_MACSTAT_DIS;
2637 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
2638 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
2639 if (sc->rl_hwrev == RL_HWREV_8169_8110SC ||
2640 sc->rl_hwrev == RL_HWREV_8169_8110SCE) {
2642 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0)
2644 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE)
2646 CSR_WRITE_4(sc, 0x7c, reg);
2647 /* Disable interrupt mitigation. */
2648 CSR_WRITE_2(sc, 0xe2, 0);
2651 * Disable TSO if interface MTU size is greater than MSS
2652 * allowed in controller.
2654 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
2655 ifp->if_capenable &= ~IFCAP_TSO4;
2656 ifp->if_hwassist &= ~CSUM_TSO;
2660 * Init our MAC address. Even though the chipset
2661 * documentation doesn't mention it, we need to enter "Config
2662 * register write enable" mode to modify the ID registers.
2664 /* Copy MAC address on stack to align. */
2665 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
2666 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2667 CSR_WRITE_4(sc, RL_IDR0,
2668 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
2669 CSR_WRITE_4(sc, RL_IDR4,
2670 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
2671 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2674 * For C+ mode, initialize the RX descriptors and mbufs.
2676 re_rx_list_init(sc);
2677 re_tx_list_init(sc);
2680 * Load the addresses of the RX and TX lists into the chip.
2683 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2684 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2685 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2686 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2688 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2689 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2690 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2691 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2694 * Enable transmit and receive.
2696 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2699 * Set the initial TX configuration.
2701 if (sc->rl_testmode) {
2702 if (sc->rl_type == RL_8169)
2703 CSR_WRITE_4(sc, RL_TXCFG,
2704 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2706 CSR_WRITE_4(sc, RL_TXCFG,
2707 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2709 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2711 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2714 * Set the initial RX configuration.
2718 /* Configure interrupt moderation. */
2719 if (sc->rl_type == RL_8169) {
2720 switch (sc->rl_hwrev) {
2721 case RL_HWREV_8100E:
2722 case RL_HWREV_8101E:
2723 case RL_HWREV_8102E:
2724 case RL_HWREV_8102EL:
2725 case RL_HWREV_8102EL_SPIN1:
2726 case RL_HWREV_8103E:
2727 CSR_WRITE_2(sc, RL_INTRMOD, 0);
2730 /* Magic from vendor. */
2731 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
2736 #ifdef DEVICE_POLLING
2738 * Disable interrupts if we are polling.
2740 if (ifp->if_capenable & IFCAP_POLLING)
2741 CSR_WRITE_2(sc, RL_IMR, 0);
2742 else /* otherwise ... */
2746 * Enable interrupts.
2748 if (sc->rl_testmode)
2749 CSR_WRITE_2(sc, RL_IMR, 0);
2751 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2752 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
2754 /* Set initial TX threshold */
2755 sc->rl_txthresh = RL_TX_THRESH_INIT;
2757 /* Start RX/TX process. */
2758 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2760 /* Enable receiver and transmitter. */
2761 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2764 #ifdef RE_TX_MODERATION
2766 * Initialize the timer interrupt register so that
2767 * a timer interrupt will be generated once the timer
2768 * reaches a certain number of ticks. The timer is
2769 * reloaded on each transmit. This gives us TX interrupt
2770 * moderation, which dramatically improves TX frame rate.
2772 if (sc->rl_type == RL_8169)
2773 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2775 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2779 * For 8169 gigE NICs, set the max allowed RX packet
2780 * size so we can receive jumbo frames.
2782 if (sc->rl_type == RL_8169) {
2783 if ((sc->rl_flags & (RL_FLAG_PCIE | RL_FLAG_NOJUMBO)) ==
2784 (RL_FLAG_PCIE | RL_FLAG_NOJUMBO))
2785 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
2787 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2790 if (sc->rl_testmode)
2795 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
2797 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2798 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2800 sc->rl_flags &= ~RL_FLAG_LINK;
2801 sc->rl_watchdog_timer = 0;
2802 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2806 * Set media options.
2809 re_ifmedia_upd(struct ifnet *ifp)
2811 struct rl_softc *sc;
2812 struct mii_data *mii;
2816 mii = device_get_softc(sc->rl_miibus);
2818 error = mii_mediachg(mii);
2825 * Report current media status.
2828 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2830 struct rl_softc *sc;
2831 struct mii_data *mii;
2834 mii = device_get_softc(sc->rl_miibus);
2839 ifmr->ifm_active = mii->mii_media_active;
2840 ifmr->ifm_status = mii->mii_media_status;
2844 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2846 struct rl_softc *sc = ifp->if_softc;
2847 struct ifreq *ifr = (struct ifreq *) data;
2848 struct mii_data *mii;
2853 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) {
2857 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 &&
2858 ifr->ifr_mtu > RL_MAX_FRAMELEN) {
2863 if (ifp->if_mtu != ifr->ifr_mtu)
2864 ifp->if_mtu = ifr->ifr_mtu;
2865 if (ifp->if_mtu > RL_TSO_MTU &&
2866 (ifp->if_capenable & IFCAP_TSO4) != 0) {
2867 ifp->if_capenable &= ~IFCAP_TSO4;
2868 ifp->if_hwassist &= ~CSUM_TSO;
2869 VLAN_CAPABILITIES(ifp);
2875 if ((ifp->if_flags & IFF_UP) != 0) {
2876 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2877 if (((ifp->if_flags ^ sc->rl_if_flags)
2878 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2883 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2886 sc->rl_if_flags = ifp->if_flags;
2892 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2898 mii = device_get_softc(sc->rl_miibus);
2899 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2905 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2907 #ifdef DEVICE_POLLING
2908 if (mask & IFCAP_POLLING) {
2909 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2910 error = ether_poll_register(re_poll, ifp);
2914 /* Disable interrupts */
2915 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2916 ifp->if_capenable |= IFCAP_POLLING;
2919 error = ether_poll_deregister(ifp);
2920 /* Enable interrupts. */
2922 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2923 ifp->if_capenable &= ~IFCAP_POLLING;
2927 #endif /* DEVICE_POLLING */
2928 if (mask & IFCAP_HWCSUM) {
2929 ifp->if_capenable ^= IFCAP_HWCSUM;
2930 if (ifp->if_capenable & IFCAP_TXCSUM)
2931 ifp->if_hwassist |= RE_CSUM_FEATURES;
2933 ifp->if_hwassist &= ~RE_CSUM_FEATURES;
2936 if ((mask & IFCAP_TSO4) != 0 &&
2937 (ifp->if_capabilities & IFCAP_TSO) != 0) {
2938 ifp->if_capenable ^= IFCAP_TSO4;
2939 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
2940 ifp->if_hwassist |= CSUM_TSO;
2942 ifp->if_hwassist &= ~CSUM_TSO;
2943 if (ifp->if_mtu > RL_TSO_MTU &&
2944 (ifp->if_capenable & IFCAP_TSO4) != 0) {
2945 ifp->if_capenable &= ~IFCAP_TSO4;
2946 ifp->if_hwassist &= ~CSUM_TSO;
2949 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2950 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2951 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2952 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2953 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2954 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2955 /* TSO over VLAN requires VLAN hardware tagging. */
2956 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2957 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
2960 if ((mask & IFCAP_WOL) != 0 &&
2961 (ifp->if_capabilities & IFCAP_WOL) != 0) {
2962 if ((mask & IFCAP_WOL_UCAST) != 0)
2963 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2964 if ((mask & IFCAP_WOL_MCAST) != 0)
2965 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2966 if ((mask & IFCAP_WOL_MAGIC) != 0)
2967 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2969 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
2970 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2973 VLAN_CAPABILITIES(ifp);
2977 error = ether_ioctl(ifp, command, data);
2985 re_watchdog(struct rl_softc *sc)
2991 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
2996 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
2997 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
2999 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3000 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
3004 if_printf(ifp, "watchdog timeout\n");
3008 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3010 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3011 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
3015 * Stop the adapter and free any mbufs allocated to the
3019 re_stop(struct rl_softc *sc)
3023 struct rl_txdesc *txd;
3024 struct rl_rxdesc *rxd;
3030 sc->rl_watchdog_timer = 0;
3031 callout_stop(&sc->rl_stat_callout);
3032 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3034 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0)
3035 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3038 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3040 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3041 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3043 if (sc->rl_head != NULL) {
3044 m_freem(sc->rl_head);
3045 sc->rl_head = sc->rl_tail = NULL;
3048 /* Free the TX list buffers. */
3050 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3051 txd = &sc->rl_ldata.rl_tx_desc[i];
3052 if (txd->tx_m != NULL) {
3053 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3054 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3055 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3062 /* Free the RX list buffers. */
3064 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3065 rxd = &sc->rl_ldata.rl_rx_desc[i];
3066 if (rxd->rx_m != NULL) {
3067 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3068 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3069 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3078 * Device suspend routine. Stop the interface and save some PCI
3079 * settings in case the BIOS doesn't restore them properly on
3083 re_suspend(device_t dev)
3085 struct rl_softc *sc;
3087 sc = device_get_softc(dev);
3099 * Device resume routine. Restore some PCI settings in case the BIOS
3100 * doesn't, re-enable busmastering, and restart the interface if
3104 re_resume(device_t dev)
3106 struct rl_softc *sc;
3109 sc = device_get_softc(dev);
3114 /* Take controller out of sleep mode. */
3115 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3116 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3117 CSR_WRITE_1(sc, RL_GPIO,
3118 CSR_READ_1(sc, RL_GPIO) | 0x01);
3122 * Clear WOL matching such that normal Rx filtering
3123 * wouldn't interfere with WOL patterns.
3127 /* reinitialize interface if necessary */
3128 if (ifp->if_flags & IFF_UP)
3138 * Stop all chip I/O so that the kernel's probe routines don't
3139 * get confused by errant DMAs when rebooting.
3142 re_shutdown(device_t dev)
3144 struct rl_softc *sc;
3146 sc = device_get_softc(dev);
3151 * Mark interface as down since otherwise we will panic if
3152 * interrupt comes in later on, which can happen in some
3155 sc->rl_ifp->if_flags &= ~IFF_UP;
3163 re_setwol(struct rl_softc *sc)
3172 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3176 /* Put controller into sleep mode. */
3177 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3178 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3179 CSR_WRITE_1(sc, RL_GPIO,
3180 CSR_READ_1(sc, RL_GPIO) & ~0x01);
3182 if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
3183 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3184 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3185 /* Enable config register write. */
3186 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3189 v = CSR_READ_1(sc, RL_CFG1);
3191 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3193 CSR_WRITE_1(sc, RL_CFG1, v);
3195 v = CSR_READ_1(sc, RL_CFG3);
3196 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3197 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3198 v |= RL_CFG3_WOL_MAGIC;
3199 CSR_WRITE_1(sc, RL_CFG3, v);
3201 /* Config register write done. */
3202 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3204 v = CSR_READ_1(sc, RL_CFG5);
3205 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3206 v &= ~RL_CFG5_WOL_LANWAKE;
3207 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3208 v |= RL_CFG5_WOL_UCAST;
3209 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3210 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3211 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3212 v |= RL_CFG5_WOL_LANWAKE;
3213 CSR_WRITE_1(sc, RL_CFG5, v);
3215 if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
3216 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3217 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3219 * It seems that hardware resets its link speed to 100Mbps in
3220 * power down mode so switching to 100Mbps in driver is not
3224 /* Request PME if WOL is requested. */
3225 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3226 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3227 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3228 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3229 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3233 re_clrwol(struct rl_softc *sc)
3240 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3243 /* Enable config register write. */
3244 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3246 v = CSR_READ_1(sc, RL_CFG3);
3247 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3248 CSR_WRITE_1(sc, RL_CFG3, v);
3250 /* Config register write done. */
3251 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3253 v = CSR_READ_1(sc, RL_CFG5);
3254 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3255 v &= ~RL_CFG5_WOL_LANWAKE;
3256 CSR_WRITE_1(sc, RL_CFG5, v);
3260 re_add_sysctls(struct rl_softc *sc)
3262 struct sysctl_ctx_list *ctx;
3263 struct sysctl_oid_list *children;
3265 ctx = device_get_sysctl_ctx(sc->rl_dev);
3266 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3268 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
3269 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
3270 "Statistics Information");
3274 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
3276 struct rl_softc *sc;
3277 struct rl_stats *stats;
3278 int error, i, result;
3281 error = sysctl_handle_int(oidp, &result, 0, req);
3282 if (error || req->newptr == NULL)
3286 sc = (struct rl_softc *)arg1;
3288 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3289 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
3290 CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
3291 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
3292 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3293 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
3294 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3295 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
3296 RL_DUMPSTATS_START));
3297 for (i = RL_TIMEOUT; i > 0; i--) {
3298 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
3299 RL_DUMPSTATS_START) == 0)
3303 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3304 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
3307 device_printf(sc->rl_dev,
3308 "DUMP statistics request timedout\n");
3311 stats = sc->rl_ldata.rl_stats;
3312 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
3313 printf("Tx frames : %ju\n",
3314 (uintmax_t)le64toh(stats->rl_tx_pkts));
3315 printf("Rx frames : %ju\n",
3316 (uintmax_t)le64toh(stats->rl_rx_pkts));
3317 printf("Tx errors : %ju\n",
3318 (uintmax_t)le64toh(stats->rl_tx_errs));
3319 printf("Rx errors : %u\n",
3320 le32toh(stats->rl_rx_errs));
3321 printf("Rx missed frames : %u\n",
3322 (uint32_t)le16toh(stats->rl_missed_pkts));
3323 printf("Rx frame alignment errs : %u\n",
3324 (uint32_t)le16toh(stats->rl_rx_framealign_errs));
3325 printf("Tx single collisions : %u\n",
3326 le32toh(stats->rl_tx_onecoll));
3327 printf("Tx multiple collisions : %u\n",
3328 le32toh(stats->rl_tx_multicolls));
3329 printf("Rx unicast frames : %ju\n",
3330 (uintmax_t)le64toh(stats->rl_rx_ucasts));
3331 printf("Rx broadcast frames : %ju\n",
3332 (uintmax_t)le64toh(stats->rl_rx_bcasts));
3333 printf("Rx multicast frames : %u\n",
3334 le32toh(stats->rl_rx_mcasts));
3335 printf("Tx aborts : %u\n",
3336 (uint32_t)le16toh(stats->rl_tx_aborts));
3337 printf("Tx underruns : %u\n",
3338 (uint32_t)le16toh(stats->rl_rx_underruns));