2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <sys/sysctl.h>
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
51 #include <machine/apicreg.h>
52 #include <machine/frame.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/apicvar.h>
55 #include <machine/resource.h>
56 #include <machine/segments.h>
58 #define IOAPIC_ISA_INTS 16
59 #define IOAPIC_MEM_REGION 32
60 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
61 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
63 #define IRQ_EXTINT (NUM_IO_INTS + 1)
64 #define IRQ_NMI (NUM_IO_INTS + 2)
65 #define IRQ_SMI (NUM_IO_INTS + 3)
66 #define IRQ_DISABLED (NUM_IO_INTS + 4)
68 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
71 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
72 * as laid out in the ACPI System Interrupt number model where each I/O
73 * APIC has a contiguous chunk of the System Interrupt address space.
74 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
75 * IRQs behave as PCI IRQs by default. We also assume that the pin for
76 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
77 * configuration of individual pins as indicated by their tables.
79 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
80 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
81 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
84 struct ioapic_intsrc {
85 struct intsrc io_intsrc;
91 u_int io_edgetrigger:1;
99 u_int io_id:8; /* logical ID */
101 u_int io_intbase:8; /* System Interrupt base */
103 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
105 STAILQ_ENTRY(ioapic) io_next;
106 struct ioapic_intsrc io_pins[0];
109 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
110 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
111 static const char *ioapic_bus_string(int bus_type);
112 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
113 static void ioapic_enable_source(struct intsrc *isrc);
114 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
115 static void ioapic_eoi_source(struct intsrc *isrc);
116 static void ioapic_enable_intr(struct intsrc *isrc);
117 static void ioapic_disable_intr(struct intsrc *isrc);
118 static int ioapic_vector(struct intsrc *isrc);
119 static int ioapic_source_pending(struct intsrc *isrc);
120 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
121 enum intr_polarity pol);
122 static void ioapic_resume(struct pic *pic);
123 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
124 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
126 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
127 struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
128 ioapic_eoi_source, ioapic_enable_intr,
129 ioapic_disable_intr, ioapic_vector,
130 ioapic_source_pending, NULL, ioapic_resume,
131 ioapic_config_intr, ioapic_assign_cpu };
133 static int next_ioapic_base;
134 static u_int next_id;
136 SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options");
137 static int enable_extint;
138 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
139 "Enable the ExtINT pin in the first I/O APIC");
140 TUNABLE_INT("hw.apic.enable_extint", &enable_extint);
143 _ioapic_eoi_source(struct intsrc *isrc)
149 ioapic_read(volatile ioapic_t *apic, int reg)
152 mtx_assert(&icu_lock, MA_OWNED);
153 apic->ioregsel = reg;
154 return (apic->iowin);
158 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
161 mtx_assert(&icu_lock, MA_OWNED);
162 apic->ioregsel = reg;
167 ioapic_bus_string(int bus_type)
183 ioapic_print_irq(struct ioapic_intsrc *intpin)
186 switch (intpin->io_irq) {
200 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
206 ioapic_enable_source(struct intsrc *isrc)
208 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
209 struct ioapic *io = (struct ioapic *)isrc->is_pic;
212 mtx_lock_spin(&icu_lock);
213 if (intpin->io_masked) {
214 flags = intpin->io_lowreg & ~IOART_INTMASK;
215 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
217 intpin->io_masked = 0;
219 mtx_unlock_spin(&icu_lock);
223 ioapic_disable_source(struct intsrc *isrc, int eoi)
225 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
226 struct ioapic *io = (struct ioapic *)isrc->is_pic;
229 mtx_lock_spin(&icu_lock);
230 if (!intpin->io_masked && !intpin->io_edgetrigger) {
231 flags = intpin->io_lowreg | IOART_INTMSET;
232 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
234 intpin->io_masked = 1;
238 _ioapic_eoi_source(isrc);
240 mtx_unlock_spin(&icu_lock);
244 ioapic_eoi_source(struct intsrc *isrc)
247 _ioapic_eoi_source(isrc);
251 * Completely program an intpin based on the data in its interrupt source
255 ioapic_program_intpin(struct ioapic_intsrc *intpin)
257 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
258 uint32_t low, high, value;
261 * If a pin is completely invalid or if it is valid but hasn't
262 * been enabled yet, just ensure that the pin is masked.
264 mtx_assert(&icu_lock, MA_OWNED);
265 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS &&
266 intpin->io_vector == 0)) {
267 low = ioapic_read(io->io_addr,
268 IOAPIC_REDTBL_LO(intpin->io_intpin));
269 if ((low & IOART_INTMASK) == IOART_INTMCLR)
270 ioapic_write(io->io_addr,
271 IOAPIC_REDTBL_LO(intpin->io_intpin),
272 low | IOART_INTMSET);
276 /* Set the destination. */
278 high = intpin->io_cpu << APIC_ID_SHIFT;
280 /* Program the rest of the low word. */
281 if (intpin->io_edgetrigger)
282 low |= IOART_TRGREDG;
284 low |= IOART_TRGRLVL;
285 if (intpin->io_activehi)
289 if (intpin->io_masked)
290 low |= IOART_INTMSET;
291 switch (intpin->io_irq) {
293 KASSERT(intpin->io_edgetrigger,
294 ("ExtINT not edge triggered"));
295 low |= IOART_DELEXINT;
298 KASSERT(intpin->io_edgetrigger,
299 ("NMI not edge triggered"));
303 KASSERT(intpin->io_edgetrigger,
304 ("SMI not edge triggered"));
308 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
310 low |= IOART_DELFIXED | intpin->io_vector;
313 /* Write the values to the APIC. */
314 intpin->io_lowreg = low;
315 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
316 value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
317 value &= ~IOART_DEST;
319 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
323 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
325 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
326 struct ioapic *io = (struct ioapic *)isrc->is_pic;
327 u_int old_vector, new_vector;
331 * keep 1st core as the destination for NMI
333 if (intpin->io_irq == IRQ_NMI)
337 * Set us up to free the old irq.
339 old_vector = intpin->io_vector;
340 old_id = intpin->io_cpu;
341 if (old_vector && apic_id == old_id)
345 * Allocate an APIC vector for this interrupt pin. Once
346 * we have a vector we program the interrupt pin.
348 new_vector = apic_alloc_vector(apic_id, intpin->io_irq);
353 * Mask the old intpin if it is enabled while it is migrated.
355 * At least some level-triggered interrupts seem to need the
356 * extra DELAY() to avoid being stuck in a non-EOI'd state.
358 mtx_lock_spin(&icu_lock);
359 if (!intpin->io_masked && !intpin->io_edgetrigger) {
360 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
361 intpin->io_lowreg | IOART_INTMSET);
365 intpin->io_cpu = apic_id;
366 intpin->io_vector = new_vector;
367 if (isrc->is_handlers > 0)
368 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
370 printf("ioapic%u: routing intpin %u (", io->io_id,
372 ioapic_print_irq(intpin);
373 printf(") to lapic %u vector %u\n", intpin->io_cpu,
376 ioapic_program_intpin(intpin);
377 mtx_unlock_spin(&icu_lock);
380 * Free the old vector after the new one is established. This is done
381 * to prevent races where we could miss an interrupt.
384 if (isrc->is_handlers > 0)
385 apic_disable_vector(old_id, old_vector);
386 apic_free_vector(old_id, old_vector, intpin->io_irq);
392 ioapic_enable_intr(struct intsrc *isrc)
394 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
396 if (intpin->io_vector == 0)
397 if (ioapic_assign_cpu(isrc, intr_next_cpu()) != 0)
398 panic("Couldn't find an APIC vector for IRQ %d",
400 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
405 ioapic_disable_intr(struct intsrc *isrc)
407 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
410 if (intpin->io_vector != 0) {
411 /* Mask this interrupt pin and free its APIC vector. */
412 vector = intpin->io_vector;
413 apic_disable_vector(intpin->io_cpu, vector);
414 mtx_lock_spin(&icu_lock);
415 intpin->io_masked = 1;
416 intpin->io_vector = 0;
417 ioapic_program_intpin(intpin);
418 mtx_unlock_spin(&icu_lock);
419 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq);
424 ioapic_vector(struct intsrc *isrc)
426 struct ioapic_intsrc *pin;
428 pin = (struct ioapic_intsrc *)isrc;
429 return (pin->io_irq);
433 ioapic_source_pending(struct intsrc *isrc)
435 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
437 if (intpin->io_vector == 0)
439 return (lapic_intr_pending(intpin->io_vector));
443 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
444 enum intr_polarity pol)
446 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
447 struct ioapic *io = (struct ioapic *)isrc->is_pic;
450 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
451 ("%s: Conforming trigger or polarity\n", __func__));
454 * EISA interrupts always use active high polarity, so don't allow
455 * them to be set to active low.
457 * XXX: Should we write to the ELCR if the trigger mode changes for
458 * an EISA IRQ or an ISA IRQ with the ELCR present?
460 mtx_lock_spin(&icu_lock);
461 if (intpin->io_bus == APIC_BUS_EISA)
462 pol = INTR_POLARITY_HIGH;
464 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
466 printf("ioapic%u: Changing trigger for pin %u to %s\n",
467 io->io_id, intpin->io_intpin,
468 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
469 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
472 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
474 printf("ioapic%u: Changing polarity for pin %u to %s\n",
475 io->io_id, intpin->io_intpin,
476 pol == INTR_POLARITY_HIGH ? "high" : "low");
477 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
481 ioapic_program_intpin(intpin);
482 mtx_unlock_spin(&icu_lock);
487 ioapic_resume(struct pic *pic)
489 struct ioapic *io = (struct ioapic *)pic;
492 mtx_lock_spin(&icu_lock);
493 for (i = 0; i < io->io_numintr; i++)
494 ioapic_program_intpin(&io->io_pins[i]);
495 mtx_unlock_spin(&icu_lock);
499 * Create a plain I/O APIC object.
502 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
505 struct ioapic_intsrc *intpin;
506 volatile ioapic_t *apic;
510 /* Map the register window so we can access the device. */
511 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
512 mtx_lock_spin(&icu_lock);
513 value = ioapic_read(apic, IOAPIC_VER);
514 mtx_unlock_spin(&icu_lock);
516 /* If it's version register doesn't seem to work, punt. */
517 if (value == 0xffffffff) {
518 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
522 /* Determine the number of vectors and set the APIC ID. */
523 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
524 io = malloc(sizeof(struct ioapic) +
525 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
526 io->io_pic = ioapic_template;
527 mtx_lock_spin(&icu_lock);
528 io->io_id = next_id++;
529 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
530 if (apic_id != -1 && io->io_apic_id != apic_id) {
531 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
532 mtx_unlock_spin(&icu_lock);
533 io->io_apic_id = apic_id;
534 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
537 mtx_unlock_spin(&icu_lock);
539 intbase = next_ioapic_base;
540 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
542 } else if (intbase != next_ioapic_base && bootverbose)
543 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
544 io->io_id, intbase, next_ioapic_base);
545 io->io_intbase = intbase;
546 next_ioapic_base = intbase + numintr;
547 io->io_numintr = numintr;
552 * Initialize pins. Start off with interrupts disabled. Default
553 * to active-hi and edge-triggered for ISA interrupts and active-lo
554 * and level-triggered for all others.
556 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
557 mtx_lock_spin(&icu_lock);
558 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
559 intpin->io_intsrc.is_pic = (struct pic *)io;
560 intpin->io_intpin = i;
561 intpin->io_irq = intbase + i;
564 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
565 * Assume that pins 1-15 are ISA interrupts and that all
566 * other pins are PCI interrupts.
568 if (intpin->io_irq == 0)
569 ioapic_set_extint(io, i);
570 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
571 intpin->io_bus = APIC_BUS_ISA;
572 intpin->io_activehi = 1;
573 intpin->io_edgetrigger = 1;
574 intpin->io_masked = 1;
576 intpin->io_bus = APIC_BUS_PCI;
577 intpin->io_activehi = 0;
578 intpin->io_edgetrigger = 0;
579 intpin->io_masked = 1;
583 * Route interrupts to the BSP by default. Interrupts may
584 * be routed to other CPUs later after they are enabled.
586 intpin->io_cpu = PCPU_GET(apic_id);
587 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
588 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
590 mtx_unlock_spin(&icu_lock);
596 ioapic_get_vector(void *cookie, u_int pin)
600 io = (struct ioapic *)cookie;
601 if (pin >= io->io_numintr)
603 return (io->io_pins[pin].io_irq);
607 ioapic_disable_pin(void *cookie, u_int pin)
611 io = (struct ioapic *)cookie;
612 if (pin >= io->io_numintr)
614 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
616 io->io_pins[pin].io_irq = IRQ_DISABLED;
618 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
623 ioapic_remap_vector(void *cookie, u_int pin, int vector)
627 io = (struct ioapic *)cookie;
628 if (pin >= io->io_numintr || vector < 0)
630 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
632 io->io_pins[pin].io_irq = vector;
634 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
640 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
644 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
646 io = (struct ioapic *)cookie;
647 if (pin >= io->io_numintr)
649 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
651 if (io->io_pins[pin].io_bus == bus_type)
653 io->io_pins[pin].io_bus = bus_type;
655 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
656 ioapic_bus_string(bus_type));
661 ioapic_set_nmi(void *cookie, u_int pin)
665 io = (struct ioapic *)cookie;
666 if (pin >= io->io_numintr)
668 if (io->io_pins[pin].io_irq == IRQ_NMI)
670 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
672 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
673 io->io_pins[pin].io_irq = IRQ_NMI;
674 io->io_pins[pin].io_masked = 0;
675 io->io_pins[pin].io_edgetrigger = 1;
676 io->io_pins[pin].io_activehi = 1;
678 printf("ioapic%u: Routing NMI -> intpin %d\n",
684 ioapic_set_smi(void *cookie, u_int pin)
688 io = (struct ioapic *)cookie;
689 if (pin >= io->io_numintr)
691 if (io->io_pins[pin].io_irq == IRQ_SMI)
693 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
695 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
696 io->io_pins[pin].io_irq = IRQ_SMI;
697 io->io_pins[pin].io_masked = 0;
698 io->io_pins[pin].io_edgetrigger = 1;
699 io->io_pins[pin].io_activehi = 1;
701 printf("ioapic%u: Routing SMI -> intpin %d\n",
707 ioapic_set_extint(void *cookie, u_int pin)
711 io = (struct ioapic *)cookie;
712 if (pin >= io->io_numintr)
714 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
716 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
718 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
719 io->io_pins[pin].io_irq = IRQ_EXTINT;
721 io->io_pins[pin].io_masked = 0;
723 io->io_pins[pin].io_masked = 1;
724 io->io_pins[pin].io_edgetrigger = 1;
725 io->io_pins[pin].io_activehi = 1;
727 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
733 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
738 io = (struct ioapic *)cookie;
739 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
741 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
743 activehi = (pol == INTR_POLARITY_HIGH);
744 if (io->io_pins[pin].io_activehi == activehi)
746 io->io_pins[pin].io_activehi = activehi;
748 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
749 pol == INTR_POLARITY_HIGH ? "high" : "low");
754 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
759 io = (struct ioapic *)cookie;
760 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
762 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
764 edgetrigger = (trigger == INTR_TRIGGER_EDGE);
765 if (io->io_pins[pin].io_edgetrigger == edgetrigger)
767 io->io_pins[pin].io_edgetrigger = edgetrigger;
769 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
770 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
775 * Register a complete I/O APIC object with the interrupt subsystem.
778 ioapic_register(void *cookie)
780 struct ioapic_intsrc *pin;
782 volatile ioapic_t *apic;
786 io = (struct ioapic *)cookie;
788 mtx_lock_spin(&icu_lock);
789 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
790 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
791 mtx_unlock_spin(&icu_lock);
792 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
793 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
794 io->io_intbase + io->io_numintr - 1);
796 /* Register valid pins as interrupt sources. */
797 intr_register_pic(&io->io_pic);
798 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++)
799 if (pin->io_irq < NUM_IO_INTS)
800 intr_register_source(&pin->io_intsrc);
803 /* A simple new-bus driver to consume PCI I/O APIC devices. */
805 ioapic_pci_probe(device_t dev)
808 if (pci_get_class(dev) == PCIC_BASEPERIPH &&
809 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) {
810 switch (pci_get_progif(dev)) {
811 case PCIP_BASEPERIPH_PIC_IO_APIC:
812 device_set_desc(dev, "IO APIC");
814 case PCIP_BASEPERIPH_PIC_IOX_APIC:
815 device_set_desc(dev, "IO(x) APIC");
827 ioapic_pci_attach(device_t dev)
833 static device_method_t ioapic_pci_methods[] = {
834 /* Device interface */
835 DEVMETHOD(device_probe, ioapic_pci_probe),
836 DEVMETHOD(device_attach, ioapic_pci_attach),
841 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0);
843 static devclass_t ioapic_devclass;
844 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0);
847 * A new-bus driver to consume the memory resources associated with
848 * the APICs in the system. On some systems ACPI or PnPBIOS system
849 * resource devices may already claim these resources. To keep from
850 * breaking those devices, we attach ourself to the nexus device after
851 * legacy0 and acpi0 and ignore any allocation failures.
854 apic_identify(driver_t *driver, device_t parent)
858 * Add at order 12. acpi0 is probed at order 10 and legacy0
859 * is probed at order 11.
861 if (lapic_paddr != 0)
862 BUS_ADD_CHILD(parent, 12, "apic", 0);
866 apic_probe(device_t dev)
869 device_set_desc(dev, "APIC resources");
875 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length)
881 * Resources use long's to track resources, so we can't
882 * include memory regions above 4GB.
887 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length);
889 panic("apic_add_resource: resource %d failed set with %d", rid,
891 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0);
895 apic_attach(device_t dev)
900 /* Reserve the local APIC. */
901 apic_add_resource(dev, 0, lapic_paddr, sizeof(lapic_t));
903 STAILQ_FOREACH(io, &ioapic_list, io_next) {
904 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION);
910 static device_method_t apic_methods[] = {
911 /* Device interface */
912 DEVMETHOD(device_identify, apic_identify),
913 DEVMETHOD(device_probe, apic_probe),
914 DEVMETHOD(device_attach, apic_attach),
919 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0);
921 static devclass_t apic_devclass;
922 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);