2 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Copyright (C) 2001 Benno Rice
27 * All rights reserved.
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
32 * 1. Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * 2. Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
38 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
39 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
40 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
41 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
43 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
44 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
45 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
46 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
47 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
51 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
52 * Copyright (C) 1995, 1996 TooLs GmbH.
53 * All rights reserved.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
63 * 3. All advertising materials mentioning features or use of this software
64 * must display the following acknowledgement:
65 * This product includes software developed by TooLs GmbH.
66 * 4. The name of TooLs GmbH may not be used to endorse or promote products
67 * derived from this software without specific prior written permission.
69 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
72 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
73 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
74 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
75 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
76 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
77 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
78 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
84 #include "opt_compat.h"
86 #include "opt_kstack_pages.h"
87 #include "opt_msgbuf.h"
89 #include <sys/cdefs.h>
90 #include <sys/types.h>
91 #include <sys/param.h>
93 #include <sys/systm.h>
101 #include <sys/kernel.h>
102 #include <sys/lock.h>
103 #include <sys/mutex.h>
104 #include <sys/sysctl.h>
105 #include <sys/exec.h>
107 #include <sys/sysproto.h>
108 #include <sys/signalvar.h>
109 #include <sys/sysent.h>
110 #include <sys/imgact.h>
111 #include <sys/msgbuf.h>
112 #include <sys/ptrace.h>
116 #include <vm/vm_page.h>
117 #include <vm/vm_object.h>
118 #include <vm/vm_pager.h>
120 #include <machine/cpu.h>
121 #include <machine/kdb.h>
122 #include <machine/reg.h>
123 #include <machine/vmparam.h>
124 #include <machine/spr.h>
125 #include <machine/hid.h>
126 #include <machine/psl.h>
127 #include <machine/trap.h>
128 #include <machine/md_var.h>
129 #include <machine/mmuvar.h>
130 #include <machine/sigframe.h>
131 #include <machine/metadata.h>
132 #include <machine/bootinfo.h>
133 #include <machine/platform.h>
135 #include <sys/linker.h>
136 #include <sys/reboot.h>
138 #include <powerpc/mpc85xx/ocpbus.h>
139 #include <powerpc/mpc85xx/mpc85xx.h>
142 extern vm_offset_t ksym_start, ksym_end;
146 #define debugf(fmt, args...) printf(fmt, ##args)
148 #define debugf(fmt, args...)
151 extern unsigned char kernel_text[];
152 extern unsigned char _etext[];
153 extern unsigned char _edata[];
154 extern unsigned char __bss_start[];
155 extern unsigned char __sbss_start[];
156 extern unsigned char __sbss_end[];
157 extern unsigned char _end[];
159 extern void dcache_enable(void);
160 extern void dcache_inval(void);
161 extern void icache_enable(void);
162 extern void icache_inval(void);
164 struct kva_md_info kmi;
165 struct pcpu __pcpu[MAXCPU];
166 struct trapframe frame0;
171 struct bootinfo *bootinfo;
173 char machine[] = "powerpc";
174 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
176 int cacheline_size = 32;
178 SYSCTL_INT(_machdep, CPU_CACHELINE, cacheline_size,
179 CTLFLAG_RD, &cacheline_size, 0, "");
181 int hw_direct_map = 0;
183 static void cpu_e500_startup(void *);
184 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_e500_startup, NULL);
186 void print_kernel_section_addr(void);
187 void print_bootinfo(void);
188 void print_kenv(void);
189 u_int e500_init(u_int32_t, u_int32_t, void *);
192 cpu_e500_startup(void *dummy)
196 /* Initialise the decrementer-based clock. */
199 /* Good {morning,afternoon,evening,night}. */
200 cpu_setup(PCPU_GET(cpuid));
202 printf("real memory = %ld (%ld MB)\n", ptoa(physmem),
203 ptoa(physmem) / 1048576);
206 /* Display any holes after the first chunk of extended memory. */
208 printf("Physical memory chunk(s):\n");
209 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
210 size = phys_avail[indx + 1] - phys_avail[indx];
212 printf("0x%08x - 0x%08x, %d bytes (%d pages)\n",
213 phys_avail[indx], phys_avail[indx + 1] - 1,
214 size, size / PAGE_SIZE);
218 vm_ksubmap_init(&kmi);
220 printf("avail memory = %ld (%ld MB)\n", ptoa(cnt.v_free_count),
221 ptoa(cnt.v_free_count) / 1048576);
223 /* Set up buffers, so they can be used to read disk labels. */
225 vm_pager_bufferinit();
248 debugf("loader passed (static) kenv:\n");
249 if (kern_envp == NULL) {
250 debugf(" no env, null ptr\n");
253 debugf(" kern_envp = 0x%08x\n", (u_int32_t)kern_envp);
256 for (cp = kern_envp; cp != NULL; cp = kenv_next(cp))
257 debugf(" %x %s\n", (u_int32_t)cp, cp);
263 struct bi_mem_region *mr;
264 struct bi_eth_addr *eth;
267 debugf("bootinfo:\n");
268 if (bootinfo == NULL) {
269 debugf(" no bootinfo, null ptr\n");
273 debugf(" version = 0x%08x\n", bootinfo->bi_version);
274 debugf(" ccsrbar = 0x%08x\n", bootinfo->bi_bar_base);
275 debugf(" cpu_clk = 0x%08x\n", bootinfo->bi_cpu_clk);
276 debugf(" bus_clk = 0x%08x\n", bootinfo->bi_bus_clk);
278 debugf(" mem regions:\n");
279 mr = (struct bi_mem_region *)bootinfo->bi_data;
280 for (i = 0; i < bootinfo->bi_mem_reg_no; i++, mr++)
281 debugf(" #%d, base = 0x%08x, size = 0x%08x\n", i,
282 mr->mem_base, mr->mem_size);
284 debugf(" eth addresses:\n");
285 eth = (struct bi_eth_addr *)mr;
286 for (i = 0; i < bootinfo->bi_eth_addr_no; i++, eth++) {
287 debugf(" #%d, addr = ", i);
288 for (j = 0; j < 6; j++)
289 debugf("%02x ", eth->mac_addr[j]);
295 print_kernel_section_addr(void)
298 debugf("kernel image addresses:\n");
299 debugf(" kernel_text = 0x%08x\n", (uint32_t)kernel_text);
300 debugf(" _etext (sdata) = 0x%08x\n", (uint32_t)_etext);
301 debugf(" _edata = 0x%08x\n", (uint32_t)_edata);
302 debugf(" __sbss_start = 0x%08x\n", (uint32_t)__sbss_start);
303 debugf(" __sbss_end = 0x%08x\n", (uint32_t)__sbss_end);
304 debugf(" __sbss_start = 0x%08x\n", (uint32_t)__bss_start);
305 debugf(" _end = 0x%08x\n", (uint32_t)_end);
308 struct bi_mem_region *
312 return ((struct bi_mem_region *)bootinfo->bi_data);
318 struct bi_mem_region *mr;
319 struct bi_eth_addr *eth;
322 /* Advance to the eth section */
324 for (i = 0; i < bootinfo->bi_mem_reg_no; i++, mr++)
327 eth = (struct bi_eth_addr *)mr;
332 e500_init(u_int32_t startkernel, u_int32_t endkernel, void *mdp)
344 * Parse metadata and fetch parameters. This must be done as the first
345 * step as we need bootinfo data to at least init the console
348 preload_metadata = mdp;
349 kmdp = preload_search_by_type("elf kernel");
351 bootinfo = (struct bootinfo *)preload_search_info(kmdp,
352 MODINFO_METADATA | MODINFOMD_BOOTINFO);
354 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
355 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *);
356 end = MD_FETCH(kmdp, MODINFOMD_KERNEND, vm_offset_t);
358 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
359 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
364 * We should scream but how? - without CCSR bar (in bootinfo)
365 * cannot even output anything...
369 * FIXME add return value and handle in the locore so we can
370 * return to the loader maybe? (this seems not very easy to
371 * restore everything as the TLB have all been reprogrammed
372 * in the locore etc...)
377 /* Initialize TLB1 handling */
378 tlb1_init(bootinfo->bi_bar_base);
380 /* Reset Time Base */
383 /* Init params/tunables that can be overridden by the loader. */
386 /* Start initializing proc0 and thread0. */
387 proc_linkup0(&proc0, &thread0);
388 thread0.td_frame = &frame0;
390 /* Set up per-cpu data and store the pointer in SPR general 0. */
392 pcpu_init(pc, 0, sizeof(struct pcpu));
393 pc->pc_curthread = &thread0;
394 __asm __volatile("mtsprg 0, %0" :: "r"(pc));
396 /* Initialize system mutexes. */
399 /* Initialize the console before printing anything. */
402 /* Print out some debug info... */
403 debugf("e500_init: console initialized\n");
404 debugf(" arg1 startkernel = 0x%08x\n", startkernel);
405 debugf(" arg2 endkernel = 0x%08x\n", endkernel);
406 debugf(" arg3 mdp = 0x%08x\n", (u_int32_t)mdp);
407 debugf(" end = 0x%08x\n", (u_int32_t)end);
408 debugf(" boothowto = 0x%08x\n", boothowto);
409 debugf(" kernel ccsrbar = 0x%08x\n", CCSRBAR_VA);
410 debugf(" MSR = 0x%08x\n", mfmsr());
411 debugf(" HID0 = 0x%08x\n", mfspr(SPR_HID0));
412 debugf(" HID1 = 0x%08x\n", mfspr(SPR_HID1));
413 debugf(" BUCSR = 0x%08x\n", mfspr(SPR_BUCSR));
415 __asm __volatile("msync; isync");
416 csr = ccsr_read4(OCP85XX_L2CTL);
417 debugf(" L2CTL = 0x%08x\n", csr);
420 print_kernel_section_addr();
422 //tlb1_print_entries();
423 //tlb1_print_tlbentries();
428 if (boothowto & RB_KDB)
429 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
432 /* Initialise platform module */
433 platform_probe_and_attach();
435 /* Initialise virtual memory. */
436 pmap_mmu_install(MMU_TYPE_BOOKE, 0);
437 pmap_bootstrap(startkernel, end);
438 debugf("MSR = 0x%08x\n", mfmsr());
439 //tlb1_print_entries();
440 //tlb1_print_tlbentries();
442 /* Initialize params/tunables that are derived from memsize. */
443 init_param2(physmem);
445 /* Finish setting up thread0. */
446 thread0.td_pcb = (struct pcb *)
447 ((thread0.td_kstack + thread0.td_kstack_pages * PAGE_SIZE -
448 sizeof(struct pcb)) & ~15);
449 bzero((void *)thread0.td_pcb, sizeof(struct pcb));
450 pc->pc_curpcb = thread0.td_pcb;
452 /* Initialise the message buffer. */
453 msgbufinit(msgbufp, MSGBUF_SIZE);
455 /* Enable Machine Check interrupt. */
456 mtmsr(mfmsr() | PSL_ME);
459 /* Enable D-cache if applicable */
460 csr = mfspr(SPR_L1CSR0);
461 if ((csr & L1CSR0_DCE) == 0) {
466 csr = mfspr(SPR_L1CSR0);
467 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
468 printf("L1 D-cache %sabled\n",
469 (csr & L1CSR0_DCE) ? "en" : "dis");
471 /* Enable L1 I-cache if applicable. */
472 csr = mfspr(SPR_L1CSR1);
473 if ((csr & L1CSR1_ICE) == 0) {
478 csr = mfspr(SPR_L1CSR1);
479 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
480 printf("L1 I-cache %sabled\n",
481 (csr & L1CSR1_ICE) ? "en" : "dis");
483 debugf("e500_init: SP = 0x%08x\n", ((uintptr_t)thread0.td_pcb - 16) & ~15);
484 debugf("e500_init: e\n");
486 return (((uintptr_t)thread0.td_pcb - 16) & ~15);
489 #define RES_GRANULE 32
490 extern uint32_t tlb0_miss_locks[];
492 /* Initialise a struct pcpu. */
494 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
497 pcpu->pc_tid_next = TID_MIN;
501 int words_per_gran = RES_GRANULE / sizeof(uint32_t);
503 ptr = &tlb0_miss_locks[cpuid * words_per_gran];
504 pcpu->pc_booke_tlb_lock = ptr;
506 *(ptr + 1) = 0; /* recurse counter */
511 * Flush the D-cache for non-DMA I/O so that the I-cache can
512 * be made coherent later.
515 cpu_flush_dcache(void *ptr, size_t len)
523 * Set Wait state enable.
533 if ((msr & PSL_EE) != PSL_EE) {
534 struct thread *td = curthread;
535 printf("td msr %x\n", td->td_md.md_saved_msr);
536 panic("ints disabled in idleproc!");
540 /* Freescale E500 core RM section 6.4.1. */
542 __asm __volatile("msync; mtmsr %0; isync" :: "r" (msr));
546 cpu_idle_wakeup(int cpu)
558 if (td->td_md.md_spinlock_count == 0)
559 td->td_md.md_saved_msr = intr_disable();
560 td->td_md.md_spinlock_count++;
571 td->td_md.md_spinlock_count--;
572 if (td->td_md.md_spinlock_count == 0)
573 intr_restore(td->td_md.md_saved_msr);
576 /* Shutdown the CPU as much as possible. */
581 mtmsr(mfmsr() & ~(PSL_CE | PSL_EE | PSL_ME | PSL_DE));
586 ptrace_set_pc(struct thread *td, unsigned long addr)
588 struct trapframe *tf;
591 tf->srr0 = (register_t)addr;
597 ptrace_single_step(struct thread *td)
599 struct trapframe *tf;
603 tf->cpu.booke.dbcr0 |= (DBCR0_IDM | DBCR0_IC);
608 ptrace_clear_single_step(struct thread *td)
610 struct trapframe *tf;
614 tf->cpu.booke.dbcr0 &= ~(DBCR0_IDM | DBCR0_IC);
619 kdb_cpu_clear_singlestep(void)
623 r = mfspr(SPR_DBCR0);
624 mtspr(SPR_DBCR0, r & ~DBCR0_IC);
625 kdb_frame->srr1 &= ~PSL_DE;
629 kdb_cpu_set_singlestep(void)
633 r = mfspr(SPR_DBCR0);
634 mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM);
635 kdb_frame->srr1 |= PSL_DE;
639 bzero(void *buf, size_t len)
645 while (((vm_offset_t) p & (sizeof(u_long) - 1)) && len) {
650 while (len >= sizeof(u_long) * 8) {
652 *((u_long*) p + 1) = 0;
653 *((u_long*) p + 2) = 0;
654 *((u_long*) p + 3) = 0;
655 len -= sizeof(u_long) * 8;
656 *((u_long*) p + 4) = 0;
657 *((u_long*) p + 5) = 0;
658 *((u_long*) p + 6) = 0;
659 *((u_long*) p + 7) = 0;
660 p += sizeof(u_long) * 8;
663 while (len >= sizeof(u_long)) {
665 len -= sizeof(u_long);
676 * XXX what is the better/proper place for this routine?
679 mem_valid(vm_offset_t addr, int len)