2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
42 #include <machine/bus.h>
44 #include <dev/fdt/fdt_common.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/mmc/bridge.h>
49 #include <dev/mmc/mmcreg.h>
51 #include <dev/sdhci/sdhci.h>
56 #include "bcm2835_dma.h"
57 #include "bcm2835_vcbus.h"
59 #define BCM2835_DEFAULT_SDHCI_FREQ 50
61 #define BCM_SDHCI_BUFFER_SIZE 512
62 #define NUM_DMA_SEGS 2
65 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
66 printf(fmt,##args); } while (0)
68 #define dprintf(fmt, args...)
71 static int bcm2835_sdhci_hs = 1;
72 static int bcm2835_sdhci_pio_mode = 0;
74 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
75 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
77 struct bcm_sdhci_softc {
80 struct resource * sc_mem_res;
81 struct resource * sc_irq_res;
82 bus_space_tag_t sc_bst;
83 bus_space_handle_t sc_bsh;
85 struct mmc_request * sc_req;
86 struct mmc_data * sc_data;
88 #define LPC_SD_FLAGS_IGNORECRC (1 << 0)
89 int sc_xfer_direction;
90 #define DIRECTION_READ 0
91 #define DIRECTION_WRITE 1
94 struct sdhci_slot sc_slot;
97 bus_dma_tag_t sc_dma_tag;
98 bus_dmamap_t sc_dma_map;
99 vm_paddr_t sc_sdhci_buffer_phys;
100 uint32_t cmd_and_mode;
101 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS];
102 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS];
103 int dmamap_seg_count;
104 int dmamap_seg_index;
108 static int bcm_sdhci_probe(device_t);
109 static int bcm_sdhci_attach(device_t);
110 static int bcm_sdhci_detach(device_t);
111 static void bcm_sdhci_intr(void *);
113 static int bcm_sdhci_get_ro(device_t, device_t);
114 static void bcm_sdhci_dma_intr(int ch, void *arg);
116 #define bcm_sdhci_lock(_sc) \
117 mtx_lock(&_sc->sc_mtx);
118 #define bcm_sdhci_unlock(_sc) \
119 mtx_unlock(&_sc->sc_mtx);
122 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
124 struct bcm_sdhci_softc *sc = arg;
127 sc->dmamap_status = err;
128 sc->dmamap_seg_count = nseg;
130 /* Note nseg is guaranteed to be zero if err is non-zero. */
131 for (i = 0; i < nseg; i++) {
132 sc->dmamap_seg_addrs[i] = segs[i].ds_addr;
133 sc->dmamap_seg_sizes[i] = segs[i].ds_len;
138 bcm_sdhci_probe(device_t dev)
141 if (!ofw_bus_status_okay(dev))
144 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
147 device_set_desc(dev, "Broadcom 2708 SDHCI controller");
148 return (BUS_PROBE_DEFAULT);
152 bcm_sdhci_attach(device_t dev)
154 struct bcm_sdhci_softc *sc = device_get_softc(dev);
164 default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
165 node = ofw_bus_get_node(sc->sc_dev);
166 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0)
167 default_freq = (int)fdt32_to_cpu(cell)/1000000;
169 dprintf("SDHCI frequency: %dMHz\n", default_freq);
171 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF);
174 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
176 if (!sc->sc_mem_res) {
177 device_printf(dev, "cannot allocate memory window\n");
182 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
183 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
186 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
188 if (!sc->sc_irq_res) {
189 device_printf(dev, "cannot allocate interrupt\n");
194 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
195 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) {
196 device_printf(dev, "cannot setup interrupt handler\n");
201 if (!bcm2835_sdhci_pio_mode)
202 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
204 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
205 if (bcm2835_sdhci_hs)
206 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
207 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
208 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
209 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
210 | SDHCI_QUIRK_DONT_SET_HISPD_BIT
211 | SDHCI_QUIRK_MISSING_CAPS;
213 sdhci_init_slot(dev, &sc->sc_slot, 0);
215 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
216 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
217 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
218 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
219 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
220 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
223 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
225 /* Allocate bus_dma resources. */
226 err = bus_dma_tag_create(bus_get_dma_tag(dev),
227 1, 0, BUS_SPACE_MAXADDR_32BIT,
228 BUS_SPACE_MAXADDR, NULL, NULL,
229 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE,
230 BUS_DMA_ALLOCNOW, NULL, NULL,
234 device_printf(dev, "failed allocate DMA tag");
238 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
240 device_printf(dev, "bus_dmamap_create failed\n");
244 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
247 bus_generic_probe(dev);
248 bus_generic_attach(dev);
250 sdhci_start_slot(&sc->sc_slot);
256 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
258 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
260 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
261 mtx_destroy(&sc->sc_mtx);
267 bcm_sdhci_detach(device_t dev)
274 bcm_sdhci_intr(void *arg)
276 struct bcm_sdhci_softc *sc = arg;
278 sdhci_generic_intr(&sc->sc_slot);
282 bcm_sdhci_get_ro(device_t bus, device_t child)
288 static inline uint32_t
289 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
291 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
296 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
299 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
301 * The Arasan HC has a bug where it may lose the content of
302 * consecutive writes to registers that are within two SD-card
303 * clock cycles of each other (a clock domain crossing problem).
305 if (sc->sc_slot.clock > 0)
306 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
310 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
312 struct bcm_sdhci_softc *sc = device_get_softc(dev);
313 uint32_t val = RD4(sc, off & ~3);
315 return ((val >> (off & 3)*8) & 0xff);
319 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
321 struct bcm_sdhci_softc *sc = device_get_softc(dev);
322 uint32_t val = RD4(sc, off & ~3);
325 * Standard 32-bit handling of command and transfer mode.
327 if (off == SDHCI_TRANSFER_MODE) {
328 return (sc->cmd_and_mode >> 16);
329 } else if (off == SDHCI_COMMAND_FLAGS) {
330 return (sc->cmd_and_mode & 0x0000ffff);
332 return ((val >> (off & 3)*8) & 0xffff);
336 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
338 struct bcm_sdhci_softc *sc = device_get_softc(dev);
344 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
345 uint32_t *data, bus_size_t count)
347 struct bcm_sdhci_softc *sc = device_get_softc(dev);
349 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
353 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
355 struct bcm_sdhci_softc *sc = device_get_softc(dev);
356 uint32_t val32 = RD4(sc, off & ~3);
357 val32 &= ~(0xff << (off & 3)*8);
358 val32 |= (val << (off & 3)*8);
359 WR4(sc, off & ~3, val32);
363 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
365 struct bcm_sdhci_softc *sc = device_get_softc(dev);
367 if (off == SDHCI_COMMAND_FLAGS)
368 val32 = sc->cmd_and_mode;
370 val32 = RD4(sc, off & ~3);
371 val32 &= ~(0xffff << (off & 3)*8);
372 val32 |= (val << (off & 3)*8);
373 if (off == SDHCI_TRANSFER_MODE)
374 sc->cmd_and_mode = val32;
376 WR4(sc, off & ~3, val32);
377 if (off == SDHCI_COMMAND_FLAGS)
378 sc->cmd_and_mode = val32;
383 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
385 struct bcm_sdhci_softc *sc = device_get_softc(dev);
390 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
391 uint32_t *data, bus_size_t count)
393 struct bcm_sdhci_softc *sc = device_get_softc(dev);
395 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
399 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc)
401 struct sdhci_slot *slot;
402 vm_paddr_t pdst, psrc;
403 int err, idx, len, sync_op;
406 idx = sc->dmamap_seg_index++;
407 len = sc->dmamap_seg_sizes[idx];
410 if (slot->curcmd->data->flags & MMC_DATA_READ) {
411 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
412 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
413 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
415 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
416 psrc = sc->sc_sdhci_buffer_phys;
417 pdst = sc->dmamap_seg_addrs[idx];
418 sync_op = BUS_DMASYNC_PREREAD;
420 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
422 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
423 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
424 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
425 psrc = sc->dmamap_seg_addrs[idx];
426 pdst = sc->sc_sdhci_buffer_phys;
427 sync_op = BUS_DMASYNC_PREWRITE;
431 * When starting a new DMA operation do the busdma sync operation, and
432 * disable SDCHI data interrrupts because we'll be driven by DMA
433 * interrupts (or SDHCI error interrupts) until the IO is done.
436 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
437 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL |
438 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
439 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE,
444 * Start the DMA transfer. Only programming errors (like failing to
445 * allocate a channel) cause a non-zero return from bcm_dma_start().
447 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len);
448 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start"));
452 bcm_sdhci_dma_intr(int ch, void *arg)
454 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
455 struct sdhci_slot *slot = &sc->sc_slot;
459 mtx_lock(&slot->mtx);
462 * If there are more segments for the current dma, start the next one.
463 * Otherwise unload the dma map and decide what to do next based on the
464 * status of the sdhci controller and whether there's more data left.
466 if (sc->dmamap_seg_index < sc->dmamap_seg_count) {
467 bcm_sdhci_start_dma_seg(sc);
468 mtx_unlock(&slot->mtx);
472 if (slot->curcmd->data->flags & MMC_DATA_READ) {
473 sync_op = BUS_DMASYNC_POSTREAD;
474 mask = SDHCI_INT_DATA_AVAIL;
476 sync_op = BUS_DMASYNC_POSTWRITE;
477 mask = SDHCI_INT_SPACE_AVAIL;
479 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
480 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
482 sc->dmamap_seg_count = 0;
483 sc->dmamap_seg_index = 0;
485 left = min(BCM_SDHCI_BUFFER_SIZE,
486 slot->curcmd->data->len - slot->offset);
489 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
491 if (reg & SDHCI_INT_DATA_END) {
492 /* ACK for all outstanding interrupts */
493 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
496 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
497 | SDHCI_INT_DATA_END;
498 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
501 /* finish this data */
502 sdhci_finish_data(slot);
505 /* already available? */
508 /* ACK for DATA_AVAIL or SPACE_AVAIL */
509 bcm_sdhci_write_4(slot->bus, slot,
510 SDHCI_INT_STATUS, mask);
512 /* continue next DMA transfer */
513 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
514 (uint8_t *)slot->curcmd->data->data +
515 slot->offset, left, bcm_sdhci_dmacb, sc,
516 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) {
517 slot->curcmd->error = MMC_ERR_NO_MEMORY;
518 sdhci_finish_data(slot);
520 bcm_sdhci_start_dma_seg(sc);
523 /* wait for next data by INT */
526 slot->intmask |= SDHCI_INT_DATA_AVAIL |
527 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
528 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
533 mtx_unlock(&slot->mtx);
537 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot)
539 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
542 if (sc->dmamap_seg_count != 0) {
543 device_printf(sc->sc_dev, "DMA in use\n");
547 left = min(BCM_SDHCI_BUFFER_SIZE,
548 slot->curcmd->data->len - slot->offset);
550 KASSERT((left & 3) == 0,
551 ("%s: len = %d, not word-aligned", __func__, left));
553 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
554 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
555 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
556 sc->dmamap_status != 0) {
557 slot->curcmd->error = MMC_ERR_NO_MEMORY;
562 bcm_sdhci_start_dma_seg(sc);
566 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot)
568 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
571 if (sc->dmamap_seg_count != 0) {
572 device_printf(sc->sc_dev, "DMA in use\n");
576 left = min(BCM_SDHCI_BUFFER_SIZE,
577 slot->curcmd->data->len - slot->offset);
579 KASSERT((left & 3) == 0,
580 ("%s: len = %d, not word-aligned", __func__, left));
582 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
583 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
584 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
585 sc->dmamap_status != 0) {
586 slot->curcmd->error = MMC_ERR_NO_MEMORY;
591 bcm_sdhci_start_dma_seg(sc);
595 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
600 * Do not use DMA for transfers less than block size or with a length
601 * that is not a multiple of four.
603 left = min(BCM_DMA_BLOCK_SIZE,
604 slot->curcmd->data->len - slot->offset);
605 if (left < BCM_DMA_BLOCK_SIZE)
614 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
618 /* DMA transfer FIFO 1KB */
619 if (slot->curcmd->data->flags & MMC_DATA_READ)
620 bcm_sdhci_read_dma(dev, slot);
622 bcm_sdhci_write_dma(dev, slot);
626 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
629 sdhci_finish_data(slot);
632 static device_method_t bcm_sdhci_methods[] = {
633 /* Device interface */
634 DEVMETHOD(device_probe, bcm_sdhci_probe),
635 DEVMETHOD(device_attach, bcm_sdhci_attach),
636 DEVMETHOD(device_detach, bcm_sdhci_detach),
639 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
640 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
642 /* MMC bridge interface */
643 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
644 DEVMETHOD(mmcbr_request, sdhci_generic_request),
645 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
646 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
647 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
649 /* Platform transfer methods */
650 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
651 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
652 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
653 /* SDHCI registers accessors */
654 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
655 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
656 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
657 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
658 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
659 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
660 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
661 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
666 static devclass_t bcm_sdhci_devclass;
668 static driver_t bcm_sdhci_driver = {
671 sizeof(struct bcm_sdhci_softc),
674 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass,
676 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);
677 MMC_DECLARE_BRIDGE(sdhci_bcm);