sys/arm/broadcom/bcm2835/bcm2835_sdhci.c

   1 /*-
   2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  */
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bio.h>
  33 #include <sys/bus.h>
  34 #include <sys/conf.h>
  35 #include <sys/endian.h>
  36 #include <sys/kernel.h>
  37 #include <sys/kthread.h>
  38 #include <sys/lock.h>
  39 #include <sys/malloc.h>
  40 #include <sys/module.h>
  41 #include <sys/mutex.h>
  42 #include <sys/queue.h>
  43 #include <sys/resource.h>
  44 #include <sys/rman.h>
  45 #include <sys/sysctl.h>
  46 #include <sys/taskqueue.h>
  47 #include <sys/time.h>
  48 #include <sys/timetc.h>
  49 #include <sys/watchdog.h>
  50
  51 #include <sys/kdb.h>
  52
  53 #include <machine/bus.h>
  54 #include <machine/cpu.h>
  55 #include <machine/cpufunc.h>
  56 #include <machine/resource.h>
  57 #include <machine/intr.h>
  58
  59 #include <dev/fdt/fdt_common.h>
  60 #include <dev/ofw/ofw_bus.h>
  61 #include <dev/ofw/ofw_bus_subr.h>
  62
  63 #include <dev/mmc/bridge.h>
  64 #include <dev/mmc/mmcreg.h>
  65 #include <dev/mmc/mmcbrvar.h>
  66
  67 #include <dev/sdhci/sdhci.h>
  68 #include "sdhci_if.h"
  69
  70 #include "bcm2835_dma.h"
  71 #include "bcm2835_vcbus.h"
  72
  73 #define BCM2835_DEFAULT_SDHCI_FREQ      50
  74
  75 #define BCM_SDHCI_BUFFER_SIZE           512
  76
  77 #ifdef DEBUG
  78 #define dprintf(fmt, args...) do { printf("%s(): ", __func__);   \
  79     printf(fmt,##args); } while (0)
  80 #else
  81 #define dprintf(fmt, args...)
  82 #endif
  83
  84 /*
  85  * Arasan HC seems to have problem with Data CRC on lower frequencies.
  86  * Use this tunable to cap initialization sequence frequency at higher
  87  * value. Default is standard 400kHz
  88  */
  89 static int bcm2835_sdhci_min_freq = 400000;
  90 static int bcm2835_sdhci_hs = 1;
  91 static int bcm2835_sdhci_pio_mode = 0;
  92
  93 TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq);
  94 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
  95 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
  96
  97 struct bcm_sdhci_dmamap_arg {
  98         bus_addr_t              sc_dma_busaddr;
  99 };
 100
 101 struct bcm_sdhci_softc {
 102         device_t                sc_dev;
 103         struct mtx              sc_mtx;
 104         struct resource *       sc_mem_res;
 105         struct resource *       sc_irq_res;
 106         bus_space_tag_t         sc_bst;
 107         bus_space_handle_t      sc_bsh;
 108         void *                  sc_intrhand;
 109         struct mmc_request *    sc_req;
 110         struct mmc_data *       sc_data;
 111         uint32_t                sc_flags;
 112 #define LPC_SD_FLAGS_IGNORECRC          (1 << 0)
 113         int                     sc_xfer_direction;
 114 #define DIRECTION_READ          0
 115 #define DIRECTION_WRITE         1
 116         int                     sc_xfer_done;
 117         int                     sc_bus_busy;
 118         struct sdhci_slot       sc_slot;
 119         int                     sc_dma_inuse;
 120         int                     sc_dma_ch;
 121         bus_dma_tag_t           sc_dma_tag;
 122         bus_dmamap_t            sc_dma_map;
 123         vm_paddr_t              sc_sdhci_buffer_phys;
 124         uint32_t                cmd_and_mode;
 125 };
 126
 127 static int bcm_sdhci_probe(device_t);
 128 static int bcm_sdhci_attach(device_t);
 129 static int bcm_sdhci_detach(device_t);
 130 static void bcm_sdhci_intr(void *);
 131
 132 static int bcm_sdhci_get_ro(device_t, device_t);
 133 static void bcm_sdhci_dma_intr(int ch, void *arg);
 134
 135 #define bcm_sdhci_lock(_sc)                                             \
 136     mtx_lock(&_sc->sc_mtx);
 137 #define bcm_sdhci_unlock(_sc)                                           \
 138     mtx_unlock(&_sc->sc_mtx);
 139
 140 static void
 141 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
 142         int nseg, int err)
 143 {
 144         bus_addr_t *addr;
 145
 146         if (err)
 147                 return;
 148
 149         addr = (bus_addr_t*)arg;
 150         *addr = segs[0].ds_addr;
 151 }
 152
 153 static int
 154 bcm_sdhci_probe(device_t dev)
 155 {
 156
 157         if (!ofw_bus_status_okay(dev))
 158                 return (ENXIO);
 159
 160         if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
 161                 return (ENXIO);
 162
 163         device_set_desc(dev, "Broadcom 2708 SDHCI controller");
 164         return (BUS_PROBE_DEFAULT);
 165 }
 166
 167 static int
 168 bcm_sdhci_attach(device_t dev)
 169 {
 170         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 171         int rid, err;
 172         phandle_t node;
 173         pcell_t cell;
 174         int default_freq;
 175
 176         sc->sc_dev = dev;
 177         sc->sc_req = NULL;
 178         err = 0;
 179
 180         default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
 181         node = ofw_bus_get_node(sc->sc_dev);
 182         if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0)
 183                 default_freq = (int)fdt32_to_cpu(cell)/1000000;
 184
 185         dprintf("SDHCI frequency: %dMHz\n", default_freq);
 186
 187         mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF);
 188
 189         rid = 0;
 190         sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 191             RF_ACTIVE);
 192         if (!sc->sc_mem_res) {
 193                 device_printf(dev, "cannot allocate memory window\n");
 194                 err = ENXIO;
 195                 goto fail;
 196         }
 197
 198         sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
 199         sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
 200
 201         rid = 0;
 202         sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 203             RF_ACTIVE);
 204         if (!sc->sc_irq_res) {
 205                 device_printf(dev, "cannot allocate interrupt\n");
 206                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 207                 err = ENXIO;
 208                 goto fail;
 209         }
 210
 211         if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
 212             NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand))
 213         {
 214                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 215                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
 216                 device_printf(dev, "cannot setup interrupt handler\n");
 217                 err = ENXIO;
 218                 goto fail;
 219         }
 220
 221         if (!bcm2835_sdhci_pio_mode)
 222                 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
 223
 224         sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
 225         if (bcm2835_sdhci_hs)
 226                 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
 227         sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
 228         sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
 229                 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
 230                 | SDHCI_QUIRK_MISSING_CAPS;
 231
 232         sdhci_init_slot(dev, &sc->sc_slot, 0);
 233
 234         sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
 235         if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
 236                 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
 237         if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
 238                 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
 239         if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
 240                 goto fail;
 241
 242         bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
 243
 244         /* Allocate bus_dma resources. */
 245         err = bus_dma_tag_create(bus_get_dma_tag(dev),
 246             1, 0, BUS_SPACE_MAXADDR_32BIT,
 247             BUS_SPACE_MAXADDR, NULL, NULL,
 248             BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE,
 249             BUS_DMA_ALLOCNOW, NULL, NULL,
 250             &sc->sc_dma_tag);
 251
 252         if (err) {
 253                 device_printf(dev, "failed allocate DMA tag");
 254                 goto fail;
 255         }
 256
 257         err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
 258         if (err) {
 259                 device_printf(dev, "bus_dmamap_create failed\n");
 260                 goto fail;
 261         }
 262
 263         sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
 264             SDHCI_BUFFER);
 265
 266         bus_generic_probe(dev);
 267         bus_generic_attach(dev);
 268
 269         sdhci_start_slot(&sc->sc_slot);
 270
 271         return (0);
 272
 273 fail:
 274         if (sc->sc_intrhand)
 275                 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
 276         if (sc->sc_irq_res)
 277                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
 278         if (sc->sc_mem_res)
 279                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 280
 281         return (err);
 282 }
 283
 284 static int
 285 bcm_sdhci_detach(device_t dev)
 286 {
 287
 288         return (EBUSY);
 289 }
 290
 291 static void
 292 bcm_sdhci_intr(void *arg)
 293 {
 294         struct bcm_sdhci_softc *sc = arg;
 295
 296         sdhci_generic_intr(&sc->sc_slot);
 297 }
 298
 299 static int
 300 bcm_sdhci_get_ro(device_t bus, device_t child)
 301 {
 302
 303         return (0);
 304 }
 305
 306 static inline uint32_t
 307 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
 308 {
 309         uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
 310         return val;
 311 }
 312
 313 static inline void
 314 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
 315 {
 316         bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
 317
 318         if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL))
 319         {
 320                 int timeout = 100000;
 321                 while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)
 322                     && --timeout > 0)
 323                         continue;
 324
 325                 if (timeout <= 0)
 326                         printf("sdhci_brcm: writing 0x%X to reg 0x%X "
 327                                 "always gives 0x%X\n",
 328                                 val, (uint32_t)off,
 329                                 bus_space_read_4(sc->sc_bst, sc->sc_bsh, off));
 330         }
 331 }
 332
 333 static uint8_t
 334 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 335 {
 336         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 337         uint32_t val = RD4(sc, off & ~3);
 338
 339         return ((val >> (off & 3)*8) & 0xff);
 340 }
 341
 342 static uint16_t
 343 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 344 {
 345         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 346         uint32_t val = RD4(sc, off & ~3);
 347
 348         /*
 349          * Standard 32-bit handling of command and transfer mode.
 350          */
 351         if (off == SDHCI_TRANSFER_MODE) {
 352                 return (sc->cmd_and_mode >> 16);
 353         } else if (off == SDHCI_COMMAND_FLAGS) {
 354                 return (sc->cmd_and_mode & 0x0000ffff);
 355         }
 356         return ((val >> (off & 3)*8) & 0xffff);
 357 }
 358
 359 static uint32_t
 360 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 361 {
 362         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 363
 364         return RD4(sc, off);
 365 }
 366
 367 static void
 368 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
 369     uint32_t *data, bus_size_t count)
 370 {
 371         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 372
 373         bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
 374 }
 375
 376 static void
 377 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
 378 {
 379         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 380         uint32_t val32 = RD4(sc, off & ~3);
 381         val32 &= ~(0xff << (off & 3)*8);
 382         val32 |= (val << (off & 3)*8);
 383         WR4(sc, off & ~3, val32);
 384 }
 385
 386 static void
 387 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
 388 {
 389         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 390         uint32_t val32;
 391         if (off == SDHCI_COMMAND_FLAGS)
 392                 val32 = sc->cmd_and_mode;
 393         else
 394                 val32 = RD4(sc, off & ~3);
 395         val32 &= ~(0xffff << (off & 3)*8);
 396         val32 |= (val << (off & 3)*8);
 397         if (off == SDHCI_TRANSFER_MODE)
 398                 sc->cmd_and_mode = val32;
 399         else
 400                 WR4(sc, off & ~3, val32);
 401 }
 402
 403 static void
 404 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
 405 {
 406         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 407         WR4(sc, off, val);
 408 }
 409
 410 static void
 411 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
 412     uint32_t *data, bus_size_t count)
 413 {
 414         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 415
 416         bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
 417 }
 418
 419 static uint32_t
 420 bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot)
 421 {
 422
 423         return bcm2835_sdhci_min_freq;
 424 }
 425
 426 static void
 427 bcm_sdhci_dma_intr(int ch, void *arg)
 428 {
 429         struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
 430         struct sdhci_slot *slot = &sc->sc_slot;
 431         uint32_t reg, mask;
 432         bus_addr_t pmem;
 433         vm_paddr_t pdst, psrc;
 434         size_t len;
 435         int left, sync_op;
 436
 437         mtx_lock(&slot->mtx);
 438
 439         len = bcm_dma_length(sc->sc_dma_ch);
 440         if (slot->curcmd->data->flags & MMC_DATA_READ) {
 441                 sync_op = BUS_DMASYNC_POSTREAD;
 442                 mask = SDHCI_INT_DATA_AVAIL;
 443         } else {
 444                 sync_op = BUS_DMASYNC_POSTWRITE;
 445                 mask = SDHCI_INT_SPACE_AVAIL;
 446         }
 447         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
 448         bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
 449
 450         slot->offset += len;
 451         sc->sc_dma_inuse = 0;
 452
 453         left = min(BCM_SDHCI_BUFFER_SIZE,
 454             slot->curcmd->data->len - slot->offset);
 455
 456         /* DATA END? */
 457         reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
 458
 459         if (reg & SDHCI_INT_DATA_END) {
 460                 /* ACK for all outstanding interrupts */
 461                 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
 462
 463                 /* enable INT */
 464                 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
 465                     | SDHCI_INT_DATA_END;
 466                 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
 467                     slot->intmask);
 468
 469                 /* finish this data */
 470                 sdhci_finish_data(slot);
 471         }
 472         else {
 473                 /* already available? */
 474                 if (reg & mask) {
 475                         sc->sc_dma_inuse = 1;
 476
 477                         /* ACK for DATA_AVAIL or SPACE_AVAIL */
 478                         bcm_sdhci_write_4(slot->bus, slot,
 479                             SDHCI_INT_STATUS, mask);
 480
 481                         /* continue next DMA transfer */
 482                         bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
 483                             (uint8_t *)slot->curcmd->data->data +
 484                             slot->offset, left, bcm_dmamap_cb, &pmem, 0);
 485                         if (slot->curcmd->data->flags & MMC_DATA_READ) {
 486                                 psrc = sc->sc_sdhci_buffer_phys;
 487                                 pdst = pmem;
 488                                 sync_op = BUS_DMASYNC_PREREAD;
 489                         } else {
 490                                 psrc = pmem;
 491                                 pdst = sc->sc_sdhci_buffer_phys;
 492                                 sync_op = BUS_DMASYNC_PREWRITE;
 493                         }
 494                         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
 495                         if (bcm_dma_start(sc->sc_dma_ch, psrc, pdst, left)) {
 496                                 /* XXX stop xfer, other error recovery? */
 497                                 device_printf(sc->sc_dev, "failed DMA start\n");
 498                         }
 499                 } else {
 500                         /* wait for next data by INT */
 501
 502                         /* enable INT */
 503                         slot->intmask |= SDHCI_INT_DATA_AVAIL |
 504                             SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
 505                         bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
 506                             slot->intmask);
 507                 }
 508         }
 509
 510         mtx_unlock(&slot->mtx);
 511 }
 512
 513 static void
 514 bcm_sdhci_read_dma(struct sdhci_slot *slot)
 515 {
 516         struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
 517         size_t left;
 518         bus_addr_t paddr;
 519
 520         if (sc->sc_dma_inuse) {
 521                 device_printf(sc->sc_dev, "DMA in use\n");
 522                 return;
 523         }
 524
 525         sc->sc_dma_inuse = 1;
 526
 527         left = min(BCM_SDHCI_BUFFER_SIZE,
 528             slot->curcmd->data->len - slot->offset);
 529
 530         KASSERT((left & 3) == 0,
 531             ("%s: len = %d, not word-aligned", __func__, left));
 532
 533         bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
 534             BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
 535         bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
 536             BCM_DMA_INC_ADDR,
 537             (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
 538
 539         bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
 540             (uint8_t *)slot->curcmd->data->data + slot->offset, left,
 541             bcm_dmamap_cb, &paddr, 0);
 542
 543         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
 544             BUS_DMASYNC_PREREAD);
 545
 546         /* DMA start */
 547         if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys,
 548             paddr, left) != 0)
 549                 device_printf(sc->sc_dev, "failed DMA start\n");
 550 }
 551
 552 static void
 553 bcm_sdhci_write_dma(struct sdhci_slot *slot)
 554 {
 555         struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
 556         size_t left;
 557         bus_addr_t paddr;
 558
 559         if (sc->sc_dma_inuse) {
 560                 device_printf(sc->sc_dev, "DMA in use\n");
 561                 return;
 562         }
 563
 564         sc->sc_dma_inuse = 1;
 565
 566         left = min(BCM_SDHCI_BUFFER_SIZE,
 567             slot->curcmd->data->len - slot->offset);
 568
 569         KASSERT((left & 3) == 0,
 570             ("%s: len = %d, not word-aligned", __func__, left));
 571
 572         bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
 573             (uint8_t *)slot->curcmd->data->data + slot->offset, left,
 574             bcm_dmamap_cb, &paddr, 0);
 575
 576         bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
 577             BCM_DMA_INC_ADDR,
 578             (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
 579         bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
 580             BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
 581
 582         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
 583             BUS_DMASYNC_PREWRITE);
 584
 585         /* DMA start */
 586         if (bcm_dma_start(sc->sc_dma_ch, paddr,
 587             sc->sc_sdhci_buffer_phys, left) != 0)
 588                 device_printf(sc->sc_dev, "failed DMA start\n");
 589 }
 590
 591 static int
 592 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
 593 {
 594         size_t left;
 595
 596         /*
 597          * Do not use DMA for transfers less than block size or with a length
 598          * that is not a multiple of four.
 599          */
 600         left = min(BCM_DMA_BLOCK_SIZE,
 601             slot->curcmd->data->len - slot->offset);
 602         if (left < BCM_DMA_BLOCK_SIZE)
 603                 return (0);
 604         if (left & 0x03)
 605                 return (0);
 606
 607         return (1);
 608 }
 609
 610 static void
 611 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
 612     uint32_t *intmask)
 613 {
 614
 615         /* Disable INT */
 616         slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
 617         bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
 618
 619         /* DMA transfer FIFO 1KB */
 620         if (slot->curcmd->data->flags & MMC_DATA_READ)
 621                 bcm_sdhci_read_dma(slot);
 622         else
 623                 bcm_sdhci_write_dma(slot);
 624 }
 625
 626 static void
 627 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
 628 {
 629
 630         sdhci_finish_data(slot);
 631 }
 632
 633 static device_method_t bcm_sdhci_methods[] = {
 634         /* Device interface */
 635         DEVMETHOD(device_probe,         bcm_sdhci_probe),
 636         DEVMETHOD(device_attach,        bcm_sdhci_attach),
 637         DEVMETHOD(device_detach,        bcm_sdhci_detach),
 638
 639         /* Bus interface */
 640         DEVMETHOD(bus_read_ivar,        sdhci_generic_read_ivar),
 641         DEVMETHOD(bus_write_ivar,       sdhci_generic_write_ivar),
 642         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 643
 644         /* MMC bridge interface */
 645         DEVMETHOD(mmcbr_update_ios,     sdhci_generic_update_ios),
 646         DEVMETHOD(mmcbr_request,        sdhci_generic_request),
 647         DEVMETHOD(mmcbr_get_ro,         bcm_sdhci_get_ro),
 648         DEVMETHOD(mmcbr_acquire_host,   sdhci_generic_acquire_host),
 649         DEVMETHOD(mmcbr_release_host,   sdhci_generic_release_host),
 650
 651         DEVMETHOD(sdhci_min_freq,       bcm_sdhci_min_freq),
 652         /* Platform transfer methods */
 653         DEVMETHOD(sdhci_platform_will_handle,           bcm_sdhci_will_handle_transfer),
 654         DEVMETHOD(sdhci_platform_start_transfer,        bcm_sdhci_start_transfer),
 655         DEVMETHOD(sdhci_platform_finish_transfer,       bcm_sdhci_finish_transfer),
 656         /* SDHCI registers accessors */
 657         DEVMETHOD(sdhci_read_1,         bcm_sdhci_read_1),
 658         DEVMETHOD(sdhci_read_2,         bcm_sdhci_read_2),
 659         DEVMETHOD(sdhci_read_4,         bcm_sdhci_read_4),
 660         DEVMETHOD(sdhci_read_multi_4,   bcm_sdhci_read_multi_4),
 661         DEVMETHOD(sdhci_write_1,        bcm_sdhci_write_1),
 662         DEVMETHOD(sdhci_write_2,        bcm_sdhci_write_2),
 663         DEVMETHOD(sdhci_write_4,        bcm_sdhci_write_4),
 664         DEVMETHOD(sdhci_write_multi_4,  bcm_sdhci_write_multi_4),
 665
 666         { 0, 0 }
 667 };
 668
 669 static devclass_t bcm_sdhci_devclass;
 670
 671 static driver_t bcm_sdhci_driver = {
 672         "sdhci_bcm",
 673         bcm_sdhci_methods,
 674         sizeof(struct bcm_sdhci_softc),
 675 };
 676
 677 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0);
 678 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);