sys/arm/broadcom/bcm2835/bcm2835_sdhci.c

   1 /*-
   2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  */
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bio.h>
  33 #include <sys/bus.h>
  34 #include <sys/conf.h>
  35 #include <sys/endian.h>
  36 #include <sys/kernel.h>
  37 #include <sys/kthread.h>
  38 #include <sys/lock.h>
  39 #include <sys/malloc.h>
  40 #include <sys/module.h>
  41 #include <sys/mutex.h>
  42 #include <sys/queue.h>
  43 #include <sys/resource.h>
  44 #include <sys/rman.h>
  45 #include <sys/sysctl.h>
  46 #include <sys/taskqueue.h>
  47 #include <sys/time.h>
  48 #include <sys/timetc.h>
  49 #include <sys/watchdog.h>
  50
  51 #include <sys/kdb.h>
  52
  53 #include <machine/bus.h>
  54 #include <machine/cpu.h>
  55 #include <machine/cpufunc.h>
  56 #include <machine/resource.h>
  57 #include <machine/intr.h>
  58
  59 #include <dev/fdt/fdt_common.h>
  60 #include <dev/ofw/ofw_bus.h>
  61 #include <dev/ofw/ofw_bus_subr.h>
  62
  63 #include <dev/mmc/bridge.h>
  64 #include <dev/mmc/mmcreg.h>
  65 #include <dev/mmc/mmcbrvar.h>
  66
  67 #include <dev/sdhci/sdhci.h>
  68 #include "sdhci_if.h"
  69
  70 #include "bcm2835_dma.h"
  71 #include "bcm2835_vcbus.h"
  72
  73 #define BCM2835_DEFAULT_SDHCI_FREQ      50
  74
  75 #define BCM_SDHCI_BUFFER_SIZE           512
  76
  77 #ifdef DEBUG
  78 #define dprintf(fmt, args...) do { printf("%s(): ", __func__);   \
  79     printf(fmt,##args); } while (0)
  80 #else
  81 #define dprintf(fmt, args...)
  82 #endif
  83
  84 /*
  85  * Arasan HC seems to have problem with Data CRC on lower frequencies.
  86  * Use this tunable to cap initialization sequence frequency at higher
  87  * value. Default is standard 400kHz
  88  */
  89 static int bcm2835_sdhci_min_freq = 400000;
  90 static int bcm2835_sdhci_hs = 1;
  91 static int bcm2835_sdhci_pio_mode = 0;
  92
  93 TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq);
  94 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
  95 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
  96
  97 struct bcm_sdhci_dmamap_arg {
  98         bus_addr_t              sc_dma_busaddr;
  99 };
 100
 101 struct bcm_sdhci_softc {
 102         device_t                sc_dev;
 103         struct mtx              sc_mtx;
 104         struct resource *       sc_mem_res;
 105         struct resource *       sc_irq_res;
 106         bus_space_tag_t         sc_bst;
 107         bus_space_handle_t      sc_bsh;
 108         void *                  sc_intrhand;
 109         struct mmc_request *    sc_req;
 110         struct mmc_data *       sc_data;
 111         uint32_t                sc_flags;
 112 #define LPC_SD_FLAGS_IGNORECRC          (1 << 0)
 113         int                     sc_xfer_direction;
 114 #define DIRECTION_READ          0
 115 #define DIRECTION_WRITE         1
 116         int                     sc_xfer_done;
 117         int                     sc_bus_busy;
 118         struct sdhci_slot       sc_slot;
 119         int                     sc_dma_inuse;
 120         int                     sc_dma_ch;
 121         bus_dma_tag_t           sc_dma_tag;
 122         bus_dmamap_t            sc_dma_map;
 123         vm_paddr_t              sc_sdhci_buffer_phys;
 124 };
 125
 126 static int bcm_sdhci_probe(device_t);
 127 static int bcm_sdhci_attach(device_t);
 128 static int bcm_sdhci_detach(device_t);
 129 static void bcm_sdhci_intr(void *);
 130
 131 static int bcm_sdhci_get_ro(device_t, device_t);
 132 static void bcm_sdhci_dma_intr(int ch, void *arg);
 133
 134 #define bcm_sdhci_lock(_sc)                                             \
 135     mtx_lock(&_sc->sc_mtx);
 136 #define bcm_sdhci_unlock(_sc)                                           \
 137     mtx_unlock(&_sc->sc_mtx);
 138
 139 static void
 140 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
 141         int nseg, int err)
 142 {
 143         bus_addr_t *addr;
 144
 145         if (err)
 146                 return;
 147
 148         addr = (bus_addr_t*)arg;
 149         *addr = segs[0].ds_addr;
 150 }
 151
 152 static int
 153 bcm_sdhci_probe(device_t dev)
 154 {
 155
 156         if (!ofw_bus_status_okay(dev))
 157                 return (ENXIO);
 158
 159         if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
 160                 return (ENXIO);
 161
 162         device_set_desc(dev, "Broadcom 2708 SDHCI controller");
 163         return (BUS_PROBE_DEFAULT);
 164 }
 165
 166 static int
 167 bcm_sdhci_attach(device_t dev)
 168 {
 169         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 170         int rid, err;
 171         phandle_t node;
 172         pcell_t cell;
 173         int default_freq;
 174
 175         sc->sc_dev = dev;
 176         sc->sc_req = NULL;
 177         err = 0;
 178
 179         default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
 180         node = ofw_bus_get_node(sc->sc_dev);
 181         if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0)
 182                 default_freq = (int)fdt32_to_cpu(cell)/1000000;
 183
 184         dprintf("SDHCI frequency: %dMHz\n", default_freq);
 185
 186         mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF);
 187
 188         rid = 0;
 189         sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 190             RF_ACTIVE);
 191         if (!sc->sc_mem_res) {
 192                 device_printf(dev, "cannot allocate memory window\n");
 193                 err = ENXIO;
 194                 goto fail;
 195         }
 196
 197         sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
 198         sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
 199
 200         rid = 0;
 201         sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 202             RF_ACTIVE);
 203         if (!sc->sc_irq_res) {
 204                 device_printf(dev, "cannot allocate interrupt\n");
 205                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 206                 err = ENXIO;
 207                 goto fail;
 208         }
 209
 210         if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
 211             NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand))
 212         {
 213                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 214                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
 215                 device_printf(dev, "cannot setup interrupt handler\n");
 216                 err = ENXIO;
 217                 goto fail;
 218         }
 219
 220         if (!bcm2835_sdhci_pio_mode)
 221                 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
 222
 223         sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
 224         if (bcm2835_sdhci_hs)
 225                 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
 226         sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
 227         sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
 228                 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
 229                 | SDHCI_QUIRK_MISSING_CAPS;
 230
 231         sdhci_init_slot(dev, &sc->sc_slot, 0);
 232
 233         sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
 234         if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
 235                 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
 236         if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
 237                 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
 238         if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
 239                 goto fail;
 240
 241         bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
 242
 243         /* Allocate bus_dma resources. */
 244         err = bus_dma_tag_create(bus_get_dma_tag(dev),
 245             1, 0, BUS_SPACE_MAXADDR_32BIT,
 246             BUS_SPACE_MAXADDR, NULL, NULL,
 247             BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE,
 248             BUS_DMA_ALLOCNOW, NULL, NULL,
 249             &sc->sc_dma_tag);
 250
 251         if (err) {
 252                 device_printf(dev, "failed allocate DMA tag");
 253                 goto fail;
 254         }
 255
 256         err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
 257         if (err) {
 258                 device_printf(dev, "bus_dmamap_create failed\n");
 259                 goto fail;
 260         }
 261
 262         sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
 263             SDHCI_BUFFER);
 264
 265         bus_generic_probe(dev);
 266         bus_generic_attach(dev);
 267
 268         sdhci_start_slot(&sc->sc_slot);
 269
 270         return (0);
 271
 272 fail:
 273         if (sc->sc_intrhand)
 274                 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
 275         if (sc->sc_irq_res)
 276                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
 277         if (sc->sc_mem_res)
 278                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 279
 280         return (err);
 281 }
 282
 283 static int
 284 bcm_sdhci_detach(device_t dev)
 285 {
 286
 287         return (EBUSY);
 288 }
 289
 290 static void
 291 bcm_sdhci_intr(void *arg)
 292 {
 293         struct bcm_sdhci_softc *sc = arg;
 294
 295         sdhci_generic_intr(&sc->sc_slot);
 296 }
 297
 298 static int
 299 bcm_sdhci_get_ro(device_t bus, device_t child)
 300 {
 301
 302         return (0);
 303 }
 304
 305 static inline uint32_t
 306 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
 307 {
 308         uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
 309         return val;
 310 }
 311
 312 static inline void
 313 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
 314 {
 315         bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
 316
 317         if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL))
 318         {
 319                 int timeout = 100000;
 320                 while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)
 321                     && --timeout > 0)
 322                         continue;
 323
 324                 if (timeout <= 0)
 325                         printf("sdhci_brcm: writing 0x%X to reg 0x%X "
 326                                 "always gives 0x%X\n",
 327                                 val, (uint32_t)off,
 328                                 bus_space_read_4(sc->sc_bst, sc->sc_bsh, off));
 329         }
 330 }
 331
 332 static uint8_t
 333 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 334 {
 335         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 336         uint32_t val = RD4(sc, off & ~3);
 337
 338         return ((val >> (off & 3)*8) & 0xff);
 339 }
 340
 341 static uint16_t
 342 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 343 {
 344         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 345         uint32_t val = RD4(sc, off & ~3);
 346
 347         return ((val >> (off & 3)*8) & 0xffff);
 348 }
 349
 350 static uint32_t
 351 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 352 {
 353         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 354
 355         return RD4(sc, off);
 356 }
 357
 358 static void
 359 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
 360     uint32_t *data, bus_size_t count)
 361 {
 362         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 363
 364         bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
 365 }
 366
 367 static void
 368 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
 369 {
 370         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 371         uint32_t val32 = RD4(sc, off & ~3);
 372         val32 &= ~(0xff << (off & 3)*8);
 373         val32 |= (val << (off & 3)*8);
 374         WR4(sc, off & ~3, val32);
 375 }
 376
 377 static void
 378 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
 379 {
 380         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 381         static uint32_t cmd_and_trandfer_mode;
 382         uint32_t val32;
 383         if (off == SDHCI_COMMAND_FLAGS)
 384                 val32 = cmd_and_trandfer_mode;
 385         else
 386                 val32 = RD4(sc, off & ~3);
 387         val32 &= ~(0xffff << (off & 3)*8);
 388         val32 |= (val << (off & 3)*8);
 389         if (off == SDHCI_TRANSFER_MODE)
 390                 cmd_and_trandfer_mode = val32;
 391         else
 392                 WR4(sc, off & ~3, val32);
 393 }
 394
 395 static void
 396 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
 397 {
 398         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 399         WR4(sc, off, val);
 400 }
 401
 402 static void
 403 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
 404     uint32_t *data, bus_size_t count)
 405 {
 406         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 407
 408         bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
 409 }
 410
 411 static uint32_t
 412 bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot)
 413 {
 414
 415         return bcm2835_sdhci_min_freq;
 416 }
 417
 418 static void
 419 bcm_sdhci_dma_intr(int ch, void *arg)
 420 {
 421         struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
 422         struct sdhci_slot *slot = &sc->sc_slot;
 423         uint32_t reg, mask;
 424         bus_addr_t pmem;
 425         vm_paddr_t pdst, psrc;
 426         size_t len;
 427         int left, sync_op;
 428
 429         mtx_lock(&slot->mtx);
 430
 431         len = bcm_dma_length(sc->sc_dma_ch);
 432         if (slot->curcmd->data->flags & MMC_DATA_READ) {
 433                 sync_op = BUS_DMASYNC_POSTREAD;
 434                 mask = SDHCI_INT_DATA_AVAIL;
 435         } else {
 436                 sync_op = BUS_DMASYNC_POSTWRITE;
 437                 mask = SDHCI_INT_SPACE_AVAIL;
 438         }
 439         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
 440         bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
 441
 442         slot->offset += len;
 443         sc->sc_dma_inuse = 0;
 444
 445         left = min(BCM_SDHCI_BUFFER_SIZE,
 446             slot->curcmd->data->len - slot->offset);
 447
 448         /* DATA END? */
 449         reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
 450
 451         if (reg & SDHCI_INT_DATA_END) {
 452                 /* ACK for all outstanding interrupts */
 453                 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
 454
 455                 /* enable INT */
 456                 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
 457                     | SDHCI_INT_DATA_END;
 458                 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
 459                     slot->intmask);
 460
 461                 /* finish this data */
 462                 sdhci_finish_data(slot);
 463         }
 464         else {
 465                 /* already available? */
 466                 if (reg & mask) {
 467                         sc->sc_dma_inuse = 1;
 468
 469                         /* ACK for DATA_AVAIL or SPACE_AVAIL */
 470                         bcm_sdhci_write_4(slot->bus, slot,
 471                             SDHCI_INT_STATUS, mask);
 472
 473                         /* continue next DMA transfer */
 474                         bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
 475                             (uint8_t *)slot->curcmd->data->data +
 476                             slot->offset, left, bcm_dmamap_cb, &pmem, 0);
 477                         if (slot->curcmd->data->flags & MMC_DATA_READ) {
 478                                 psrc = sc->sc_sdhci_buffer_phys;
 479                                 pdst = pmem;
 480                                 sync_op = BUS_DMASYNC_PREREAD;
 481                         } else {
 482                                 psrc = pmem;
 483                                 pdst = sc->sc_sdhci_buffer_phys;
 484                                 sync_op = BUS_DMASYNC_PREWRITE;
 485                         }
 486                         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
 487                         if (bcm_dma_start(sc->sc_dma_ch, psrc, pdst, left)) {
 488                                 /* XXX stop xfer, other error recovery? */
 489                                 device_printf(sc->sc_dev, "failed DMA start\n");
 490                         }
 491                 } else {
 492                         /* wait for next data by INT */
 493
 494                         /* enable INT */
 495                         slot->intmask |= SDHCI_INT_DATA_AVAIL |
 496                             SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
 497                         bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
 498                             slot->intmask);
 499                 }
 500         }
 501
 502         mtx_unlock(&slot->mtx);
 503 }
 504
 505 static void
 506 bcm_sdhci_read_dma(struct sdhci_slot *slot)
 507 {
 508         struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
 509         size_t left;
 510         bus_addr_t paddr;
 511
 512         if (sc->sc_dma_inuse) {
 513                 device_printf(sc->sc_dev, "DMA in use\n");
 514                 return;
 515         }
 516
 517         sc->sc_dma_inuse = 1;
 518
 519         left = min(BCM_SDHCI_BUFFER_SIZE,
 520             slot->curcmd->data->len - slot->offset);
 521
 522         KASSERT((left & 3) == 0,
 523             ("%s: len = %d, not word-aligned", __func__, left));
 524
 525         bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
 526             BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
 527         bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
 528             BCM_DMA_INC_ADDR,
 529             (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
 530
 531         bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
 532             (uint8_t *)slot->curcmd->data->data + slot->offset, left,
 533             bcm_dmamap_cb, &paddr, 0);
 534
 535         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
 536             BUS_DMASYNC_PREREAD);
 537
 538         /* DMA start */
 539         if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys,
 540             paddr, left) != 0)
 541                 device_printf(sc->sc_dev, "failed DMA start\n");
 542 }
 543
 544 static void
 545 bcm_sdhci_write_dma(struct sdhci_slot *slot)
 546 {
 547         struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
 548         size_t left;
 549         bus_addr_t paddr;
 550
 551         if (sc->sc_dma_inuse) {
 552                 device_printf(sc->sc_dev, "DMA in use\n");
 553                 return;
 554         }
 555
 556         sc->sc_dma_inuse = 1;
 557
 558         left = min(BCM_SDHCI_BUFFER_SIZE,
 559             slot->curcmd->data->len - slot->offset);
 560
 561         KASSERT((left & 3) == 0,
 562             ("%s: len = %d, not word-aligned", __func__, left));
 563
 564         bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
 565             (uint8_t *)slot->curcmd->data->data + slot->offset, left,
 566             bcm_dmamap_cb, &paddr, 0);
 567
 568         bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
 569             BCM_DMA_INC_ADDR,
 570             (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
 571         bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
 572             BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
 573
 574         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
 575             BUS_DMASYNC_PREWRITE);
 576
 577         /* DMA start */
 578         if (bcm_dma_start(sc->sc_dma_ch, paddr,
 579             sc->sc_sdhci_buffer_phys, left) != 0)
 580                 device_printf(sc->sc_dev, "failed DMA start\n");
 581 }
 582
 583 static int
 584 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
 585 {
 586         size_t left;
 587
 588         /*
 589          * Do not use DMA for transfers less than block size or with a length
 590          * that is not a multiple of four.
 591          */
 592         left = min(BCM_DMA_BLOCK_SIZE,
 593             slot->curcmd->data->len - slot->offset);
 594         if (left < BCM_DMA_BLOCK_SIZE)
 595                 return (0);
 596         if (left & 0x03)
 597                 return (0);
 598
 599         return (1);
 600 }
 601
 602 static void
 603 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
 604     uint32_t *intmask)
 605 {
 606
 607         /* Disable INT */
 608         slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
 609         bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
 610
 611         /* DMA transfer FIFO 1KB */
 612         if (slot->curcmd->data->flags & MMC_DATA_READ)
 613                 bcm_sdhci_read_dma(slot);
 614         else
 615                 bcm_sdhci_write_dma(slot);
 616 }
 617
 618 static void
 619 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
 620 {
 621
 622         sdhci_finish_data(slot);
 623 }
 624
 625 static device_method_t bcm_sdhci_methods[] = {
 626         /* Device interface */
 627         DEVMETHOD(device_probe,         bcm_sdhci_probe),
 628         DEVMETHOD(device_attach,        bcm_sdhci_attach),
 629         DEVMETHOD(device_detach,        bcm_sdhci_detach),
 630
 631         /* Bus interface */
 632         DEVMETHOD(bus_read_ivar,        sdhci_generic_read_ivar),
 633         DEVMETHOD(bus_write_ivar,       sdhci_generic_write_ivar),
 634         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 635
 636         /* MMC bridge interface */
 637         DEVMETHOD(mmcbr_update_ios,     sdhci_generic_update_ios),
 638         DEVMETHOD(mmcbr_request,        sdhci_generic_request),
 639         DEVMETHOD(mmcbr_get_ro,         bcm_sdhci_get_ro),
 640         DEVMETHOD(mmcbr_acquire_host,   sdhci_generic_acquire_host),
 641         DEVMETHOD(mmcbr_release_host,   sdhci_generic_release_host),
 642
 643         DEVMETHOD(sdhci_min_freq,       bcm_sdhci_min_freq),
 644         /* Platform transfer methods */
 645         DEVMETHOD(sdhci_platform_will_handle,           bcm_sdhci_will_handle_transfer),
 646         DEVMETHOD(sdhci_platform_start_transfer,        bcm_sdhci_start_transfer),
 647         DEVMETHOD(sdhci_platform_finish_transfer,       bcm_sdhci_finish_transfer),
 648         /* SDHCI registers accessors */
 649         DEVMETHOD(sdhci_read_1,         bcm_sdhci_read_1),
 650         DEVMETHOD(sdhci_read_2,         bcm_sdhci_read_2),
 651         DEVMETHOD(sdhci_read_4,         bcm_sdhci_read_4),
 652         DEVMETHOD(sdhci_read_multi_4,   bcm_sdhci_read_multi_4),
 653         DEVMETHOD(sdhci_write_1,        bcm_sdhci_write_1),
 654         DEVMETHOD(sdhci_write_2,        bcm_sdhci_write_2),
 655         DEVMETHOD(sdhci_write_4,        bcm_sdhci_write_4),
 656         DEVMETHOD(sdhci_write_multi_4,  bcm_sdhci_write_multi_4),
 657
 658         { 0, 0 }
 659 };
 660
 661 static devclass_t bcm_sdhci_devclass;
 662
 663 static driver_t bcm_sdhci_driver = {
 664         "sdhci_bcm",
 665         bcm_sdhci_methods,
 666         sizeof(struct bcm_sdhci_softc),
 667 };
 668
 669 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0);
 670 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);