sys/arm/broadcom/bcm2835/bcm2835_sdhci.c

   1 /*-
   2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  */
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bio.h>
  33 #include <sys/bus.h>
  34 #include <sys/conf.h>
  35 #include <sys/endian.h>
  36 #include <sys/kernel.h>
  37 #include <sys/kthread.h>
  38 #include <sys/lock.h>
  39 #include <sys/malloc.h>
  40 #include <sys/module.h>
  41 #include <sys/mutex.h>
  42 #include <sys/queue.h>
  43 #include <sys/resource.h>
  44 #include <sys/rman.h>
  45 #include <sys/taskqueue.h>
  46 #include <sys/time.h>
  47 #include <sys/timetc.h>
  48 #include <sys/watchdog.h>
  49
  50 #include <sys/kdb.h>
  51
  52 #include <machine/bus.h>
  53 #include <machine/cpu.h>
  54 #include <machine/cpufunc.h>
  55 #include <machine/resource.h>
  56 #include <machine/intr.h>
  57
  58 #include <dev/fdt/fdt_common.h>
  59 #include <dev/ofw/ofw_bus.h>
  60 #include <dev/ofw/ofw_bus_subr.h>
  61
  62 #include <dev/mmc/bridge.h>
  63 #include <dev/mmc/mmcreg.h>
  64 #include <dev/mmc/mmcbrvar.h>
  65
  66 #include <dev/sdhci/sdhci.h>
  67 #include "sdhci_if.h"
  68
  69 #include "bcm2835_dma.h"
  70 #include "bcm2835_vcbus.h"
  71
  72 #define BCM2835_DEFAULT_SDHCI_FREQ      50
  73
  74 #define BCM_SDHCI_BUFFER_SIZE           512
  75
  76 #ifdef DEBUG
  77 #define dprintf(fmt, args...) do { printf("%s(): ", __func__);   \
  78     printf(fmt,##args); } while (0)
  79 #else
  80 #define dprintf(fmt, args...)
  81 #endif
  82
  83 /*
  84  * Arasan HC seems to have problem with Data CRC on lower frequencies.
  85  * Use this tunable to cap initialization sequence frequency at higher
  86  * value. Default is standard 400kHz
  87  */
  88 static int bcm2835_sdhci_min_freq = 400000;
  89 static int bcm2835_sdhci_hs = 1;
  90 static int bcm2835_sdhci_pio_mode = 0;
  91
  92 TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq);
  93 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
  94 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
  95
  96 struct bcm_sdhci_dmamap_arg {
  97         bus_addr_t              sc_dma_busaddr;
  98 };
  99
 100 struct bcm_sdhci_softc {
 101         device_t                sc_dev;
 102         struct mtx              sc_mtx;
 103         struct resource *       sc_mem_res;
 104         struct resource *       sc_irq_res;
 105         bus_space_tag_t         sc_bst;
 106         bus_space_handle_t      sc_bsh;
 107         void *                  sc_intrhand;
 108         struct mmc_request *    sc_req;
 109         struct mmc_data *       sc_data;
 110         uint32_t                sc_flags;
 111 #define LPC_SD_FLAGS_IGNORECRC          (1 << 0)
 112         int                     sc_xfer_direction;
 113 #define DIRECTION_READ          0
 114 #define DIRECTION_WRITE         1
 115         int                     sc_xfer_done;
 116         int                     sc_bus_busy;
 117         struct sdhci_slot       sc_slot;
 118         int                     sc_dma_inuse;
 119         int                     sc_dma_ch;
 120         bus_dma_tag_t           sc_dma_tag;
 121         bus_dmamap_t            sc_dma_map;
 122         vm_paddr_t              sc_sdhci_buffer_phys;
 123 };
 124
 125 static int bcm_sdhci_probe(device_t);
 126 static int bcm_sdhci_attach(device_t);
 127 static int bcm_sdhci_detach(device_t);
 128 static void bcm_sdhci_intr(void *);
 129
 130 static int bcm_sdhci_get_ro(device_t, device_t);
 131 static void bcm_sdhci_dma_intr(int ch, void *arg);
 132
 133 #define bcm_sdhci_lock(_sc)                                             \
 134     mtx_lock(&_sc->sc_mtx);
 135 #define bcm_sdhci_unlock(_sc)                                           \
 136     mtx_unlock(&_sc->sc_mtx);
 137
 138 static void
 139 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
 140         int nseg, int err)
 141 {
 142         bus_addr_t *addr;
 143
 144         if (err)
 145                 return;
 146
 147         addr = (bus_addr_t*)arg;
 148         *addr = segs[0].ds_addr;
 149 }
 150
 151 static int
 152 bcm_sdhci_probe(device_t dev)
 153 {
 154         if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
 155                 return (ENXIO);
 156
 157         device_set_desc(dev, "Broadcom 2708 SDHCI controller");
 158         return (BUS_PROBE_DEFAULT);
 159 }
 160
 161 static int
 162 bcm_sdhci_attach(device_t dev)
 163 {
 164         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 165         int rid, err;
 166         phandle_t node;
 167         pcell_t cell;
 168         int default_freq;
 169
 170         sc->sc_dev = dev;
 171         sc->sc_req = NULL;
 172         err = 0;
 173
 174         default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
 175         node = ofw_bus_get_node(sc->sc_dev);
 176         if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0)
 177                 default_freq = (int)fdt32_to_cpu(cell)/1000000;
 178
 179         dprintf("SDHCI frequency: %dMHz\n", default_freq);
 180
 181         mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF);
 182
 183         rid = 0;
 184         sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 185             RF_ACTIVE);
 186         if (!sc->sc_mem_res) {
 187                 device_printf(dev, "cannot allocate memory window\n");
 188                 err = ENXIO;
 189                 goto fail;
 190         }
 191
 192         sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
 193         sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
 194
 195         rid = 0;
 196         sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 197             RF_ACTIVE);
 198         if (!sc->sc_irq_res) {
 199                 device_printf(dev, "cannot allocate interrupt\n");
 200                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 201                 err = ENXIO;
 202                 goto fail;
 203         }
 204
 205         if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
 206             NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand))
 207         {
 208                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 209                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
 210                 device_printf(dev, "cannot setup interrupt handler\n");
 211                 err = ENXIO;
 212                 goto fail;
 213         }
 214
 215         if (!bcm2835_sdhci_pio_mode)
 216                 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
 217
 218         sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
 219         if (bcm2835_sdhci_hs)
 220                 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
 221         sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
 222         sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
 223                 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
 224                 | SDHCI_QUIRK_MISSING_CAPS;
 225
 226         sdhci_init_slot(dev, &sc->sc_slot, 0);
 227
 228         sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
 229         if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
 230                 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
 231         if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
 232                 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
 233         if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
 234                 goto fail;
 235
 236         bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
 237
 238         /* Allocate bus_dma resources. */
 239         err = bus_dma_tag_create(bus_get_dma_tag(dev),
 240             1, 0, BUS_SPACE_MAXADDR_32BIT,
 241             BUS_SPACE_MAXADDR, NULL, NULL,
 242             BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE,
 243             BUS_DMA_ALLOCNOW, NULL, NULL,
 244             &sc->sc_dma_tag);
 245
 246         if (err) {
 247                 device_printf(dev, "failed allocate DMA tag");
 248                 goto fail;
 249         }
 250
 251         err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
 252         if (err) {
 253                 device_printf(dev, "bus_dmamap_create failed\n");
 254                 goto fail;
 255         }
 256
 257         sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
 258             SDHCI_BUFFER);
 259
 260         bus_generic_probe(dev);
 261         bus_generic_attach(dev);
 262
 263         sdhci_start_slot(&sc->sc_slot);
 264
 265         return (0);
 266
 267 fail:
 268         if (sc->sc_intrhand)
 269                 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
 270         if (sc->sc_irq_res)
 271                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
 272         if (sc->sc_mem_res)
 273                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
 274
 275         return (err);
 276 }
 277
 278 static int
 279 bcm_sdhci_detach(device_t dev)
 280 {
 281
 282         return (EBUSY);
 283 }
 284
 285 static void
 286 bcm_sdhci_intr(void *arg)
 287 {
 288         struct bcm_sdhci_softc *sc = arg;
 289
 290         sdhci_generic_intr(&sc->sc_slot);
 291 }
 292
 293 static int
 294 bcm_sdhci_get_ro(device_t bus, device_t child)
 295 {
 296
 297         return (0);
 298 }
 299
 300 static inline uint32_t
 301 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
 302 {
 303         uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
 304         return val;
 305 }
 306
 307 static inline void
 308 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
 309 {
 310         bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
 311
 312         if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL))
 313         {
 314                 int timeout = 100000;
 315                 while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)
 316                     && --timeout > 0)
 317                         continue;
 318
 319                 if (timeout <= 0)
 320                         printf("sdhci_brcm: writing 0x%X to reg 0x%X "
 321                                 "always gives 0x%X\n",
 322                                 val, (uint32_t)off,
 323                                 bus_space_read_4(sc->sc_bst, sc->sc_bsh, off));
 324         }
 325 }
 326
 327 static uint8_t
 328 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 329 {
 330         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 331         uint32_t val = RD4(sc, off & ~3);
 332
 333         return ((val >> (off & 3)*8) & 0xff);
 334 }
 335
 336 static uint16_t
 337 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 338 {
 339         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 340         uint32_t val = RD4(sc, off & ~3);
 341
 342         return ((val >> (off & 3)*8) & 0xffff);
 343 }
 344
 345 static uint32_t
 346 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
 347 {
 348         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 349
 350         return RD4(sc, off);
 351 }
 352
 353 static void
 354 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
 355     uint32_t *data, bus_size_t count)
 356 {
 357         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 358
 359         bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
 360 }
 361
 362 static void
 363 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
 364 {
 365         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 366         uint32_t val32 = RD4(sc, off & ~3);
 367         val32 &= ~(0xff << (off & 3)*8);
 368         val32 |= (val << (off & 3)*8);
 369         WR4(sc, off & ~3, val32);
 370 }
 371
 372 static void
 373 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
 374 {
 375         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 376         static uint32_t cmd_and_trandfer_mode;
 377         uint32_t val32;
 378         if (off == SDHCI_COMMAND_FLAGS)
 379                 val32 = cmd_and_trandfer_mode;
 380         else
 381                 val32 = RD4(sc, off & ~3);
 382         val32 &= ~(0xffff << (off & 3)*8);
 383         val32 |= (val << (off & 3)*8);
 384         if (off == SDHCI_TRANSFER_MODE)
 385                 cmd_and_trandfer_mode = val32;
 386         else
 387                 WR4(sc, off & ~3, val32);
 388 }
 389
 390 static void
 391 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
 392 {
 393         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 394         WR4(sc, off, val);
 395 }
 396
 397 static void
 398 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
 399     uint32_t *data, bus_size_t count)
 400 {
 401         struct bcm_sdhci_softc *sc = device_get_softc(dev);
 402
 403         bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
 404 }
 405
 406 static uint32_t
 407 bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot)
 408 {
 409
 410         return bcm2835_sdhci_min_freq;
 411 }
 412
 413 static void
 414 bcm_sdhci_dma_intr(int ch, void *arg)
 415 {
 416         struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
 417         struct sdhci_slot *slot = &sc->sc_slot;
 418         uint32_t reg, mask;
 419         bus_addr_t pmem;
 420         vm_paddr_t pdst, psrc;
 421         size_t len;
 422         int left, sync_op;
 423
 424         mtx_lock(&slot->mtx);
 425
 426         len = bcm_dma_length(sc->sc_dma_ch);
 427         if (slot->curcmd->data->flags & MMC_DATA_READ) {
 428                 sync_op = BUS_DMASYNC_POSTREAD;
 429                 mask = SDHCI_INT_DATA_AVAIL;
 430         } else {
 431                 sync_op = BUS_DMASYNC_POSTWRITE;
 432                 mask = SDHCI_INT_SPACE_AVAIL;
 433         }
 434         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
 435         bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
 436
 437         slot->offset += len;
 438         sc->sc_dma_inuse = 0;
 439
 440         left = min(BCM_SDHCI_BUFFER_SIZE,
 441             slot->curcmd->data->len - slot->offset);
 442
 443         /* DATA END? */
 444         reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
 445
 446         if (reg & SDHCI_INT_DATA_END) {
 447                 /* ACK for all outstanding interrupts */
 448                 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
 449
 450                 /* enable INT */
 451                 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
 452                     | SDHCI_INT_DATA_END;
 453                 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
 454                     slot->intmask);
 455
 456                 /* finish this data */
 457                 sdhci_finish_data(slot);
 458         }
 459         else {
 460                 /* already available? */
 461                 if (reg & mask) {
 462                         sc->sc_dma_inuse = 1;
 463
 464                         /* ACK for DATA_AVAIL or SPACE_AVAIL */
 465                         bcm_sdhci_write_4(slot->bus, slot,
 466                             SDHCI_INT_STATUS, mask);
 467
 468                         /* continue next DMA transfer */
 469                         bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
 470                             (uint8_t *)slot->curcmd->data->data +
 471                             slot->offset, left, bcm_dmamap_cb, &pmem, 0);
 472                         if (slot->curcmd->data->flags & MMC_DATA_READ) {
 473                                 psrc = sc->sc_sdhci_buffer_phys;
 474                                 pdst = pmem;
 475                                 sync_op = BUS_DMASYNC_PREREAD;
 476                         } else {
 477                                 psrc = pmem;
 478                                 pdst = sc->sc_sdhci_buffer_phys;
 479                                 sync_op = BUS_DMASYNC_PREWRITE;
 480                         }
 481                         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
 482                         if (bcm_dma_start(sc->sc_dma_ch, psrc, pdst, left)) {
 483                                 /* XXX stop xfer, other error recovery? */
 484                                 device_printf(sc->sc_dev, "failed DMA start\n");
 485                         }
 486                 } else {
 487                         /* wait for next data by INT */
 488
 489                         /* enable INT */
 490                         slot->intmask |= SDHCI_INT_DATA_AVAIL |
 491                             SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
 492                         bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
 493                             slot->intmask);
 494                 }
 495         }
 496
 497         mtx_unlock(&slot->mtx);
 498 }
 499
 500 static void
 501 bcm_sdhci_read_dma(struct sdhci_slot *slot)
 502 {
 503         struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
 504         size_t left;
 505         bus_addr_t paddr;
 506
 507         if (sc->sc_dma_inuse) {
 508                 device_printf(sc->sc_dev, "DMA in use\n");
 509                 return;
 510         }
 511
 512         sc->sc_dma_inuse = 1;
 513
 514         left = min(BCM_SDHCI_BUFFER_SIZE,
 515             slot->curcmd->data->len - slot->offset);
 516
 517         KASSERT((left & 3) == 0,
 518             ("%s: len = %d, not word-aligned", __func__, left));
 519
 520         bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
 521             BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
 522         bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
 523             BCM_DMA_INC_ADDR,
 524             (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
 525
 526         bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
 527             (uint8_t *)slot->curcmd->data->data + slot->offset, left,
 528             bcm_dmamap_cb, &paddr, 0);
 529
 530         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
 531             BUS_DMASYNC_PREREAD);
 532
 533         /* DMA start */
 534         if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys,
 535             paddr, left) != 0)
 536                 device_printf(sc->sc_dev, "failed DMA start\n");
 537 }
 538
 539 static void
 540 bcm_sdhci_write_dma(struct sdhci_slot *slot)
 541 {
 542         struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
 543         size_t left;
 544         bus_addr_t paddr;
 545
 546         if (sc->sc_dma_inuse) {
 547                 device_printf(sc->sc_dev, "DMA in use\n");
 548                 return;
 549         }
 550
 551         sc->sc_dma_inuse = 1;
 552
 553         left = min(BCM_SDHCI_BUFFER_SIZE,
 554             slot->curcmd->data->len - slot->offset);
 555
 556         KASSERT((left & 3) == 0,
 557             ("%s: len = %d, not word-aligned", __func__, left));
 558
 559         bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
 560             (uint8_t *)slot->curcmd->data->data + slot->offset, left,
 561             bcm_dmamap_cb, &paddr, 0);
 562
 563         bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
 564             BCM_DMA_INC_ADDR,
 565             (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
 566         bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
 567             BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
 568
 569         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
 570             BUS_DMASYNC_PREWRITE);
 571
 572         /* DMA start */
 573         if (bcm_dma_start(sc->sc_dma_ch, paddr,
 574             sc->sc_sdhci_buffer_phys, left) != 0)
 575                 device_printf(sc->sc_dev, "failed DMA start\n");
 576 }
 577
 578 static int
 579 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
 580 {
 581         size_t left;
 582
 583         /*
 584          * Do not use DMA for transfers less than block size or with a length
 585          * that is not a multiple of four.
 586          */
 587         left = min(BCM_DMA_BLOCK_SIZE,
 588             slot->curcmd->data->len - slot->offset);
 589         if (left < BCM_DMA_BLOCK_SIZE)
 590                 return (0);
 591         if (left & 0x03)
 592                 return (0);
 593
 594         return (1);
 595 }
 596
 597 static void
 598 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
 599     uint32_t *intmask)
 600 {
 601
 602         /* Disable INT */
 603         slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
 604         bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
 605
 606         /* DMA transfer FIFO 1KB */
 607         if (slot->curcmd->data->flags & MMC_DATA_READ)
 608                 bcm_sdhci_read_dma(slot);
 609         else
 610                 bcm_sdhci_write_dma(slot);
 611 }
 612
 613 static void
 614 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
 615 {
 616
 617         sdhci_finish_data(slot);
 618 }
 619
 620 static device_method_t bcm_sdhci_methods[] = {
 621         /* Device interface */
 622         DEVMETHOD(device_probe,         bcm_sdhci_probe),
 623         DEVMETHOD(device_attach,        bcm_sdhci_attach),
 624         DEVMETHOD(device_detach,        bcm_sdhci_detach),
 625
 626         /* Bus interface */
 627         DEVMETHOD(bus_read_ivar,        sdhci_generic_read_ivar),
 628         DEVMETHOD(bus_write_ivar,       sdhci_generic_write_ivar),
 629         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 630
 631         /* MMC bridge interface */
 632         DEVMETHOD(mmcbr_update_ios,     sdhci_generic_update_ios),
 633         DEVMETHOD(mmcbr_request,        sdhci_generic_request),
 634         DEVMETHOD(mmcbr_get_ro,         bcm_sdhci_get_ro),
 635         DEVMETHOD(mmcbr_acquire_host,   sdhci_generic_acquire_host),
 636         DEVMETHOD(mmcbr_release_host,   sdhci_generic_release_host),
 637
 638         DEVMETHOD(sdhci_min_freq,       bcm_sdhci_min_freq),
 639         /* Platform transfer methods */
 640         DEVMETHOD(sdhci_platform_will_handle,           bcm_sdhci_will_handle_transfer),
 641         DEVMETHOD(sdhci_platform_start_transfer,        bcm_sdhci_start_transfer),
 642         DEVMETHOD(sdhci_platform_finish_transfer,       bcm_sdhci_finish_transfer),
 643         /* SDHCI registers accessors */
 644         DEVMETHOD(sdhci_read_1,         bcm_sdhci_read_1),
 645         DEVMETHOD(sdhci_read_2,         bcm_sdhci_read_2),
 646         DEVMETHOD(sdhci_read_4,         bcm_sdhci_read_4),
 647         DEVMETHOD(sdhci_read_multi_4,   bcm_sdhci_read_multi_4),
 648         DEVMETHOD(sdhci_write_1,        bcm_sdhci_write_1),
 649         DEVMETHOD(sdhci_write_2,        bcm_sdhci_write_2),
 650         DEVMETHOD(sdhci_write_4,        bcm_sdhci_write_4),
 651         DEVMETHOD(sdhci_write_multi_4,  bcm_sdhci_write_multi_4),
 652
 653         { 0, 0 }
 654 };
 655
 656 static devclass_t bcm_sdhci_devclass;
 657
 658 static driver_t bcm_sdhci_driver = {
 659         "sdhci_bcm",
 660         bcm_sdhci_methods,
 661         sizeof(struct bcm_sdhci_softc),
 662 };
 663
 664 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0);
 665 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);