2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
32 #include <sys/callout.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/stdarg.h>
47 #include <dev/mmc/bridge.h>
48 #include <dev/mmc/mmcreg.h>
49 #include <dev/mmc/mmcbrvar.h>
58 device_t dev; /* Controller device */
59 struct resource *irq_res; /* IRQ resource */
61 void *intrhand; /* Interrupt handle */
63 int num_slots; /* Number of slots on this controller */
64 struct sdhci_slot slots[6];
67 static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
70 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
71 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
73 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
74 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
75 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
76 #define RD_MULTI_4(slot, off, ptr, count) \
77 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
79 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
80 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
81 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
82 #define WR_MULTI_4(slot, off, ptr, count) \
83 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
85 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
86 static void sdhci_start(struct sdhci_slot *slot);
87 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
89 static void sdhci_card_task(void *, int);
92 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
93 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
94 #define SDHCI_LOCK_INIT(_slot) \
95 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
96 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
97 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
98 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
100 #define SDHCI_DEFAULT_MAX_FREQ 50
102 #define SDHCI_200_MAX_DIVIDER 256
103 #define SDHCI_300_MAX_DIVIDER 2046
106 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
109 printf("getaddr: error %d\n", error);
112 *(bus_addr_t *)arg = segs[0].ds_addr;
116 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
121 retval = printf("%s-slot%d: ",
122 device_get_nameunit(slot->bus), slot->num);
125 retval += vprintf(fmt, ap);
131 sdhci_dumpregs(struct sdhci_slot *slot)
134 "============== REGISTER DUMP ==============\n");
136 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
137 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
138 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
139 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
140 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
141 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
142 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
143 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
144 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
145 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
146 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
147 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
148 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
149 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
150 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
151 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
152 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
153 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
154 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n",
155 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
158 "===========================================\n");
162 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
167 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
168 if (!(RD4(slot, SDHCI_PRESENT_STATE) &
173 /* Some controllers need this kick or reset won't work. */
174 if ((mask & SDHCI_RESET_ALL) == 0 &&
175 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
178 /* This is to force an update */
181 sdhci_set_clock(slot, clock);
184 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
186 if (mask & SDHCI_RESET_ALL) {
191 /* Wait max 100 ms */
193 /* Controller clears the bits when it's done */
194 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) {
197 "Reset 0x%x never completed - 0x%x.\n",
198 (int)mask, (int)res);
199 sdhci_dumpregs(slot);
208 sdhci_init(struct sdhci_slot *slot)
211 sdhci_reset(slot, SDHCI_RESET_ALL);
213 /* Enable interrupts. */
214 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
215 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
216 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
217 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
218 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
219 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
221 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
222 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
226 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
233 if (clock == slot->clock)
237 /* Turn off the clock. */
238 WR2(slot, SDHCI_CLOCK_CONTROL, 0);
239 /* If no clock requested - left it so. */
243 /* Recalculate timeout clock frequency based on the new sd clock. */
244 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
245 slot->timeout_clk = slot->clock / 1000;
247 if (slot->version < SDHCI_SPEC_300) {
248 /* Looking for highest freq <= clock. */
250 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
255 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
259 /* Version 3.0 divisors are multiples of two up to 1023*2 */
260 if (clock >= slot->max_clk)
263 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
264 if ((slot->max_clk / div) <= clock)
271 if (bootverbose || sdhci_debug)
272 slot_printf(slot, "Divider %d for freq %d (max %d)\n",
273 div, clock, slot->max_clk);
275 /* Now we have got divider, set it. */
276 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
277 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
278 << SDHCI_DIVIDER_HI_SHIFT;
280 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
282 clk |= SDHCI_CLOCK_INT_EN;
283 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
284 /* Wait up to 10 ms until it stabilize. */
286 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
287 & SDHCI_CLOCK_INT_STABLE)) {
290 "Internal clock never stabilised.\n");
291 sdhci_dumpregs(slot);
297 /* Pass clock signal to the bus. */
298 clk |= SDHCI_CLOCK_CARD_EN;
299 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
303 sdhci_set_power(struct sdhci_slot *slot, u_char power)
307 if (slot->power == power)
312 /* Turn off the power. */
314 WR1(slot, SDHCI_POWER_CONTROL, pwr);
315 /* If power down requested - left it so. */
319 switch (1 << power) {
320 case MMC_OCR_LOW_VOLTAGE:
321 pwr |= SDHCI_POWER_180;
323 case MMC_OCR_290_300:
324 case MMC_OCR_300_310:
325 pwr |= SDHCI_POWER_300;
327 case MMC_OCR_320_330:
328 case MMC_OCR_330_340:
329 pwr |= SDHCI_POWER_330;
332 WR1(slot, SDHCI_POWER_CONTROL, pwr);
333 /* Turn on the power. */
334 pwr |= SDHCI_POWER_ON;
335 WR1(slot, SDHCI_POWER_CONTROL, pwr);
339 sdhci_read_block_pio(struct sdhci_slot *slot)
345 buffer = slot->curcmd->data->data;
346 buffer += slot->offset;
347 /* Transfer one block at a time. */
348 left = min(512, slot->curcmd->data->len - slot->offset);
349 slot->offset += left;
351 /* If we are too fast, broken controllers return zeroes. */
352 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
354 /* Handle unaligned and aligned buffer cases. */
355 if ((intptr_t)buffer & 3) {
357 data = RD4(slot, SDHCI_BUFFER);
359 buffer[1] = (data >> 8);
360 buffer[2] = (data >> 16);
361 buffer[3] = (data >> 24);
366 RD_MULTI_4(slot, SDHCI_BUFFER,
367 (uint32_t *)buffer, left >> 2);
370 /* Handle uneven size case. */
372 data = RD4(slot, SDHCI_BUFFER);
382 sdhci_write_block_pio(struct sdhci_slot *slot)
388 buffer = slot->curcmd->data->data;
389 buffer += slot->offset;
390 /* Transfer one block at a time. */
391 left = min(512, slot->curcmd->data->len - slot->offset);
392 slot->offset += left;
394 /* Handle unaligned and aligned buffer cases. */
395 if ((intptr_t)buffer & 3) {
403 WR4(slot, SDHCI_BUFFER, data);
406 WR_MULTI_4(slot, SDHCI_BUFFER,
407 (uint32_t *)buffer, left >> 2);
410 /* Handle uneven size case. */
417 WR4(slot, SDHCI_BUFFER, data);
422 sdhci_transfer_pio(struct sdhci_slot *slot)
425 /* Read as many blocks as possible. */
426 if (slot->curcmd->data->flags & MMC_DATA_READ) {
427 while (RD4(slot, SDHCI_PRESENT_STATE) &
428 SDHCI_DATA_AVAILABLE) {
429 sdhci_read_block_pio(slot);
430 if (slot->offset >= slot->curcmd->data->len)
434 while (RD4(slot, SDHCI_PRESENT_STATE) &
435 SDHCI_SPACE_AVAILABLE) {
436 sdhci_write_block_pio(slot);
437 if (slot->offset >= slot->curcmd->data->len)
444 sdhci_card_delay(void *arg)
446 struct sdhci_slot *slot = arg;
448 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
452 sdhci_card_task(void *arg, int pending)
454 struct sdhci_slot *slot = arg;
457 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
458 if (slot->dev == NULL) {
459 /* If card is present - attach mmc bus. */
460 slot->dev = device_add_child(slot->bus, "mmc", -1);
461 device_set_ivars(slot->dev, slot);
463 device_probe_and_attach(slot->dev);
467 if (slot->dev != NULL) {
468 /* If no card present - detach mmc bus. */
469 device_t d = slot->dev;
472 device_delete_child(slot->bus, d);
479 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
484 SDHCI_LOCK_INIT(slot);
488 /* Allocate DMA tag. */
489 err = bus_dma_tag_create(bus_get_dma_tag(dev),
490 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
491 BUS_SPACE_MAXADDR, NULL, NULL,
492 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
493 BUS_DMA_ALLOCNOW, NULL, NULL,
496 device_printf(dev, "Can't create DMA tag\n");
497 SDHCI_LOCK_DESTROY(slot);
500 /* Allocate DMA memory. */
501 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
502 BUS_DMA_NOWAIT, &slot->dmamap);
504 device_printf(dev, "Can't alloc DMA memory\n");
505 SDHCI_LOCK_DESTROY(slot);
508 /* Map the memory. */
509 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
510 (void *)slot->dmamem, DMA_BLOCK_SIZE,
511 sdhci_getaddr, &slot->paddr, 0);
512 if (err != 0 || slot->paddr == 0) {
513 device_printf(dev, "Can't load DMA memory\n");
514 SDHCI_LOCK_DESTROY(slot);
521 /* Initialize slot. */
523 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
524 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
525 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
528 caps = RD4(slot, SDHCI_CAPABILITIES);
529 /* Calculate base clock frequency. */
530 if (slot->version >= SDHCI_SPEC_300)
531 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
532 SDHCI_CLOCK_BASE_SHIFT;
534 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
535 SDHCI_CLOCK_BASE_SHIFT;
537 slot->max_clk = freq * 1000000;
539 * If the frequency wasn't in the capabilities and the hardware driver
540 * hasn't already set max_clk we're probably not going to work right
541 * with an assumption, so complain about it.
543 if (slot->max_clk == 0) {
544 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
545 device_printf(dev, "Hardware doesn't specify base clock "
546 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
548 /* Calculate timeout clock frequency. */
549 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
550 slot->timeout_clk = slot->max_clk / 1000;
553 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
554 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
555 slot->timeout_clk *= 1000;
558 * If the frequency wasn't in the capabilities and the hardware driver
559 * hasn't already set timeout_clk we'll probably work okay using the
560 * max timeout, but still mention it.
562 if (slot->timeout_clk == 0) {
563 device_printf(dev, "Hardware doesn't specify timeout clock "
564 "frequency, setting BROKEN_TIMEOUT quirk.\n");
565 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
568 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
569 slot->host.f_max = slot->max_clk;
570 slot->host.host_ocr = 0;
571 if (caps & SDHCI_CAN_VDD_330)
572 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
573 if (caps & SDHCI_CAN_VDD_300)
574 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
575 if (caps & SDHCI_CAN_VDD_180)
576 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
577 if (slot->host.host_ocr == 0) {
578 device_printf(dev, "Hardware doesn't report any "
579 "support voltages.\n");
581 slot->host.caps = MMC_CAP_4_BIT_DATA;
582 if (caps & SDHCI_CAN_DO_HISPD)
583 slot->host.caps |= MMC_CAP_HSPEED;
584 /* Decide if we have usable DMA. */
585 if (caps & SDHCI_CAN_DO_DMA)
586 slot->opt |= SDHCI_HAVE_DMA;
588 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
589 slot->opt &= ~SDHCI_HAVE_DMA;
590 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
591 slot->opt |= SDHCI_HAVE_DMA;
594 * Use platform-provided transfer backend
595 * with PIO as a fallback mechanism
597 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
598 slot->opt &= ~SDHCI_HAVE_DMA;
600 if (bootverbose || sdhci_debug) {
601 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
602 slot->max_clk / 1000000,
603 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
604 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
605 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
606 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
607 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
608 sdhci_dumpregs(slot);
611 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
612 callout_init(&slot->card_callout, 1);
613 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
618 sdhci_start_slot(struct sdhci_slot *slot)
620 sdhci_card_task(slot, 0);
624 sdhci_cleanup_slot(struct sdhci_slot *slot)
628 callout_drain(&slot->timeout_callout);
629 callout_drain(&slot->card_callout);
630 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
637 device_delete_child(slot->bus, d);
640 sdhci_reset(slot, SDHCI_RESET_ALL);
642 bus_dmamap_unload(slot->dmatag, slot->dmamap);
643 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
644 bus_dma_tag_destroy(slot->dmatag);
646 SDHCI_LOCK_DESTROY(slot);
652 sdhci_generic_suspend(struct sdhci_slot *slot)
654 sdhci_reset(slot, SDHCI_RESET_ALL);
660 sdhci_generic_resume(struct sdhci_slot *slot)
668 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot)
670 if (slot->version >= SDHCI_SPEC_300)
671 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
673 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
677 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
679 struct sdhci_slot *slot = device_get_ivars(reqdev);
680 struct mmc_ios *ios = &slot->host.ios;
683 /* Do full reset on bus power down to clear from any state. */
684 if (ios->power_mode == power_off) {
685 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
688 /* Configure the bus. */
689 sdhci_set_clock(slot, ios->clock);
690 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd);
691 if (ios->bus_width == bus_width_4)
692 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
694 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
695 if (ios->timing == bus_timing_hs)
696 slot->hostctrl |= SDHCI_CTRL_HISPD;
698 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
699 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
700 /* Some controllers like reset after bus changes. */
701 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
702 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
709 sdhci_req_done(struct sdhci_slot *slot)
711 struct mmc_request *req;
713 if (slot->req != NULL && slot->curcmd != NULL) {
714 callout_stop(&slot->timeout_callout);
723 sdhci_timeout(void *arg)
725 struct sdhci_slot *slot = arg;
727 if (slot->curcmd != NULL) {
728 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
729 slot->curcmd->error = MMC_ERR_TIMEOUT;
730 sdhci_req_done(slot);
735 sdhci_set_transfer_mode(struct sdhci_slot *slot,
736 struct mmc_data *data)
743 mode = SDHCI_TRNS_BLK_CNT_EN;
745 mode |= SDHCI_TRNS_MULTI;
746 if (data->flags & MMC_DATA_READ)
747 mode |= SDHCI_TRNS_READ;
749 mode |= SDHCI_TRNS_ACMD12;
750 if (slot->flags & SDHCI_USE_DMA)
751 mode |= SDHCI_TRNS_DMA;
753 WR2(slot, SDHCI_TRANSFER_MODE, mode);
757 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
760 uint32_t mask, state;
765 cmd->error = MMC_ERR_NONE;
767 /* This flags combination is not supported by controller. */
768 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
769 slot_printf(slot, "Unsupported response type!\n");
770 cmd->error = MMC_ERR_FAILED;
771 sdhci_req_done(slot);
775 /* Read controller present state. */
776 state = RD4(slot, SDHCI_PRESENT_STATE);
777 /* Do not issue command if there is no card, clock or power.
778 * Controller will not detect timeout without clock active. */
779 if ((state & SDHCI_CARD_PRESENT) == 0 ||
782 cmd->error = MMC_ERR_FAILED;
783 sdhci_req_done(slot);
786 /* Always wait for free CMD bus. */
787 mask = SDHCI_CMD_INHIBIT;
788 /* Wait for free DAT if we have data or busy signal. */
789 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
790 mask |= SDHCI_DAT_INHIBIT;
791 /* We shouldn't wait for DAT for stop commands. */
792 if (cmd == slot->req->stop)
793 mask &= ~SDHCI_DAT_INHIBIT;
795 * Wait for bus no more then 250 ms. Typically there will be no wait
796 * here at all, but when writing a crash dump we may be bypassing the
797 * host platform's interrupt handler, and in some cases that handler
798 * may be working around hardware quirks such as not respecting r1b
799 * busy indications. In those cases, this wait-loop serves the purpose
800 * of waiting for the prior command and data transfers to be done, and
801 * SD cards are allowed to take up to 250ms for write and erase ops.
802 * (It's usually more like 20-30ms in the real world.)
805 while (state & mask) {
807 slot_printf(slot, "Controller never released "
808 "inhibit bit(s).\n");
809 sdhci_dumpregs(slot);
810 cmd->error = MMC_ERR_FAILED;
811 sdhci_req_done(slot);
816 state = RD4(slot, SDHCI_PRESENT_STATE);
819 /* Prepare command flags. */
820 if (!(cmd->flags & MMC_RSP_PRESENT))
821 flags = SDHCI_CMD_RESP_NONE;
822 else if (cmd->flags & MMC_RSP_136)
823 flags = SDHCI_CMD_RESP_LONG;
824 else if (cmd->flags & MMC_RSP_BUSY)
825 flags = SDHCI_CMD_RESP_SHORT_BUSY;
827 flags = SDHCI_CMD_RESP_SHORT;
828 if (cmd->flags & MMC_RSP_CRC)
829 flags |= SDHCI_CMD_CRC;
830 if (cmd->flags & MMC_RSP_OPCODE)
831 flags |= SDHCI_CMD_INDEX;
833 flags |= SDHCI_CMD_DATA;
834 if (cmd->opcode == MMC_STOP_TRANSMISSION)
835 flags |= SDHCI_CMD_TYPE_ABORT;
837 sdhci_start_data(slot, cmd->data);
839 * Interrupt aggregation: To reduce total number of interrupts
840 * group response interrupt with data interrupt when possible.
841 * If there going to be data interrupt, mask response one.
843 if (slot->data_done == 0) {
844 WR4(slot, SDHCI_SIGNAL_ENABLE,
845 slot->intmask &= ~SDHCI_INT_RESPONSE);
847 /* Set command argument. */
848 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
849 /* Set data transfer mode. */
850 sdhci_set_transfer_mode(slot, cmd->data);
852 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
853 /* Start timeout callout. */
854 callout_reset(&slot->timeout_callout, 2*hz, sdhci_timeout, slot);
858 sdhci_finish_command(struct sdhci_slot *slot)
863 /* Interrupt aggregation: Restore command interrupt.
864 * Main restore point for the case when command interrupt
866 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
867 /* In case of error - reset host and return. */
868 if (slot->curcmd->error) {
869 sdhci_reset(slot, SDHCI_RESET_CMD);
870 sdhci_reset(slot, SDHCI_RESET_DATA);
874 /* If command has response - fetch it. */
875 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
876 if (slot->curcmd->flags & MMC_RSP_136) {
877 /* CRC is stripped so we need one byte shift. */
879 for (i = 0; i < 4; i++) {
880 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
881 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
882 slot->curcmd->resp[3 - i] = val;
884 slot->curcmd->resp[3 - i] =
890 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
892 /* If data ready - finish. */
898 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
900 uint32_t target_timeout, current_timeout;
903 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
910 /* Calculate and set data timeout.*/
911 /* XXX: We should have this from mmc layer, now assume 1 sec. */
912 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
915 target_timeout = 1000000;
917 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
918 while (current_timeout < target_timeout && div < 0xE) {
920 current_timeout <<= 1;
922 /* Compensate for an off-by-one error in the CaFe chip.*/
924 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
928 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
933 /* Use DMA if possible. */
934 if ((slot->opt & SDHCI_HAVE_DMA))
935 slot->flags |= SDHCI_USE_DMA;
936 /* If data is small, broken DMA may return zeroes instead of data, */
937 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
939 slot->flags &= ~SDHCI_USE_DMA;
940 /* Some controllers require even block sizes. */
941 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
943 slot->flags &= ~SDHCI_USE_DMA;
944 /* Load DMA buffer. */
945 if (slot->flags & SDHCI_USE_DMA) {
946 if (data->flags & MMC_DATA_READ)
947 bus_dmamap_sync(slot->dmatag, slot->dmamap,
948 BUS_DMASYNC_PREREAD);
950 memcpy(slot->dmamem, data->data,
951 (data->len < DMA_BLOCK_SIZE) ?
952 data->len : DMA_BLOCK_SIZE);
953 bus_dmamap_sync(slot->dmatag, slot->dmamap,
954 BUS_DMASYNC_PREWRITE);
956 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
957 /* Interrupt aggregation: Mask border interrupt
958 * for the last page and unmask else. */
959 if (data->len == DMA_BLOCK_SIZE)
960 slot->intmask &= ~SDHCI_INT_DMA_END;
962 slot->intmask |= SDHCI_INT_DMA_END;
963 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
965 /* Current data offset for both PIO and DMA. */
967 /* Set block size and request IRQ on 4K border. */
968 WR2(slot, SDHCI_BLOCK_SIZE,
969 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
970 /* Set block count. */
971 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
975 sdhci_finish_data(struct sdhci_slot *slot)
977 struct mmc_data *data = slot->curcmd->data;
980 /* Interrupt aggregation: Restore command interrupt.
981 * Auxiliary restore point for the case when data interrupt
983 if (!slot->cmd_done) {
984 WR4(slot, SDHCI_SIGNAL_ENABLE,
985 slot->intmask |= SDHCI_INT_RESPONSE);
987 /* Unload rest of data from DMA buffer. */
988 if (slot->flags & SDHCI_USE_DMA) {
989 if (data->flags & MMC_DATA_READ) {
990 size_t left = data->len - slot->offset;
991 bus_dmamap_sync(slot->dmatag, slot->dmamap,
992 BUS_DMASYNC_POSTREAD);
993 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
994 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
996 bus_dmamap_sync(slot->dmatag, slot->dmamap,
997 BUS_DMASYNC_POSTWRITE);
999 /* If there was error - reset the host. */
1000 if (slot->curcmd->error) {
1001 sdhci_reset(slot, SDHCI_RESET_CMD);
1002 sdhci_reset(slot, SDHCI_RESET_DATA);
1006 /* If we already have command response - finish. */
1012 sdhci_start(struct sdhci_slot *slot)
1014 struct mmc_request *req;
1020 if (!(slot->flags & CMD_STARTED)) {
1021 slot->flags |= CMD_STARTED;
1022 sdhci_start_command(slot, req->cmd);
1025 /* We don't need this until using Auto-CMD12 feature
1026 if (!(slot->flags & STOP_STARTED) && req->stop) {
1027 slot->flags |= STOP_STARTED;
1028 sdhci_start_command(slot, req->stop);
1032 if (sdhci_debug > 1)
1033 slot_printf(slot, "result: %d\n", req->cmd->error);
1034 if (!req->cmd->error &&
1035 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1036 sdhci_reset(slot, SDHCI_RESET_CMD);
1037 sdhci_reset(slot, SDHCI_RESET_DATA);
1040 sdhci_req_done(slot);
1044 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1046 struct sdhci_slot *slot = device_get_ivars(reqdev);
1049 if (slot->req != NULL) {
1053 if (sdhci_debug > 1) {
1054 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1055 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1056 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1057 (req->cmd->data)?req->cmd->data->flags:0);
1064 while (slot->req != NULL) {
1065 sdhci_generic_intr(slot);
1073 sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1075 struct sdhci_slot *slot = device_get_ivars(reqdev);
1079 val = RD4(slot, SDHCI_PRESENT_STATE);
1081 return (!(val & SDHCI_WRITE_PROTECT));
1085 sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1087 struct sdhci_slot *slot = device_get_ivars(reqdev);
1091 while (slot->bus_busy)
1092 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1095 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1101 sdhci_generic_release_host(device_t brdev, device_t reqdev)
1103 struct sdhci_slot *slot = device_get_ivars(reqdev);
1106 /* Deactivate led. */
1107 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1115 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1118 if (!slot->curcmd) {
1119 slot_printf(slot, "Got command interrupt 0x%08x, but "
1120 "there is no active command.\n", intmask);
1121 sdhci_dumpregs(slot);
1124 if (intmask & SDHCI_INT_TIMEOUT)
1125 slot->curcmd->error = MMC_ERR_TIMEOUT;
1126 else if (intmask & SDHCI_INT_CRC)
1127 slot->curcmd->error = MMC_ERR_BADCRC;
1128 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1129 slot->curcmd->error = MMC_ERR_FIFO;
1131 sdhci_finish_command(slot);
1135 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1138 if (!slot->curcmd) {
1139 slot_printf(slot, "Got data interrupt 0x%08x, but "
1140 "there is no active command.\n", intmask);
1141 sdhci_dumpregs(slot);
1144 if (slot->curcmd->data == NULL &&
1145 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1146 slot_printf(slot, "Got data interrupt 0x%08x, but "
1147 "there is no active data operation.\n",
1149 sdhci_dumpregs(slot);
1152 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1153 slot->curcmd->error = MMC_ERR_TIMEOUT;
1154 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1155 slot->curcmd->error = MMC_ERR_BADCRC;
1156 if (slot->curcmd->data == NULL &&
1157 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1158 SDHCI_INT_DMA_END))) {
1159 slot_printf(slot, "Got data interrupt 0x%08x, but "
1160 "there is busy-only command.\n", intmask);
1161 sdhci_dumpregs(slot);
1162 slot->curcmd->error = MMC_ERR_INVALID;
1164 if (slot->curcmd->error) {
1165 /* No need to continue after any error. */
1166 if (slot->flags & PLATFORM_DATA_STARTED) {
1167 slot->flags &= ~PLATFORM_DATA_STARTED;
1168 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1170 sdhci_finish_data(slot);
1174 /* Handle PIO interrupt. */
1175 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1176 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1177 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1178 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask);
1179 slot->flags |= PLATFORM_DATA_STARTED;
1181 sdhci_transfer_pio(slot);
1183 /* Handle DMA border. */
1184 if (intmask & SDHCI_INT_DMA_END) {
1185 struct mmc_data *data = slot->curcmd->data;
1188 /* Unload DMA buffer... */
1189 left = data->len - slot->offset;
1190 if (data->flags & MMC_DATA_READ) {
1191 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1192 BUS_DMASYNC_POSTREAD);
1193 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1194 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1196 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1197 BUS_DMASYNC_POSTWRITE);
1199 /* ... and reload it again. */
1200 slot->offset += DMA_BLOCK_SIZE;
1201 left = data->len - slot->offset;
1202 if (data->flags & MMC_DATA_READ) {
1203 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1204 BUS_DMASYNC_PREREAD);
1206 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1207 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1208 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1209 BUS_DMASYNC_PREWRITE);
1211 /* Interrupt aggregation: Mask border interrupt
1212 * for the last page. */
1213 if (left == DMA_BLOCK_SIZE) {
1214 slot->intmask &= ~SDHCI_INT_DMA_END;
1215 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1218 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1220 /* We have got all data. */
1221 if (intmask & SDHCI_INT_DATA_END) {
1222 if (slot->flags & PLATFORM_DATA_STARTED) {
1223 slot->flags &= ~PLATFORM_DATA_STARTED;
1224 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1226 sdhci_finish_data(slot);
1231 sdhci_acmd_irq(struct sdhci_slot *slot)
1235 err = RD4(slot, SDHCI_ACMD12_ERR);
1236 if (!slot->curcmd) {
1237 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1238 "there is no active command.\n", err);
1239 sdhci_dumpregs(slot);
1242 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1243 sdhci_reset(slot, SDHCI_RESET_CMD);
1247 sdhci_generic_intr(struct sdhci_slot *slot)
1252 /* Read slot interrupt status. */
1253 intmask = RD4(slot, SDHCI_INT_STATUS);
1254 if (intmask == 0 || intmask == 0xffffffff) {
1258 if (sdhci_debug > 2)
1259 slot_printf(slot, "Interrupt %#x\n", intmask);
1261 /* Handle card presence interrupts. */
1262 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1263 WR4(slot, SDHCI_INT_STATUS, intmask &
1264 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1266 if (intmask & SDHCI_INT_CARD_REMOVE) {
1267 if (bootverbose || sdhci_debug)
1268 slot_printf(slot, "Card removed\n");
1269 callout_stop(&slot->card_callout);
1270 taskqueue_enqueue(taskqueue_swi_giant,
1273 if (intmask & SDHCI_INT_CARD_INSERT) {
1274 if (bootverbose || sdhci_debug)
1275 slot_printf(slot, "Card inserted\n");
1276 callout_reset(&slot->card_callout, hz / 2,
1277 sdhci_card_delay, slot);
1279 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1281 /* Handle command interrupts. */
1282 if (intmask & SDHCI_INT_CMD_MASK) {
1283 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1284 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1286 /* Handle data interrupts. */
1287 if (intmask & SDHCI_INT_DATA_MASK) {
1288 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1289 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1291 /* Handle AutoCMD12 error interrupt. */
1292 if (intmask & SDHCI_INT_ACMD12ERR) {
1293 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1294 sdhci_acmd_irq(slot);
1296 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1297 intmask &= ~SDHCI_INT_ACMD12ERR;
1298 intmask &= ~SDHCI_INT_ERROR;
1299 /* Handle bus power interrupt. */
1300 if (intmask & SDHCI_INT_BUS_POWER) {
1301 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1303 "Card is consuming too much power!\n");
1304 intmask &= ~SDHCI_INT_BUS_POWER;
1306 /* The rest is unknown. */
1308 WR4(slot, SDHCI_INT_STATUS, intmask);
1309 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1311 sdhci_dumpregs(slot);
1318 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1320 struct sdhci_slot *slot = device_get_ivars(child);
1325 case MMCBR_IVAR_BUS_MODE:
1326 *result = slot->host.ios.bus_mode;
1328 case MMCBR_IVAR_BUS_WIDTH:
1329 *result = slot->host.ios.bus_width;
1331 case MMCBR_IVAR_CHIP_SELECT:
1332 *result = slot->host.ios.chip_select;
1334 case MMCBR_IVAR_CLOCK:
1335 *result = slot->host.ios.clock;
1337 case MMCBR_IVAR_F_MIN:
1338 *result = slot->host.f_min;
1340 case MMCBR_IVAR_F_MAX:
1341 *result = slot->host.f_max;
1343 case MMCBR_IVAR_HOST_OCR:
1344 *result = slot->host.host_ocr;
1346 case MMCBR_IVAR_MODE:
1347 *result = slot->host.mode;
1349 case MMCBR_IVAR_OCR:
1350 *result = slot->host.ocr;
1352 case MMCBR_IVAR_POWER_MODE:
1353 *result = slot->host.ios.power_mode;
1355 case MMCBR_IVAR_VDD:
1356 *result = slot->host.ios.vdd;
1358 case MMCBR_IVAR_CAPS:
1359 *result = slot->host.caps;
1361 case MMCBR_IVAR_TIMING:
1362 *result = slot->host.ios.timing;
1364 case MMCBR_IVAR_MAX_DATA:
1372 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1374 struct sdhci_slot *slot = device_get_ivars(child);
1379 case MMCBR_IVAR_BUS_MODE:
1380 slot->host.ios.bus_mode = value;
1382 case MMCBR_IVAR_BUS_WIDTH:
1383 slot->host.ios.bus_width = value;
1385 case MMCBR_IVAR_CHIP_SELECT:
1386 slot->host.ios.chip_select = value;
1388 case MMCBR_IVAR_CLOCK:
1394 max_clock = slot->max_clk;
1397 if (slot->version < SDHCI_SPEC_300) {
1398 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
1406 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
1410 clock = max_clock / (i + 2);
1414 slot->host.ios.clock = clock;
1416 slot->host.ios.clock = 0;
1418 case MMCBR_IVAR_MODE:
1419 slot->host.mode = value;
1421 case MMCBR_IVAR_OCR:
1422 slot->host.ocr = value;
1424 case MMCBR_IVAR_POWER_MODE:
1425 slot->host.ios.power_mode = value;
1427 case MMCBR_IVAR_VDD:
1428 slot->host.ios.vdd = value;
1430 case MMCBR_IVAR_TIMING:
1431 slot->host.ios.timing = value;
1433 case MMCBR_IVAR_CAPS:
1434 case MMCBR_IVAR_HOST_OCR:
1435 case MMCBR_IVAR_F_MIN:
1436 case MMCBR_IVAR_F_MAX:
1437 case MMCBR_IVAR_MAX_DATA:
1443 MODULE_VERSION(sdhci, 1);