2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
32 #include <sys/callout.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/stdarg.h>
47 #include <dev/mmc/bridge.h>
48 #include <dev/mmc/mmcreg.h>
49 #include <dev/mmc/mmcbrvar.h>
55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
57 static int sdhci_debug;
58 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
59 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level");
61 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
62 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
63 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
64 #define RD_MULTI_4(slot, off, ptr, count) \
65 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
67 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
68 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
69 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
70 #define WR_MULTI_4(slot, off, ptr, count) \
71 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
73 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
74 static void sdhci_start(struct sdhci_slot *slot);
75 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
77 static void sdhci_card_task(void *, int);
80 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
81 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
82 #define SDHCI_LOCK_INIT(_slot) \
83 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
84 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
85 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
86 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
88 #define SDHCI_DEFAULT_MAX_FREQ 50
90 #define SDHCI_200_MAX_DIVIDER 256
91 #define SDHCI_300_MAX_DIVIDER 2046
94 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
97 printf("getaddr: error %d\n", error);
100 *(bus_addr_t *)arg = segs[0].ds_addr;
104 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
109 retval = printf("%s-slot%d: ",
110 device_get_nameunit(slot->bus), slot->num);
113 retval += vprintf(fmt, ap);
119 sdhci_dumpregs(struct sdhci_slot *slot)
122 "============== REGISTER DUMP ==============\n");
124 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
125 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
126 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
127 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
128 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
129 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
130 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
131 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
132 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
133 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
134 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
135 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
136 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
137 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
138 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
139 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
140 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
141 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
142 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n",
143 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
146 "===========================================\n");
150 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
154 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
155 if (!(RD4(slot, SDHCI_PRESENT_STATE) &
160 /* Some controllers need this kick or reset won't work. */
161 if ((mask & SDHCI_RESET_ALL) == 0 &&
162 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
165 /* This is to force an update */
168 sdhci_set_clock(slot, clock);
171 if (mask & SDHCI_RESET_ALL) {
176 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
178 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
180 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
181 * specification. The reset bit has internal propagation delay,
182 * so a fast read after write returns 0 even if reset process is
183 * in progress. The workaround is to poll for 1 before polling
184 * for 0. In the worst case, if we miss seeing it asserted the
185 * time we spent waiting is enough to ensure the reset finishes.
188 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
196 /* Wait max 100 ms */
198 /* Controller clears the bits when it's done */
199 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
201 slot_printf(slot, "Reset 0x%x never completed.\n",
203 sdhci_dumpregs(slot);
212 sdhci_init(struct sdhci_slot *slot)
215 sdhci_reset(slot, SDHCI_RESET_ALL);
217 /* Enable interrupts. */
218 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
219 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
220 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
221 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
222 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
223 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
225 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
226 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
230 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
237 if (clock == slot->clock)
241 /* Turn off the clock. */
242 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
243 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
244 /* If no clock requested - left it so. */
248 /* Recalculate timeout clock frequency based on the new sd clock. */
249 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
250 slot->timeout_clk = slot->clock / 1000;
252 if (slot->version < SDHCI_SPEC_300) {
253 /* Looking for highest freq <= clock. */
255 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
260 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
264 /* Version 3.0 divisors are multiples of two up to 1023*2 */
265 if (clock >= slot->max_clk)
268 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
269 if ((slot->max_clk / div) <= clock)
276 if (bootverbose || sdhci_debug)
277 slot_printf(slot, "Divider %d for freq %d (max %d)\n",
278 div, clock, slot->max_clk);
280 /* Now we have got divider, set it. */
281 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
282 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
283 << SDHCI_DIVIDER_HI_SHIFT;
285 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
287 clk |= SDHCI_CLOCK_INT_EN;
288 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
289 /* Wait up to 10 ms until it stabilize. */
291 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
292 & SDHCI_CLOCK_INT_STABLE)) {
295 "Internal clock never stabilised.\n");
296 sdhci_dumpregs(slot);
302 /* Pass clock signal to the bus. */
303 clk |= SDHCI_CLOCK_CARD_EN;
304 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
308 sdhci_set_power(struct sdhci_slot *slot, u_char power)
312 if (slot->power == power)
317 /* Turn off the power. */
319 WR1(slot, SDHCI_POWER_CONTROL, pwr);
320 /* If power down requested - left it so. */
324 switch (1 << power) {
325 case MMC_OCR_LOW_VOLTAGE:
326 pwr |= SDHCI_POWER_180;
328 case MMC_OCR_290_300:
329 case MMC_OCR_300_310:
330 pwr |= SDHCI_POWER_300;
332 case MMC_OCR_320_330:
333 case MMC_OCR_330_340:
334 pwr |= SDHCI_POWER_330;
337 WR1(slot, SDHCI_POWER_CONTROL, pwr);
338 /* Turn on the power. */
339 pwr |= SDHCI_POWER_ON;
340 WR1(slot, SDHCI_POWER_CONTROL, pwr);
344 sdhci_read_block_pio(struct sdhci_slot *slot)
350 buffer = slot->curcmd->data->data;
351 buffer += slot->offset;
352 /* Transfer one block at a time. */
353 left = min(512, slot->curcmd->data->len - slot->offset);
354 slot->offset += left;
356 /* If we are too fast, broken controllers return zeroes. */
357 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
359 /* Handle unaligned and aligned buffer cases. */
360 if ((intptr_t)buffer & 3) {
362 data = RD4(slot, SDHCI_BUFFER);
364 buffer[1] = (data >> 8);
365 buffer[2] = (data >> 16);
366 buffer[3] = (data >> 24);
371 RD_MULTI_4(slot, SDHCI_BUFFER,
372 (uint32_t *)buffer, left >> 2);
375 /* Handle uneven size case. */
377 data = RD4(slot, SDHCI_BUFFER);
387 sdhci_write_block_pio(struct sdhci_slot *slot)
393 buffer = slot->curcmd->data->data;
394 buffer += slot->offset;
395 /* Transfer one block at a time. */
396 left = min(512, slot->curcmd->data->len - slot->offset);
397 slot->offset += left;
399 /* Handle unaligned and aligned buffer cases. */
400 if ((intptr_t)buffer & 3) {
408 WR4(slot, SDHCI_BUFFER, data);
411 WR_MULTI_4(slot, SDHCI_BUFFER,
412 (uint32_t *)buffer, left >> 2);
415 /* Handle uneven size case. */
422 WR4(slot, SDHCI_BUFFER, data);
427 sdhci_transfer_pio(struct sdhci_slot *slot)
430 /* Read as many blocks as possible. */
431 if (slot->curcmd->data->flags & MMC_DATA_READ) {
432 while (RD4(slot, SDHCI_PRESENT_STATE) &
433 SDHCI_DATA_AVAILABLE) {
434 sdhci_read_block_pio(slot);
435 if (slot->offset >= slot->curcmd->data->len)
439 while (RD4(slot, SDHCI_PRESENT_STATE) &
440 SDHCI_SPACE_AVAILABLE) {
441 sdhci_write_block_pio(slot);
442 if (slot->offset >= slot->curcmd->data->len)
449 sdhci_card_delay(void *arg)
451 struct sdhci_slot *slot = arg;
453 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
457 sdhci_card_task(void *arg, int pending)
459 struct sdhci_slot *slot = arg;
462 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
463 if (slot->dev == NULL) {
464 /* If card is present - attach mmc bus. */
465 slot->dev = device_add_child(slot->bus, "mmc", -1);
466 device_set_ivars(slot->dev, slot);
468 device_probe_and_attach(slot->dev);
472 if (slot->dev != NULL) {
473 /* If no card present - detach mmc bus. */
474 device_t d = slot->dev;
477 device_delete_child(slot->bus, d);
484 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
489 SDHCI_LOCK_INIT(slot);
493 /* Allocate DMA tag. */
494 err = bus_dma_tag_create(bus_get_dma_tag(dev),
495 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
496 BUS_SPACE_MAXADDR, NULL, NULL,
497 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
498 BUS_DMA_ALLOCNOW, NULL, NULL,
501 device_printf(dev, "Can't create DMA tag\n");
502 SDHCI_LOCK_DESTROY(slot);
505 /* Allocate DMA memory. */
506 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
507 BUS_DMA_NOWAIT, &slot->dmamap);
509 device_printf(dev, "Can't alloc DMA memory\n");
510 SDHCI_LOCK_DESTROY(slot);
513 /* Map the memory. */
514 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
515 (void *)slot->dmamem, DMA_BLOCK_SIZE,
516 sdhci_getaddr, &slot->paddr, 0);
517 if (err != 0 || slot->paddr == 0) {
518 device_printf(dev, "Can't load DMA memory\n");
519 SDHCI_LOCK_DESTROY(slot);
526 /* Initialize slot. */
528 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
529 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
530 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
533 caps = RD4(slot, SDHCI_CAPABILITIES);
534 /* Calculate base clock frequency. */
535 if (slot->version >= SDHCI_SPEC_300)
536 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
537 SDHCI_CLOCK_BASE_SHIFT;
539 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
540 SDHCI_CLOCK_BASE_SHIFT;
542 slot->max_clk = freq * 1000000;
544 * If the frequency wasn't in the capabilities and the hardware driver
545 * hasn't already set max_clk we're probably not going to work right
546 * with an assumption, so complain about it.
548 if (slot->max_clk == 0) {
549 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
550 device_printf(dev, "Hardware doesn't specify base clock "
551 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
553 /* Calculate timeout clock frequency. */
554 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
555 slot->timeout_clk = slot->max_clk / 1000;
558 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
559 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
560 slot->timeout_clk *= 1000;
563 * If the frequency wasn't in the capabilities and the hardware driver
564 * hasn't already set timeout_clk we'll probably work okay using the
565 * max timeout, but still mention it.
567 if (slot->timeout_clk == 0) {
568 device_printf(dev, "Hardware doesn't specify timeout clock "
569 "frequency, setting BROKEN_TIMEOUT quirk.\n");
570 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
573 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
574 slot->host.f_max = slot->max_clk;
575 slot->host.host_ocr = 0;
576 if (caps & SDHCI_CAN_VDD_330)
577 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
578 if (caps & SDHCI_CAN_VDD_300)
579 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
580 if (caps & SDHCI_CAN_VDD_180)
581 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
582 if (slot->host.host_ocr == 0) {
583 device_printf(dev, "Hardware doesn't report any "
584 "support voltages.\n");
586 slot->host.caps = MMC_CAP_4_BIT_DATA;
587 if (caps & SDHCI_CAN_DO_HISPD)
588 slot->host.caps |= MMC_CAP_HSPEED;
589 /* Decide if we have usable DMA. */
590 if (caps & SDHCI_CAN_DO_DMA)
591 slot->opt |= SDHCI_HAVE_DMA;
593 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
594 slot->opt &= ~SDHCI_HAVE_DMA;
595 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
596 slot->opt |= SDHCI_HAVE_DMA;
599 * Use platform-provided transfer backend
600 * with PIO as a fallback mechanism
602 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
603 slot->opt &= ~SDHCI_HAVE_DMA;
605 if (bootverbose || sdhci_debug) {
606 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
607 slot->max_clk / 1000000,
608 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
609 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
610 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
611 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
612 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
613 sdhci_dumpregs(slot);
616 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
617 callout_init(&slot->card_callout, 1);
618 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
623 sdhci_start_slot(struct sdhci_slot *slot)
625 sdhci_card_task(slot, 0);
629 sdhci_cleanup_slot(struct sdhci_slot *slot)
633 callout_drain(&slot->timeout_callout);
634 callout_drain(&slot->card_callout);
635 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
642 device_delete_child(slot->bus, d);
645 sdhci_reset(slot, SDHCI_RESET_ALL);
647 bus_dmamap_unload(slot->dmatag, slot->dmamap);
648 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
649 bus_dma_tag_destroy(slot->dmatag);
651 SDHCI_LOCK_DESTROY(slot);
657 sdhci_generic_suspend(struct sdhci_slot *slot)
659 sdhci_reset(slot, SDHCI_RESET_ALL);
665 sdhci_generic_resume(struct sdhci_slot *slot)
673 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot)
675 if (slot->version >= SDHCI_SPEC_300)
676 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
678 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
682 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
684 struct sdhci_slot *slot = device_get_ivars(reqdev);
685 struct mmc_ios *ios = &slot->host.ios;
688 /* Do full reset on bus power down to clear from any state. */
689 if (ios->power_mode == power_off) {
690 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
693 /* Configure the bus. */
694 sdhci_set_clock(slot, ios->clock);
695 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd);
696 if (ios->bus_width == bus_width_4)
697 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
699 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
700 if (ios->timing == bus_timing_hs)
701 slot->hostctrl |= SDHCI_CTRL_HISPD;
703 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
704 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
705 /* Some controllers like reset after bus changes. */
706 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
707 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
714 sdhci_req_done(struct sdhci_slot *slot)
716 struct mmc_request *req;
718 if (slot->req != NULL && slot->curcmd != NULL) {
719 callout_stop(&slot->timeout_callout);
728 sdhci_timeout(void *arg)
730 struct sdhci_slot *slot = arg;
732 if (slot->curcmd != NULL) {
733 slot_printf(slot, " Controller timeout\n");
734 sdhci_dumpregs(slot);
735 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
736 slot->curcmd->error = MMC_ERR_TIMEOUT;
737 sdhci_req_done(slot);
739 slot_printf(slot, " Spurious timeout - no active command\n");
744 sdhci_set_transfer_mode(struct sdhci_slot *slot,
745 struct mmc_data *data)
752 mode = SDHCI_TRNS_BLK_CNT_EN;
754 mode |= SDHCI_TRNS_MULTI;
755 if (data->flags & MMC_DATA_READ)
756 mode |= SDHCI_TRNS_READ;
758 mode |= SDHCI_TRNS_ACMD12;
759 if (slot->flags & SDHCI_USE_DMA)
760 mode |= SDHCI_TRNS_DMA;
762 WR2(slot, SDHCI_TRANSFER_MODE, mode);
766 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
769 uint32_t mask, state;
774 cmd->error = MMC_ERR_NONE;
776 /* This flags combination is not supported by controller. */
777 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
778 slot_printf(slot, "Unsupported response type!\n");
779 cmd->error = MMC_ERR_FAILED;
780 sdhci_req_done(slot);
784 /* Read controller present state. */
785 state = RD4(slot, SDHCI_PRESENT_STATE);
786 /* Do not issue command if there is no card, clock or power.
787 * Controller will not detect timeout without clock active. */
788 if ((state & SDHCI_CARD_PRESENT) == 0 ||
791 cmd->error = MMC_ERR_FAILED;
792 sdhci_req_done(slot);
795 /* Always wait for free CMD bus. */
796 mask = SDHCI_CMD_INHIBIT;
797 /* Wait for free DAT if we have data or busy signal. */
798 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
799 mask |= SDHCI_DAT_INHIBIT;
800 /* We shouldn't wait for DAT for stop commands. */
801 if (cmd == slot->req->stop)
802 mask &= ~SDHCI_DAT_INHIBIT;
804 * Wait for bus no more then 250 ms. Typically there will be no wait
805 * here at all, but when writing a crash dump we may be bypassing the
806 * host platform's interrupt handler, and in some cases that handler
807 * may be working around hardware quirks such as not respecting r1b
808 * busy indications. In those cases, this wait-loop serves the purpose
809 * of waiting for the prior command and data transfers to be done, and
810 * SD cards are allowed to take up to 250ms for write and erase ops.
811 * (It's usually more like 20-30ms in the real world.)
814 while (state & mask) {
816 slot_printf(slot, "Controller never released "
817 "inhibit bit(s).\n");
818 sdhci_dumpregs(slot);
819 cmd->error = MMC_ERR_FAILED;
820 sdhci_req_done(slot);
825 state = RD4(slot, SDHCI_PRESENT_STATE);
828 /* Prepare command flags. */
829 if (!(cmd->flags & MMC_RSP_PRESENT))
830 flags = SDHCI_CMD_RESP_NONE;
831 else if (cmd->flags & MMC_RSP_136)
832 flags = SDHCI_CMD_RESP_LONG;
833 else if (cmd->flags & MMC_RSP_BUSY)
834 flags = SDHCI_CMD_RESP_SHORT_BUSY;
836 flags = SDHCI_CMD_RESP_SHORT;
837 if (cmd->flags & MMC_RSP_CRC)
838 flags |= SDHCI_CMD_CRC;
839 if (cmd->flags & MMC_RSP_OPCODE)
840 flags |= SDHCI_CMD_INDEX;
842 flags |= SDHCI_CMD_DATA;
843 if (cmd->opcode == MMC_STOP_TRANSMISSION)
844 flags |= SDHCI_CMD_TYPE_ABORT;
846 sdhci_start_data(slot, cmd->data);
848 * Interrupt aggregation: To reduce total number of interrupts
849 * group response interrupt with data interrupt when possible.
850 * If there going to be data interrupt, mask response one.
852 if (slot->data_done == 0) {
853 WR4(slot, SDHCI_SIGNAL_ENABLE,
854 slot->intmask &= ~SDHCI_INT_RESPONSE);
856 /* Set command argument. */
857 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
858 /* Set data transfer mode. */
859 sdhci_set_transfer_mode(slot, cmd->data);
861 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
862 /* Start timeout callout. */
863 callout_reset(&slot->timeout_callout, 2*hz, sdhci_timeout, slot);
867 sdhci_finish_command(struct sdhci_slot *slot)
872 /* Interrupt aggregation: Restore command interrupt.
873 * Main restore point for the case when command interrupt
875 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
876 /* In case of error - reset host and return. */
877 if (slot->curcmd->error) {
878 sdhci_reset(slot, SDHCI_RESET_CMD);
879 sdhci_reset(slot, SDHCI_RESET_DATA);
883 /* If command has response - fetch it. */
884 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
885 if (slot->curcmd->flags & MMC_RSP_136) {
886 /* CRC is stripped so we need one byte shift. */
888 for (i = 0; i < 4; i++) {
889 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
890 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
891 slot->curcmd->resp[3 - i] = val;
893 slot->curcmd->resp[3 - i] =
899 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
901 /* If data ready - finish. */
907 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
909 uint32_t target_timeout, current_timeout;
912 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
919 /* Calculate and set data timeout.*/
920 /* XXX: We should have this from mmc layer, now assume 1 sec. */
921 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
924 target_timeout = 1000000;
926 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
927 while (current_timeout < target_timeout && div < 0xE) {
929 current_timeout <<= 1;
931 /* Compensate for an off-by-one error in the CaFe chip.*/
933 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
937 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
942 /* Use DMA if possible. */
943 if ((slot->opt & SDHCI_HAVE_DMA))
944 slot->flags |= SDHCI_USE_DMA;
945 /* If data is small, broken DMA may return zeroes instead of data, */
946 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
948 slot->flags &= ~SDHCI_USE_DMA;
949 /* Some controllers require even block sizes. */
950 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
952 slot->flags &= ~SDHCI_USE_DMA;
953 /* Load DMA buffer. */
954 if (slot->flags & SDHCI_USE_DMA) {
955 if (data->flags & MMC_DATA_READ)
956 bus_dmamap_sync(slot->dmatag, slot->dmamap,
957 BUS_DMASYNC_PREREAD);
959 memcpy(slot->dmamem, data->data,
960 (data->len < DMA_BLOCK_SIZE) ?
961 data->len : DMA_BLOCK_SIZE);
962 bus_dmamap_sync(slot->dmatag, slot->dmamap,
963 BUS_DMASYNC_PREWRITE);
965 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
966 /* Interrupt aggregation: Mask border interrupt
967 * for the last page and unmask else. */
968 if (data->len == DMA_BLOCK_SIZE)
969 slot->intmask &= ~SDHCI_INT_DMA_END;
971 slot->intmask |= SDHCI_INT_DMA_END;
972 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
974 /* Current data offset for both PIO and DMA. */
976 /* Set block size and request IRQ on 4K border. */
977 WR2(slot, SDHCI_BLOCK_SIZE,
978 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
979 /* Set block count. */
980 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
984 sdhci_finish_data(struct sdhci_slot *slot)
986 struct mmc_data *data = slot->curcmd->data;
988 /* Interrupt aggregation: Restore command interrupt.
989 * Auxiliary restore point for the case when data interrupt
991 if (!slot->cmd_done) {
992 WR4(slot, SDHCI_SIGNAL_ENABLE,
993 slot->intmask |= SDHCI_INT_RESPONSE);
995 /* Unload rest of data from DMA buffer. */
996 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) {
997 if (data->flags & MMC_DATA_READ) {
998 size_t left = data->len - slot->offset;
999 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1000 BUS_DMASYNC_POSTREAD);
1001 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1002 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1004 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1005 BUS_DMASYNC_POSTWRITE);
1007 slot->data_done = 1;
1008 /* If there was error - reset the host. */
1009 if (slot->curcmd->error) {
1010 sdhci_reset(slot, SDHCI_RESET_CMD);
1011 sdhci_reset(slot, SDHCI_RESET_DATA);
1015 /* If we already have command response - finish. */
1021 sdhci_start(struct sdhci_slot *slot)
1023 struct mmc_request *req;
1029 if (!(slot->flags & CMD_STARTED)) {
1030 slot->flags |= CMD_STARTED;
1031 sdhci_start_command(slot, req->cmd);
1034 /* We don't need this until using Auto-CMD12 feature
1035 if (!(slot->flags & STOP_STARTED) && req->stop) {
1036 slot->flags |= STOP_STARTED;
1037 sdhci_start_command(slot, req->stop);
1041 if (sdhci_debug > 1)
1042 slot_printf(slot, "result: %d\n", req->cmd->error);
1043 if (!req->cmd->error &&
1044 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1045 sdhci_reset(slot, SDHCI_RESET_CMD);
1046 sdhci_reset(slot, SDHCI_RESET_DATA);
1049 sdhci_req_done(slot);
1053 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1055 struct sdhci_slot *slot = device_get_ivars(reqdev);
1058 if (slot->req != NULL) {
1062 if (sdhci_debug > 1) {
1063 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1064 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1065 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1066 (req->cmd->data)?req->cmd->data->flags:0);
1073 while (slot->req != NULL) {
1074 sdhci_generic_intr(slot);
1082 sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1084 struct sdhci_slot *slot = device_get_ivars(reqdev);
1088 val = RD4(slot, SDHCI_PRESENT_STATE);
1090 return (!(val & SDHCI_WRITE_PROTECT));
1094 sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1096 struct sdhci_slot *slot = device_get_ivars(reqdev);
1100 while (slot->bus_busy)
1101 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1104 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1110 sdhci_generic_release_host(device_t brdev, device_t reqdev)
1112 struct sdhci_slot *slot = device_get_ivars(reqdev);
1115 /* Deactivate led. */
1116 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1124 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1127 if (!slot->curcmd) {
1128 slot_printf(slot, "Got command interrupt 0x%08x, but "
1129 "there is no active command.\n", intmask);
1130 sdhci_dumpregs(slot);
1133 if (intmask & SDHCI_INT_TIMEOUT)
1134 slot->curcmd->error = MMC_ERR_TIMEOUT;
1135 else if (intmask & SDHCI_INT_CRC)
1136 slot->curcmd->error = MMC_ERR_BADCRC;
1137 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1138 slot->curcmd->error = MMC_ERR_FIFO;
1140 sdhci_finish_command(slot);
1144 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1147 if (!slot->curcmd) {
1148 slot_printf(slot, "Got data interrupt 0x%08x, but "
1149 "there is no active command.\n", intmask);
1150 sdhci_dumpregs(slot);
1153 if (slot->curcmd->data == NULL &&
1154 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1155 slot_printf(slot, "Got data interrupt 0x%08x, but "
1156 "there is no active data operation.\n",
1158 sdhci_dumpregs(slot);
1161 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1162 slot->curcmd->error = MMC_ERR_TIMEOUT;
1163 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1164 slot->curcmd->error = MMC_ERR_BADCRC;
1165 if (slot->curcmd->data == NULL &&
1166 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1167 SDHCI_INT_DMA_END))) {
1168 slot_printf(slot, "Got data interrupt 0x%08x, but "
1169 "there is busy-only command.\n", intmask);
1170 sdhci_dumpregs(slot);
1171 slot->curcmd->error = MMC_ERR_INVALID;
1173 if (slot->curcmd->error) {
1174 /* No need to continue after any error. */
1178 /* Handle PIO interrupt. */
1179 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1180 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1181 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1182 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask);
1183 slot->flags |= PLATFORM_DATA_STARTED;
1185 sdhci_transfer_pio(slot);
1187 /* Handle DMA border. */
1188 if (intmask & SDHCI_INT_DMA_END) {
1189 struct mmc_data *data = slot->curcmd->data;
1192 /* Unload DMA buffer... */
1193 left = data->len - slot->offset;
1194 if (data->flags & MMC_DATA_READ) {
1195 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1196 BUS_DMASYNC_POSTREAD);
1197 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1198 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1200 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1201 BUS_DMASYNC_POSTWRITE);
1203 /* ... and reload it again. */
1204 slot->offset += DMA_BLOCK_SIZE;
1205 left = data->len - slot->offset;
1206 if (data->flags & MMC_DATA_READ) {
1207 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1208 BUS_DMASYNC_PREREAD);
1210 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1211 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1212 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1213 BUS_DMASYNC_PREWRITE);
1215 /* Interrupt aggregation: Mask border interrupt
1216 * for the last page. */
1217 if (left == DMA_BLOCK_SIZE) {
1218 slot->intmask &= ~SDHCI_INT_DMA_END;
1219 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1222 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1224 /* We have got all data. */
1225 if (intmask & SDHCI_INT_DATA_END) {
1226 if (slot->flags & PLATFORM_DATA_STARTED) {
1227 slot->flags &= ~PLATFORM_DATA_STARTED;
1228 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1230 sdhci_finish_data(slot);
1233 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
1234 if (slot->flags & PLATFORM_DATA_STARTED) {
1235 slot->flags &= ~PLATFORM_DATA_STARTED;
1236 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1238 sdhci_finish_data(slot);
1244 sdhci_acmd_irq(struct sdhci_slot *slot)
1248 err = RD4(slot, SDHCI_ACMD12_ERR);
1249 if (!slot->curcmd) {
1250 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1251 "there is no active command.\n", err);
1252 sdhci_dumpregs(slot);
1255 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1256 sdhci_reset(slot, SDHCI_RESET_CMD);
1260 sdhci_generic_intr(struct sdhci_slot *slot)
1265 /* Read slot interrupt status. */
1266 intmask = RD4(slot, SDHCI_INT_STATUS);
1267 if (intmask == 0 || intmask == 0xffffffff) {
1271 if (sdhci_debug > 2)
1272 slot_printf(slot, "Interrupt %#x\n", intmask);
1274 /* Handle card presence interrupts. */
1275 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1276 WR4(slot, SDHCI_INT_STATUS, intmask &
1277 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1279 if (intmask & SDHCI_INT_CARD_REMOVE) {
1280 if (bootverbose || sdhci_debug)
1281 slot_printf(slot, "Card removed\n");
1282 callout_stop(&slot->card_callout);
1283 taskqueue_enqueue(taskqueue_swi_giant,
1286 if (intmask & SDHCI_INT_CARD_INSERT) {
1287 if (bootverbose || sdhci_debug)
1288 slot_printf(slot, "Card inserted\n");
1289 callout_reset(&slot->card_callout, hz / 2,
1290 sdhci_card_delay, slot);
1292 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1294 /* Handle command interrupts. */
1295 if (intmask & SDHCI_INT_CMD_MASK) {
1296 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1297 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1299 /* Handle data interrupts. */
1300 if (intmask & SDHCI_INT_DATA_MASK) {
1301 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1302 /* Dont call data_irq in case of errored command */
1303 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
1304 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1306 /* Handle AutoCMD12 error interrupt. */
1307 if (intmask & SDHCI_INT_ACMD12ERR) {
1308 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1309 sdhci_acmd_irq(slot);
1311 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1312 intmask &= ~SDHCI_INT_ACMD12ERR;
1313 intmask &= ~SDHCI_INT_ERROR;
1314 /* Handle bus power interrupt. */
1315 if (intmask & SDHCI_INT_BUS_POWER) {
1316 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1318 "Card is consuming too much power!\n");
1319 intmask &= ~SDHCI_INT_BUS_POWER;
1321 /* The rest is unknown. */
1323 WR4(slot, SDHCI_INT_STATUS, intmask);
1324 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1326 sdhci_dumpregs(slot);
1333 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1335 struct sdhci_slot *slot = device_get_ivars(child);
1340 case MMCBR_IVAR_BUS_MODE:
1341 *result = slot->host.ios.bus_mode;
1343 case MMCBR_IVAR_BUS_WIDTH:
1344 *result = slot->host.ios.bus_width;
1346 case MMCBR_IVAR_CHIP_SELECT:
1347 *result = slot->host.ios.chip_select;
1349 case MMCBR_IVAR_CLOCK:
1350 *result = slot->host.ios.clock;
1352 case MMCBR_IVAR_F_MIN:
1353 *result = slot->host.f_min;
1355 case MMCBR_IVAR_F_MAX:
1356 *result = slot->host.f_max;
1358 case MMCBR_IVAR_HOST_OCR:
1359 *result = slot->host.host_ocr;
1361 case MMCBR_IVAR_MODE:
1362 *result = slot->host.mode;
1364 case MMCBR_IVAR_OCR:
1365 *result = slot->host.ocr;
1367 case MMCBR_IVAR_POWER_MODE:
1368 *result = slot->host.ios.power_mode;
1370 case MMCBR_IVAR_VDD:
1371 *result = slot->host.ios.vdd;
1373 case MMCBR_IVAR_CAPS:
1374 *result = slot->host.caps;
1376 case MMCBR_IVAR_TIMING:
1377 *result = slot->host.ios.timing;
1379 case MMCBR_IVAR_MAX_DATA:
1387 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1389 struct sdhci_slot *slot = device_get_ivars(child);
1394 case MMCBR_IVAR_BUS_MODE:
1395 slot->host.ios.bus_mode = value;
1397 case MMCBR_IVAR_BUS_WIDTH:
1398 slot->host.ios.bus_width = value;
1400 case MMCBR_IVAR_CHIP_SELECT:
1401 slot->host.ios.chip_select = value;
1403 case MMCBR_IVAR_CLOCK:
1409 max_clock = slot->max_clk;
1412 if (slot->version < SDHCI_SPEC_300) {
1413 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
1421 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
1425 clock = max_clock / (i + 2);
1429 slot->host.ios.clock = clock;
1431 slot->host.ios.clock = 0;
1433 case MMCBR_IVAR_MODE:
1434 slot->host.mode = value;
1436 case MMCBR_IVAR_OCR:
1437 slot->host.ocr = value;
1439 case MMCBR_IVAR_POWER_MODE:
1440 slot->host.ios.power_mode = value;
1442 case MMCBR_IVAR_VDD:
1443 slot->host.ios.vdd = value;
1445 case MMCBR_IVAR_TIMING:
1446 slot->host.ios.timing = value;
1448 case MMCBR_IVAR_CAPS:
1449 case MMCBR_IVAR_HOST_OCR:
1450 case MMCBR_IVAR_F_MIN:
1451 case MMCBR_IVAR_F_MAX:
1452 case MMCBR_IVAR_MAX_DATA:
1458 MODULE_VERSION(sdhci, 1);