2 * Copyright 2013-2015 John Wehle <john@feith.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Amlogic aml8726 watchdog driver.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/eventhandler.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/malloc.h>
44 #include <sys/watchdog.h>
46 #include <machine/bus.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
51 #include <arm/amlogic/aml8726/aml8726_soc.h>
54 struct aml8726_wdt_softc {
56 struct resource * res[2];
61 static struct resource_spec aml8726_wdt_spec[] = {
62 { SYS_RES_MEMORY, 0, RF_ACTIVE },
63 { SYS_RES_IRQ, 0, RF_ACTIVE },
68 uint32_t ctrl_cpu_mask;
70 uint32_t term_cnt_mask;
71 uint32_t reset_cnt_mask;
72 } aml8726_wdt_soc_params;
75 * devclass_get_device / device_get_softc could be used
76 * to dynamically locate this, however the wdt is a
77 * required device which can't be unloaded so there's
78 * no need for the overhead.
80 static struct aml8726_wdt_softc *aml8726_wdt_sc = NULL;
82 #define AML_WDT_LOCK(sc) mtx_lock_spin(&(sc)->mtx)
83 #define AML_WDT_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx)
84 #define AML_WDT_LOCK_INIT(sc) \
85 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
87 #define AML_WDT_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
89 #define AML_WDT_CTRL_REG 0
90 #define AML_WDT_CTRL_CPU_WDRESET_MASK aml8726_wdt_soc_params.ctrl_cpu_mask
91 #define AML_WDT_CTRL_CPU_WDRESET_SHIFT 24
92 #define AML_WDT_CTRL_IRQ_EN (1 << 23)
93 #define AML_WDT_CTRL_EN aml8726_wdt_soc_params.ctrl_en
94 #define AML_WDT_CTRL_TERMINAL_CNT_MASK aml8726_wdt_soc_params.term_cnt_mask
95 #define AML_WDT_CTRL_TERMINAL_CNT_SHIFT 0
96 #define AML_WDT_RESET_REG 4
97 #define AML_WDT_RESET_CNT_MASK aml8726_wdt_soc_params.reset_cnt_mask
98 #define AML_WDT_RESET_CNT_SHIFT 0
100 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
101 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
102 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \
103 (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
106 aml8726_wdt_watchdog(void *private, u_int cmd, int *error)
108 struct aml8726_wdt_softc *sc = (struct aml8726_wdt_softc *)private;
110 uint64_t tens_of_usec;
114 tens_of_usec = (((uint64_t)1 << (cmd & WD_INTERVAL)) + 9999) / 10000;
116 if (cmd != 0 && tens_of_usec <= (AML_WDT_CTRL_TERMINAL_CNT_MASK >>
117 AML_WDT_CTRL_TERMINAL_CNT_SHIFT)) {
119 wcr = AML_WDT_CTRL_CPU_WDRESET_MASK |
120 AML_WDT_CTRL_EN | ((uint32_t)tens_of_usec <<
121 AML_WDT_CTRL_TERMINAL_CNT_SHIFT);
123 CSR_WRITE_4(sc, AML_WDT_RESET_REG, 0);
124 CSR_WRITE_4(sc, AML_WDT_CTRL_REG, wcr);
128 CSR_WRITE_4(sc, AML_WDT_CTRL_REG,
129 (CSR_READ_4(sc, AML_WDT_CTRL_REG) &
130 ~(AML_WDT_CTRL_IRQ_EN | AML_WDT_CTRL_EN)));
136 aml8726_wdt_intr(void *arg)
138 struct aml8726_wdt_softc *sc = (struct aml8726_wdt_softc *)arg;
141 * Normally a timeout causes a hardware reset, however
142 * the watchdog timer can be configured to cause an
143 * interrupt instead by setting AML_WDT_CTRL_IRQ_EN
144 * and clearing AML_WDT_CTRL_CPU_WDRESET_MASK.
149 CSR_WRITE_4(sc, AML_WDT_CTRL_REG,
150 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & ~(AML_WDT_CTRL_IRQ_EN |
153 CSR_BARRIER(sc, AML_WDT_CTRL_REG);
157 device_printf(sc->dev, "timeout expired\n");
159 return (FILTER_HANDLED);
163 aml8726_wdt_probe(device_t dev)
166 if (!ofw_bus_status_okay(dev))
169 if (!ofw_bus_is_compatible(dev, "amlogic,meson6-wdt"))
172 device_set_desc(dev, "Amlogic aml8726 WDT");
174 return (BUS_PROBE_DEFAULT);
178 aml8726_wdt_attach(device_t dev)
180 struct aml8726_wdt_softc *sc = device_get_softc(dev);
182 /* There should be exactly one instance. */
183 if (aml8726_wdt_sc != NULL)
188 if (bus_alloc_resources(dev, aml8726_wdt_spec, sc->res)) {
189 device_printf(dev, "can not allocate resources for device\n");
194 * Certain bitfields are dependent on the hardware revision.
196 switch (aml8726_soc_hw_rev) {
197 case AML_SOC_HW_REV_M8:
198 aml8726_wdt_soc_params.ctrl_cpu_mask = 0xf <<
199 AML_WDT_CTRL_CPU_WDRESET_SHIFT;
200 switch (aml8726_soc_metal_rev) {
201 case AML_SOC_M8_METAL_REV_M2_A:
202 aml8726_wdt_soc_params.ctrl_en = 1 << 19;
203 aml8726_wdt_soc_params.term_cnt_mask = 0x07ffff <<
204 AML_WDT_CTRL_TERMINAL_CNT_SHIFT;
205 aml8726_wdt_soc_params.reset_cnt_mask = 0x07ffff <<
206 AML_WDT_RESET_CNT_SHIFT;
209 aml8726_wdt_soc_params.ctrl_en = 1 << 22;
210 aml8726_wdt_soc_params.term_cnt_mask = 0x3fffff <<
211 AML_WDT_CTRL_TERMINAL_CNT_SHIFT;
212 aml8726_wdt_soc_params.reset_cnt_mask = 0x3fffff <<
213 AML_WDT_RESET_CNT_SHIFT;
217 case AML_SOC_HW_REV_M8B:
218 aml8726_wdt_soc_params.ctrl_cpu_mask = 0xf <<
219 AML_WDT_CTRL_CPU_WDRESET_SHIFT;
220 aml8726_wdt_soc_params.ctrl_en = 1 << 19;
221 aml8726_wdt_soc_params.term_cnt_mask = 0x07ffff <<
222 AML_WDT_CTRL_TERMINAL_CNT_SHIFT;
223 aml8726_wdt_soc_params.reset_cnt_mask = 0x07ffff <<
224 AML_WDT_RESET_CNT_SHIFT;
227 aml8726_wdt_soc_params.ctrl_cpu_mask = 3 <<
228 AML_WDT_CTRL_CPU_WDRESET_SHIFT;
229 aml8726_wdt_soc_params.ctrl_en = 1 << 22;
230 aml8726_wdt_soc_params.term_cnt_mask = 0x3fffff <<
231 AML_WDT_CTRL_TERMINAL_CNT_SHIFT;
232 aml8726_wdt_soc_params.reset_cnt_mask = 0x3fffff <<
233 AML_WDT_RESET_CNT_SHIFT;
238 * Disable the watchdog.
240 CSR_WRITE_4(sc, AML_WDT_CTRL_REG,
241 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & ~(AML_WDT_CTRL_IRQ_EN |
245 * Initialize the mutex prior to installing the interrupt handler
246 * in case of a spurious interrupt.
248 AML_WDT_LOCK_INIT(sc);
250 if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
251 aml8726_wdt_intr, NULL, sc, &sc->ih_cookie)) {
252 device_printf(dev, "could not setup interrupt handler\n");
253 bus_release_resources(dev, aml8726_wdt_spec, sc->res);
254 AML_WDT_LOCK_DESTROY(sc);
260 EVENTHANDLER_REGISTER(watchdog_list, aml8726_wdt_watchdog, sc, 0);
266 aml8726_wdt_detach(device_t dev)
272 static device_method_t aml8726_wdt_methods[] = {
273 /* Device interface */
274 DEVMETHOD(device_probe, aml8726_wdt_probe),
275 DEVMETHOD(device_attach, aml8726_wdt_attach),
276 DEVMETHOD(device_detach, aml8726_wdt_detach),
281 static driver_t aml8726_wdt_driver = {
284 sizeof(struct aml8726_wdt_softc),
287 static devclass_t aml8726_wdt_devclass;
289 EARLY_DRIVER_MODULE(wdt, simplebus, aml8726_wdt_driver, aml8726_wdt_devclass,
290 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
296 /* Watchdog has not yet been initialized */
297 if (aml8726_wdt_sc == NULL)
298 printf("Reset hardware has not yet been initialized.\n");
300 CSR_WRITE_4(aml8726_wdt_sc, AML_WDT_RESET_REG, 0);
301 CSR_WRITE_4(aml8726_wdt_sc, AML_WDT_CTRL_REG,
302 (AML_WDT_CTRL_CPU_WDRESET_MASK | AML_WDT_CTRL_EN |
303 (10 << AML_WDT_CTRL_TERMINAL_CNT_SHIFT)));