2 * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 * NXP TDA19988 HDMI encoder
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/clock.h>
37 #include <sys/eventhandler.h>
40 #include <sys/resource.h>
42 #include <sys/types.h>
43 #include <sys/systm.h>
45 #include <dev/iicbus/iicbus.h>
46 #include <dev/iicbus/iiconf.h>
48 #include <dev/ofw/openfirm.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/videomode/videomode.h>
53 #include <dev/videomode/edidvar.h>
55 #include "iicbus_if.h"
58 #define MKREG(page, addr) (((page) << 8) | (addr))
60 #define REGPAGE(reg) (((reg) >> 8) & 0xff)
61 #define REGADDR(reg) ((reg) & 0xff)
63 #define TDA_VERSION MKREG(0x00, 0x00)
64 #define TDA_MAIN_CNTRL0 MKREG(0x00, 0x01)
65 #define MAIN_CNTRL0_SR (1 << 0)
66 #define TDA_VERSION_MSB MKREG(0x00, 0x02)
67 #define TDA_SOFTRESET MKREG(0x00, 0x0a)
68 #define SOFTRESET_I2C (1 << 1)
69 #define SOFTRESET_AUDIO (1 << 0)
70 #define TDA_DDC_CTRL MKREG(0x00, 0x0b)
72 #define TDA_CCLK MKREG(0x00, 0x0c)
74 #define TDA_INT_FLAGS_2 MKREG(0x00, 0x11)
75 #define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
77 #define TDA_VIP_CNTRL_0 MKREG(0x00, 0x20)
78 #define TDA_VIP_CNTRL_1 MKREG(0x00, 0x21)
79 #define TDA_VIP_CNTRL_2 MKREG(0x00, 0x22)
80 #define TDA_VIP_CNTRL_3 MKREG(0x00, 0x23)
81 #define VIP_CNTRL_3_SYNC_HS (2 << 4)
82 #define VIP_CNTRL_3_V_TGL (1 << 2)
83 #define VIP_CNTRL_3_H_TGL (1 << 1)
85 #define TDA_VIP_CNTRL_4 MKREG(0x00, 0x24)
86 #define VIP_CNTRL_4_BLANKIT_NDE (0 << 2)
87 #define VIP_CNTRL_4_BLANKIT_HS_VS (1 << 2)
88 #define VIP_CNTRL_4_BLANKIT_NHS_VS (2 << 2)
89 #define VIP_CNTRL_4_BLANKIT_HE_VE (3 << 2)
90 #define VIP_CNTRL_4_BLC_NONE (0 << 0)
91 #define VIP_CNTRL_4_BLC_RGB444 (1 << 0)
92 #define VIP_CNTRL_4_BLC_YUV444 (2 << 0)
93 #define VIP_CNTRL_4_BLC_YUV422 (3 << 0)
94 #define TDA_VIP_CNTRL_5 MKREG(0x00, 0x25)
95 #define VIP_CNTRL_5_SP_CNT(n) (((n) & 3) << 1)
96 #define TDA_MUX_VP_VIP_OUT MKREG(0x00, 0x27)
97 #define TDA_MAT_CONTRL MKREG(0x00, 0x80)
98 #define MAT_CONTRL_MAT_BP (1 << 2)
99 #define TDA_VIDFORMAT MKREG(0x00, 0xa0)
100 #define TDA_REFPIX_MSB MKREG(0x00, 0xa1)
101 #define TDA_REFPIX_LSB MKREG(0x00, 0xa2)
102 #define TDA_REFLINE_MSB MKREG(0x00, 0xa3)
103 #define TDA_REFLINE_LSB MKREG(0x00, 0xa4)
104 #define TDA_NPIX_MSB MKREG(0x00, 0xa5)
105 #define TDA_NPIX_LSB MKREG(0x00, 0xa6)
106 #define TDA_NLINE_MSB MKREG(0x00, 0xa7)
107 #define TDA_NLINE_LSB MKREG(0x00, 0xa8)
108 #define TDA_VS_LINE_STRT_1_MSB MKREG(0x00, 0xa9)
109 #define TDA_VS_LINE_STRT_1_LSB MKREG(0x00, 0xaa)
110 #define TDA_VS_PIX_STRT_1_MSB MKREG(0x00, 0xab)
111 #define TDA_VS_PIX_STRT_1_LSB MKREG(0x00, 0xac)
112 #define TDA_VS_LINE_END_1_MSB MKREG(0x00, 0xad)
113 #define TDA_VS_LINE_END_1_LSB MKREG(0x00, 0xae)
114 #define TDA_VS_PIX_END_1_MSB MKREG(0x00, 0xaf)
115 #define TDA_VS_PIX_END_1_LSB MKREG(0x00, 0xb0)
116 #define TDA_VS_LINE_STRT_2_MSB MKREG(0x00, 0xb1)
117 #define TDA_VS_LINE_STRT_2_LSB MKREG(0x00, 0xb2)
118 #define TDA_VS_PIX_STRT_2_MSB MKREG(0x00, 0xb3)
119 #define TDA_VS_PIX_STRT_2_LSB MKREG(0x00, 0xb4)
120 #define TDA_VS_LINE_END_2_MSB MKREG(0x00, 0xb5)
121 #define TDA_VS_LINE_END_2_LSB MKREG(0x00, 0xb6)
122 #define TDA_VS_PIX_END_2_MSB MKREG(0x00, 0xb7)
123 #define TDA_VS_PIX_END_2_LSB MKREG(0x00, 0xb8)
124 #define TDA_HS_PIX_START_MSB MKREG(0x00, 0xb9)
125 #define TDA_HS_PIX_START_LSB MKREG(0x00, 0xba)
126 #define TDA_HS_PIX_STOP_MSB MKREG(0x00, 0xbb)
127 #define TDA_HS_PIX_STOP_LSB MKREG(0x00, 0xbc)
128 #define TDA_VWIN_START_1_MSB MKREG(0x00, 0xbd)
129 #define TDA_VWIN_START_1_LSB MKREG(0x00, 0xbe)
130 #define TDA_VWIN_END_1_MSB MKREG(0x00, 0xbf)
131 #define TDA_VWIN_END_1_LSB MKREG(0x00, 0xc0)
132 #define TDA_VWIN_START_2_MSB MKREG(0x00, 0xc1)
133 #define TDA_VWIN_START_2_LSB MKREG(0x00, 0xc2)
134 #define TDA_VWIN_END_2_MSB MKREG(0x00, 0xc3)
135 #define TDA_VWIN_END_2_LSB MKREG(0x00, 0xc4)
136 #define TDA_DE_START_MSB MKREG(0x00, 0xc5)
137 #define TDA_DE_START_LSB MKREG(0x00, 0xc6)
138 #define TDA_DE_STOP_MSB MKREG(0x00, 0xc7)
139 #define TDA_DE_STOP_LSB MKREG(0x00, 0xc8)
141 #define TDA_TBG_CNTRL_0 MKREG(0x00, 0xca)
142 #define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
143 #define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
145 #define TDA_TBG_CNTRL_1 MKREG(0x00, 0xcb)
146 #define TBG_CNTRL_1_DWIN_DIS (1 << 6)
147 #define TBG_CNTRL_1_TGL_EN (1 << 2)
148 #define TBG_CNTRL_1_V_TGL (1 << 1)
149 #define TBG_CNTRL_1_H_TGL (1 << 0)
151 #define TDA_HVF_CNTRL_0 MKREG(0x00, 0xe4)
152 #define HVF_CNTRL_0_PREFIL_NONE (0 << 2)
153 #define HVF_CNTRL_0_INTPOL_BYPASS (0 << 0)
154 #define TDA_HVF_CNTRL_1 MKREG(0x00, 0xe5)
155 #define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
156 #define HVF_CNTRL_1_VQR_FULL HVF_CNTRL_1_VQR(0)
157 #define TDA_ENABLE_SPACE MKREG(0x00, 0xd6)
158 #define TDA_RPT_CNTRL MKREG(0x00, 0xf0)
160 #define TDA_PLL_SERIAL_1 MKREG(0x02, 0x00)
161 #define PLL_SERIAL_1_SRL_MAN_IP (1 << 6)
162 #define TDA_PLL_SERIAL_2 MKREG(0x02, 0x01)
163 #define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
164 #define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 0x3) << 0)
165 #define TDA_PLL_SERIAL_3 MKREG(0x02, 0x02)
166 #define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
167 #define PLL_SERIAL_3_SRL_DE (1 << 2)
168 #define PLL_SERIAL_3_SRL_CCIR (1 << 0)
169 #define TDA_SERIALIZER MKREG(0x02, 0x03)
170 #define TDA_BUFFER_OUT MKREG(0x02, 0x04)
171 #define TDA_PLL_SCG1 MKREG(0x02, 0x05)
172 #define TDA_PLL_SCG2 MKREG(0x02, 0x06)
173 #define TDA_PLL_SCGN1 MKREG(0x02, 0x07)
174 #define TDA_PLL_SCGN2 MKREG(0x02, 0x08)
175 #define TDA_PLL_SCGR1 MKREG(0x02, 0x09)
176 #define TDA_PLL_SCGR2 MKREG(0x02, 0x0a)
178 #define TDA_SEL_CLK MKREG(0x02, 0x11)
179 #define SEL_CLK_ENA_SC_CLK (1 << 3)
180 #define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
181 #define SEL_CLK_SEL_CLK1 (1 << 0)
182 #define TDA_ANA_GENERAL MKREG(0x02, 0x12)
184 #define TDA_EDID_DATA0 MKREG(0x09, 0x00)
185 #define TDA_EDID_CTRL MKREG(0x09, 0xfa)
186 #define TDA_DDC_ADDR MKREG(0x09, 0xfb)
187 #define TDA_DDC_OFFS MKREG(0x09, 0xfc)
188 #define TDA_DDC_SEGM_ADDR MKREG(0x09, 0xfd)
189 #define TDA_DDC_SEGM MKREG(0x09, 0xfe)
191 #define TDA_IF_VSP MKREG(0x10, 0x20)
192 #define TDA_IF_AVI MKREG(0x10, 0x40)
193 #define TDA_IF_SPD MKREG(0x10, 0x60)
194 #define TDA_IF_AUD MKREG(0x10, 0x80)
195 #define TDA_IF_MPS MKREG(0x10, 0xa0)
197 #define TDA_ENC_CNTRL MKREG(0x11, 0x0d)
198 #define ENC_CNTRL_DVI_MODE (0 << 2)
199 #define ENC_CNTRL_HDMI_MODE (1 << 2)
200 #define TDA_DIP_IF_FLAGS MKREG(0x11, 0x0f)
201 #define DIP_IF_FLAGS_IF5 (1 << 5)
202 #define DIP_IF_FLAGS_IF4 (1 << 4)
203 #define DIP_IF_FLAGS_IF3 (1 << 3)
204 #define DIP_IF_FLAGS_IF2 (1 << 2) /* AVI IF on page 10h */
205 #define DIP_IF_FLAGS_IF1 (1 << 1)
207 #define TDA_TX3 MKREG(0x12, 0x9a)
208 #define TDA_TX4 MKREG(0x12, 0x9b)
209 #define TX4_PD_RAM (1 << 1)
210 #define TDA_HDCP_TX33 MKREG(0x12, 0xb8)
211 #define HDCP_TX33_HDMI (1 << 1)
213 #define TDA_CURPAGE_ADDR 0xff
215 #define TDA_CEC_ENAMODS 0xff
216 #define ENAMODS_RXSENS (1 << 2)
217 #define ENAMODS_HDMI (1 << 1)
218 #define TDA_CEC_FRO_IM_CLK_CTRL 0xfb
219 #define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
220 #define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
223 #define EDID_LENGTH 0x80
224 #define MAX_READ_ATTEMPTS 100
227 #define EDID_MODES0 35
228 #define EDID_MODES1 36
229 #define EDID_TIMING_START 38
230 #define EDID_TIMING_END 54
231 #define EDID_TIMING_X(v) (((v) + 31) * 8)
232 #define EDID_FREQ(v) (((v) & 0x3f) + 60)
233 #define EDID_RATIO(v) (((v) >> 6) & 0x3)
234 #define EDID_RATIO_10x16 0
235 #define EDID_RATIO_3x4 1
236 #define EDID_RATIO_4x5 2
237 #define EDID_RATIO_9x16 3
239 #define TDA19988 0x0301
241 struct tda19988_softc {
244 uint32_t sc_cec_addr;
246 struct intr_config_hook enum_hook;
249 uint32_t sc_edid_len;
253 tda19988_set_page(struct tda19988_softc *sc, uint8_t page)
255 uint8_t addr = TDA_CURPAGE_ADDR;
258 struct iic_msg msg[] = {
259 { sc->sc_addr, IIC_M_WR, 2, cmd },
265 result = (iicbus_transfer(sc->sc_dev, msg, 1));
267 printf("tda19988_set_page failed: %d\n", result);
269 sc->sc_current_page = page;
275 tda19988_cec_read(struct tda19988_softc *sc, uint8_t addr, uint8_t *data)
278 struct iic_msg msg[] = {
279 { sc->sc_cec_addr, IIC_M_WR, 1, &addr },
280 { sc->sc_cec_addr, IIC_M_RD, 1, data },
283 result = iicbus_transfer(sc->sc_dev, msg, 2);
285 printf("tda19988_cec_read failed: %d\n", result);
290 tda19988_cec_write(struct tda19988_softc *sc, uint8_t address, uint8_t data)
294 struct iic_msg msg[] = {
295 { sc->sc_cec_addr, IIC_M_WR, 2, cmd },
301 result = iicbus_transfer(sc->sc_dev, msg, 1);
303 printf("tda19988_cec_write failed: %d\n", result);
308 tda19988_block_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data, int len)
312 struct iic_msg msg[] = {
313 { sc->sc_addr, IIC_M_WR, 1, ® },
314 { sc->sc_addr, IIC_M_RD, len, data },
319 if (sc->sc_current_page != REGPAGE(addr))
320 tda19988_set_page(sc, REGPAGE(addr));
322 result = (iicbus_transfer(sc->sc_dev, msg, 2));
324 device_printf(sc->sc_dev, "tda19988_block_read failed: %d\n", result);
329 tda19988_reg_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data)
333 struct iic_msg msg[] = {
334 { sc->sc_addr, IIC_M_WR, 1, ® },
335 { sc->sc_addr, IIC_M_RD, 1, data },
340 if (sc->sc_current_page != REGPAGE(addr))
341 tda19988_set_page(sc, REGPAGE(addr));
343 result = (iicbus_transfer(sc->sc_dev, msg, 2));
345 device_printf(sc->sc_dev, "tda19988_reg_read failed: %d\n", result);
350 tda19988_reg_write(struct tda19988_softc *sc, uint16_t address, uint8_t data)
354 struct iic_msg msg[] = {
355 { sc->sc_addr, IIC_M_WR, 2, cmd },
358 cmd[0] = REGADDR(address);
361 if (sc->sc_current_page != REGPAGE(address))
362 tda19988_set_page(sc, REGPAGE(address));
364 result = iicbus_transfer(sc->sc_dev, msg, 1);
366 device_printf(sc->sc_dev, "tda19988_reg_write failed: %d\n", result);
372 tda19988_reg_write2(struct tda19988_softc *sc, uint16_t address, uint16_t data)
376 struct iic_msg msg[] = {
377 { sc->sc_addr, IIC_M_WR, 3, cmd },
380 cmd[0] = REGADDR(address);
381 cmd[1] = (data >> 8);
382 cmd[2] = (data & 0xff);
384 if (sc->sc_current_page != REGPAGE(address))
385 tda19988_set_page(sc, REGPAGE(address));
387 result = iicbus_transfer(sc->sc_dev, msg, 1);
389 device_printf(sc->sc_dev, "tda19988_reg_write2 failed: %d\n", result);
395 tda19988_reg_set(struct tda19988_softc *sc, uint16_t addr, uint8_t flags)
399 tda19988_reg_read(sc, addr, &data);
401 tda19988_reg_write(sc, addr, data);
405 tda19988_reg_clear(struct tda19988_softc *sc, uint16_t addr, uint8_t flags)
409 tda19988_reg_read(sc, addr, &data);
411 tda19988_reg_write(sc, addr, data);
415 tda19988_probe(device_t dev)
418 if (!ofw_bus_is_compatible(dev, "nxp,tda998x"))
421 return (BUS_PROBE_DEFAULT);
425 tda19988_init_encoder(struct tda19988_softc *sc, const struct videomode *mode)
427 uint16_t ref_pix, ref_line, n_pix, n_line;
428 uint16_t hs_pix_start, hs_pix_stop;
429 uint16_t vs1_pix_start, vs1_pix_stop;
430 uint16_t vs1_line_start, vs1_line_end;
431 uint16_t vs2_pix_start, vs2_pix_stop;
432 uint16_t vs2_line_start, vs2_line_end;
433 uint16_t vwin1_line_start, vwin1_line_end;
434 uint16_t vwin2_line_start, vwin2_line_end;
435 uint16_t de_start, de_stop;
438 n_pix = mode->htotal;
439 n_line = mode->vtotal;
441 hs_pix_stop = mode->hsync_end - mode->hdisplay;
442 hs_pix_start = mode->hsync_start - mode->hdisplay;
444 de_stop = mode->htotal;
445 de_start = mode->htotal - mode->hdisplay;
446 ref_pix = hs_pix_start + 3;
448 if (mode->flags & VID_HSKEW)
449 ref_pix += mode->hskew;
451 if ((mode->flags & VID_INTERLACE) == 0) {
452 ref_line = 1 + mode->vsync_start - mode->vdisplay;
453 vwin1_line_start = mode->vtotal - mode->vdisplay - 1;
454 vwin1_line_end = vwin1_line_start + mode->vdisplay;
456 vs1_pix_start = vs1_pix_stop = hs_pix_start;
457 vs1_line_start = mode->vsync_start - mode->vdisplay;
458 vs1_line_end = vs1_line_start + mode->vsync_end - mode->vsync_start;
460 vwin2_line_start = vwin2_line_end = 0;
461 vs2_pix_start = vs2_pix_stop = 0;
462 vs2_line_start = vs2_line_end = 0;
464 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
465 vwin1_line_start = (mode->vtotal - mode->vdisplay)/2;
466 vwin1_line_end = vwin1_line_start + mode->vdisplay/2;
468 vs1_pix_start = vs1_pix_stop = hs_pix_start;
469 vs1_line_start = (mode->vsync_start - mode->vdisplay)/2;
470 vs1_line_end = vs1_line_start + (mode->vsync_end - mode->vsync_start)/2;
472 vwin2_line_start = vwin1_line_start + mode->vtotal/2;
473 vwin2_line_end = vwin2_line_start + mode->vdisplay/2;
475 vs2_pix_start = vs2_pix_stop = hs_pix_start + mode->htotal/2;
476 vs2_line_start = vs1_line_start + mode->vtotal/2 ;
477 vs2_line_end = vs2_line_start + (mode->vsync_end - mode->vsync_start)/2;
480 div = 148500 / mode->dot_clock;
487 /* set HDMI HDCP mode off */
488 tda19988_reg_set(sc, TDA_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
489 tda19988_reg_clear(sc, TDA_HDCP_TX33, HDCP_TX33_HDMI);
490 tda19988_reg_write(sc, TDA_ENC_CNTRL, ENC_CNTRL_DVI_MODE);
492 /* no pre-filter or interpolator */
493 tda19988_reg_write(sc, TDA_HVF_CNTRL_0,
494 HVF_CNTRL_0_INTPOL_BYPASS | HVF_CNTRL_0_PREFIL_NONE);
495 tda19988_reg_write(sc, TDA_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
496 tda19988_reg_write(sc, TDA_VIP_CNTRL_4,
497 VIP_CNTRL_4_BLANKIT_NDE | VIP_CNTRL_4_BLC_NONE);
499 tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR);
500 tda19988_reg_clear(sc, TDA_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IP);
501 tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE);
502 tda19988_reg_write(sc, TDA_SERIALIZER, 0);
503 tda19988_reg_write(sc, TDA_HVF_CNTRL_1, HVF_CNTRL_1_VQR_FULL);
505 tda19988_reg_write(sc, TDA_RPT_CNTRL, 0);
506 tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
507 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
509 tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
510 PLL_SERIAL_2_SRL_PR(0));
512 tda19988_reg_set(sc, TDA_MAT_CONTRL, MAT_CONTRL_MAT_BP);
514 tda19988_reg_write(sc, TDA_ANA_GENERAL, 0x09);
516 tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD);
519 * Sync on rising HSYNC/VSYNC
521 reg = VIP_CNTRL_3_SYNC_HS;
522 if (mode->flags & VID_NHSYNC)
523 reg |= VIP_CNTRL_3_H_TGL;
524 if (mode->flags & VID_NVSYNC)
525 reg |= VIP_CNTRL_3_V_TGL;
526 tda19988_reg_write(sc, TDA_VIP_CNTRL_3, reg);
528 reg = TBG_CNTRL_1_TGL_EN;
529 if (mode->flags & VID_NHSYNC)
530 reg |= TBG_CNTRL_1_H_TGL;
531 if (mode->flags & VID_NVSYNC)
532 reg |= TBG_CNTRL_1_V_TGL;
533 tda19988_reg_write(sc, TDA_TBG_CNTRL_1, reg);
536 tda19988_reg_write(sc, TDA_VIDFORMAT, 0x00);
538 tda19988_reg_write2(sc, TDA_REFPIX_MSB, ref_pix);
539 tda19988_reg_write2(sc, TDA_REFLINE_MSB, ref_line);
540 tda19988_reg_write2(sc, TDA_NPIX_MSB, n_pix);
541 tda19988_reg_write2(sc, TDA_NLINE_MSB, n_line);
543 tda19988_reg_write2(sc, TDA_VS_LINE_STRT_1_MSB, vs1_line_start);
544 tda19988_reg_write2(sc, TDA_VS_PIX_STRT_1_MSB, vs1_pix_start);
545 tda19988_reg_write2(sc, TDA_VS_LINE_END_1_MSB, vs1_line_end);
546 tda19988_reg_write2(sc, TDA_VS_PIX_END_1_MSB, vs1_pix_stop);
547 tda19988_reg_write2(sc, TDA_VS_LINE_STRT_2_MSB, vs2_line_start);
548 tda19988_reg_write2(sc, TDA_VS_PIX_STRT_2_MSB, vs2_pix_start);
549 tda19988_reg_write2(sc, TDA_VS_LINE_END_2_MSB, vs2_line_end);
550 tda19988_reg_write2(sc, TDA_VS_PIX_END_2_MSB, vs2_pix_stop);
551 tda19988_reg_write2(sc, TDA_HS_PIX_START_MSB, hs_pix_start);
552 tda19988_reg_write2(sc, TDA_HS_PIX_STOP_MSB, hs_pix_stop);
553 tda19988_reg_write2(sc, TDA_VWIN_START_1_MSB, vwin1_line_start);
554 tda19988_reg_write2(sc, TDA_VWIN_END_1_MSB, vwin1_line_end);
555 tda19988_reg_write2(sc, TDA_VWIN_START_2_MSB, vwin2_line_start);
556 tda19988_reg_write2(sc, TDA_VWIN_END_2_MSB, vwin2_line_end);
557 tda19988_reg_write2(sc, TDA_DE_START_MSB, de_start);
558 tda19988_reg_write2(sc, TDA_DE_STOP_MSB, de_stop);
560 if (sc->sc_version == TDA19988)
561 tda19988_reg_write(sc, TDA_ENABLE_SPACE, 0x00);
563 /* must be last register set */
564 tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
568 tda19988_read_edid_block(struct tda19988_softc *sc, uint8_t *buf, int block)
575 tda19988_reg_set(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
578 tda19988_reg_write(sc, TDA_DDC_ADDR, 0xa0);
579 tda19988_reg_write(sc, TDA_DDC_OFFS, (block % 2) ? 128 : 0);
580 tda19988_reg_write(sc, TDA_DDC_SEGM_ADDR, 0x60);
581 tda19988_reg_write(sc, TDA_DDC_SEGM, block / 2);
583 tda19988_reg_write(sc, TDA_EDID_CTRL, 1);
584 tda19988_reg_write(sc, TDA_EDID_CTRL, 0);
587 for (attempt = 0; attempt < MAX_READ_ATTEMPTS; attempt++) {
588 tda19988_reg_read(sc, TDA_INT_FLAGS_2, &data);
589 if (data & INT_FLAGS_2_EDID_BLK_RD)
594 if (attempt == MAX_READ_ATTEMPTS) {
599 if (tda19988_block_read(sc, TDA_EDID_DATA0, buf, EDID_LENGTH) != 0) {
605 tda19988_reg_clear(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
611 tda19988_read_edid(struct tda19988_softc *sc)
618 if (sc->sc_version == TDA19988)
619 tda19988_reg_clear(sc, TDA_TX4, TX4_PD_RAM);
621 err = tda19988_read_edid_block(sc, sc->sc_edid, 0);
625 blocks = sc->sc_edid[0x7e];
627 sc->sc_edid = realloc(sc->sc_edid,
628 EDID_LENGTH*(blocks+1), M_DEVBUF, M_WAITOK);
629 sc->sc_edid_len = EDID_LENGTH*(blocks+1);
630 for (i = 0; i < blocks; i++) {
631 /* TODO: check validity */
632 buf = sc->sc_edid + EDID_LENGTH*(i+1);
633 err = tda19988_read_edid_block(sc, buf, i);
639 EVENTHANDLER_INVOKE(hdmi_event, sc->sc_dev, HDMI_EVENT_CONNECTED);
641 if (sc->sc_version == TDA19988)
642 tda19988_reg_set(sc, TDA_TX4, TX4_PD_RAM);
648 tda19988_start(void *xdev)
650 struct tda19988_softc *sc;
651 device_t dev = (device_t)xdev;
655 sc = device_get_softc(dev);
657 tda19988_cec_write(sc, TDA_CEC_ENAMODS, ENAMODS_RXSENS | ENAMODS_HDMI);
659 tda19988_cec_read(sc, 0xfe, &data);
662 tda19988_reg_set(sc, TDA_SOFTRESET, 3);
664 tda19988_reg_clear(sc, TDA_SOFTRESET, 3);
667 /* reset transmitter: */
668 tda19988_reg_set(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR);
669 tda19988_reg_clear(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR);
671 /* PLL registers common configuration */
672 tda19988_reg_write(sc, TDA_PLL_SERIAL_1, 0x00);
673 tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
674 tda19988_reg_write(sc, TDA_PLL_SERIAL_3, 0x00);
675 tda19988_reg_write(sc, TDA_SERIALIZER, 0x00);
676 tda19988_reg_write(sc, TDA_BUFFER_OUT, 0x00);
677 tda19988_reg_write(sc, TDA_PLL_SCG1, 0x00);
678 tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
679 tda19988_reg_write(sc, TDA_PLL_SCGN1, 0xfa);
680 tda19988_reg_write(sc, TDA_PLL_SCGN2, 0x00);
681 tda19988_reg_write(sc, TDA_PLL_SCGR1, 0x5b);
682 tda19988_reg_write(sc, TDA_PLL_SCGR2, 0x00);
683 tda19988_reg_write(sc, TDA_PLL_SCG2, 0x10);
685 /* Write the default value MUX register */
686 tda19988_reg_write(sc, TDA_MUX_VP_VIP_OUT, 0x24);
689 tda19988_reg_read(sc, TDA_VERSION, &data);
691 tda19988_reg_read(sc, TDA_VERSION_MSB, &data);
692 version |= (data << 8);
694 /* Clear feature bits */
695 sc->sc_version = version & ~0x30;
696 switch (sc->sc_version) {
698 device_printf(dev, "TDA19988\n");
701 device_printf(dev, "Unknown device: %04x\n", sc->sc_version);
705 tda19988_reg_write(sc, TDA_DDC_CTRL, DDC_ENABLE);
706 tda19988_reg_write(sc, TDA_TX3, 39);
708 tda19988_cec_write(sc, TDA_CEC_FRO_IM_CLK_CTRL,
709 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
711 if (tda19988_read_edid(sc) < 0) {
712 device_printf(dev, "failed to read EDID\n");
716 /* Default values for RGB 4:4:4 mapping */
717 tda19988_reg_write(sc, TDA_VIP_CNTRL_0, 0x23);
718 tda19988_reg_write(sc, TDA_VIP_CNTRL_1, 0x01);
719 tda19988_reg_write(sc, TDA_VIP_CNTRL_2, 0x45);
722 config_intrhook_disestablish(&sc->enum_hook);
726 tda19988_attach(device_t dev)
728 struct tda19988_softc *sc;
731 sc = device_get_softc(dev);
734 sc->sc_addr = iicbus_get_addr(dev);
735 sc->sc_cec_addr = (0x34 << 1); /* hardcoded */
736 sc->sc_edid = malloc(EDID_LENGTH, M_DEVBUF, M_WAITOK | M_ZERO);
737 sc->sc_edid_len = EDID_LENGTH;
739 device_set_desc(dev, "NXP TDA19988 HDMI transmitter");
741 sc->enum_hook.ich_func = tda19988_start;
742 sc->enum_hook.ich_arg = dev;
744 if (config_intrhook_establish(&sc->enum_hook) != 0)
747 node = ofw_bus_get_node(dev);
748 OF_device_register_xref(OF_xref_from_node(node), dev);
754 tda19988_detach(device_t dev)
757 /* XXX: Do not let unload drive */
762 tda19988_get_edid(device_t dev, uint8_t **edid, uint32_t *edid_len)
764 struct tda19988_softc *sc;
766 sc = device_get_softc(dev);
770 *edid_len = sc->sc_edid_len;
778 tda19988_set_videomode(device_t dev, const struct videomode *mode)
780 struct tda19988_softc *sc;
782 sc = device_get_softc(dev);
784 tda19988_init_encoder(sc, mode);
789 static device_method_t tda_methods[] = {
790 DEVMETHOD(device_probe, tda19988_probe),
791 DEVMETHOD(device_attach, tda19988_attach),
792 DEVMETHOD(device_detach, tda19988_detach),
795 DEVMETHOD(hdmi_get_edid, tda19988_get_edid),
796 DEVMETHOD(hdmi_set_videomode, tda19988_set_videomode),
800 static driver_t tda_driver = {
803 sizeof(struct tda19988_softc),
806 static devclass_t tda_devclass;
808 DRIVER_MODULE(tda, iicbus, tda_driver, tda_devclass, 0, 0);
809 MODULE_VERSION(tda, 1);
810 MODULE_DEPEND(tda, iicbus, 1, 1, 1);