sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/eventhandler.h>
  31 #include <sys/sockio.h>
  32 #include <machine/atomic.h>
  33
  34 #ifndef ETH_DRIVER_VERSION
  35 #define ETH_DRIVER_VERSION      "3.5.1"
  36 #endif
  37 #define DRIVER_RELDATE  "April 2019"
  38
  39 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  40         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  41
  42 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  43
  44 struct mlx5e_channel_param {
  45         struct mlx5e_rq_param rq;
  46         struct mlx5e_sq_param sq;
  47         struct mlx5e_cq_param rx_cq;
  48         struct mlx5e_cq_param tx_cq;
  49 };
  50
  51 struct media {
  52         u32     subtype;
  53         u64     baudrate;
  54 };
  55
  56 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
  57
  58         [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
  59                 .subtype = IFM_1000_CX_SGMII,
  60                 .baudrate = IF_Mbps(1000ULL),
  61         },
  62         [MLX5E_1000BASE_KX][MLX5E_KX] = {
  63                 .subtype = IFM_1000_KX,
  64                 .baudrate = IF_Mbps(1000ULL),
  65         },
  66         [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
  67                 .subtype = IFM_10G_CX4,
  68                 .baudrate = IF_Gbps(10ULL),
  69         },
  70         [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
  71                 .subtype = IFM_10G_KX4,
  72                 .baudrate = IF_Gbps(10ULL),
  73         },
  74         [MLX5E_10GBASE_KR][MLX5E_KR] = {
  75                 .subtype = IFM_10G_KR,
  76                 .baudrate = IF_Gbps(10ULL),
  77         },
  78         [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
  79                 .subtype = IFM_20G_KR2,
  80                 .baudrate = IF_Gbps(20ULL),
  81         },
  82         [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
  83                 .subtype = IFM_40G_CR4,
  84                 .baudrate = IF_Gbps(40ULL),
  85         },
  86         [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
  87                 .subtype = IFM_40G_KR4,
  88                 .baudrate = IF_Gbps(40ULL),
  89         },
  90         [MLX5E_56GBASE_R4][MLX5E_R] = {
  91                 .subtype = IFM_56G_R4,
  92                 .baudrate = IF_Gbps(56ULL),
  93         },
  94         [MLX5E_10GBASE_CR][MLX5E_CR1] = {
  95                 .subtype = IFM_10G_CR1,
  96                 .baudrate = IF_Gbps(10ULL),
  97         },
  98         [MLX5E_10GBASE_SR][MLX5E_SR] = {
  99                 .subtype = IFM_10G_SR,
 100                 .baudrate = IF_Gbps(10ULL),
 101         },
 102         [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
 103                 .subtype = IFM_10G_ER,
 104                 .baudrate = IF_Gbps(10ULL),
 105         },
 106         [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
 107                 .subtype = IFM_10G_LR,
 108                 .baudrate = IF_Gbps(10ULL),
 109         },
 110         [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
 111                 .subtype = IFM_40G_SR4,
 112                 .baudrate = IF_Gbps(40ULL),
 113         },
 114         [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
 115                 .subtype = IFM_40G_LR4,
 116                 .baudrate = IF_Gbps(40ULL),
 117         },
 118         [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
 119                 .subtype = IFM_40G_ER4,
 120                 .baudrate = IF_Gbps(40ULL),
 121         },
 122         [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
 123                 .subtype = IFM_100G_CR4,
 124                 .baudrate = IF_Gbps(100ULL),
 125         },
 126         [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
 127                 .subtype = IFM_100G_SR4,
 128                 .baudrate = IF_Gbps(100ULL),
 129         },
 130         [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
 131                 .subtype = IFM_100G_KR4,
 132                 .baudrate = IF_Gbps(100ULL),
 133         },
 134         [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
 135                 .subtype = IFM_100G_LR4,
 136                 .baudrate = IF_Gbps(100ULL),
 137         },
 138         [MLX5E_100BASE_TX][MLX5E_TX] = {
 139                 .subtype = IFM_100_TX,
 140                 .baudrate = IF_Mbps(100ULL),
 141         },
 142         [MLX5E_1000BASE_T][MLX5E_T] = {
 143                 .subtype = IFM_1000_T,
 144                 .baudrate = IF_Mbps(1000ULL),
 145         },
 146         [MLX5E_10GBASE_T][MLX5E_T] = {
 147                 .subtype = IFM_10G_T,
 148                 .baudrate = IF_Gbps(10ULL),
 149         },
 150         [MLX5E_25GBASE_CR][MLX5E_CR] = {
 151                 .subtype = IFM_25G_CR,
 152                 .baudrate = IF_Gbps(25ULL),
 153         },
 154         [MLX5E_25GBASE_KR][MLX5E_KR] = {
 155                 .subtype = IFM_25G_KR,
 156                 .baudrate = IF_Gbps(25ULL),
 157         },
 158         [MLX5E_25GBASE_SR][MLX5E_SR] = {
 159                 .subtype = IFM_25G_SR,
 160                 .baudrate = IF_Gbps(25ULL),
 161         },
 162         [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
 163                 .subtype = IFM_50G_CR2,
 164                 .baudrate = IF_Gbps(50ULL),
 165         },
 166         [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
 167                 .subtype = IFM_50G_KR2,
 168                 .baudrate = IF_Gbps(50ULL),
 169         },
 170 };
 171
 172 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
 173         [MLX5E_SGMII_100M][MLX5E_SGMII] = {
 174                 .subtype = IFM_100_SGMII,
 175                 .baudrate = IF_Mbps(100),
 176         },
 177         [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
 178                 .subtype = IFM_1000_KX,
 179                 .baudrate = IF_Mbps(1000),
 180         },
 181         [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
 182                 .subtype = IFM_1000_CX_SGMII,
 183                 .baudrate = IF_Mbps(1000),
 184         },
 185         [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
 186                 .subtype = IFM_1000_CX,
 187                 .baudrate = IF_Mbps(1000),
 188         },
 189         [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
 190                 .subtype = IFM_1000_LX,
 191                 .baudrate = IF_Mbps(1000),
 192         },
 193         [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
 194                 .subtype = IFM_1000_SX,
 195                 .baudrate = IF_Mbps(1000),
 196         },
 197         [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
 198                 .subtype = IFM_1000_T,
 199                 .baudrate = IF_Mbps(1000),
 200         },
 201         [MLX5E_5GBASE_R][MLX5E_T] = {
 202                 .subtype = IFM_5000_T,
 203                 .baudrate = IF_Mbps(5000),
 204         },
 205         [MLX5E_5GBASE_R][MLX5E_KR] = {
 206                 .subtype = IFM_5000_KR,
 207                 .baudrate = IF_Mbps(5000),
 208         },
 209         [MLX5E_5GBASE_R][MLX5E_KR1] = {
 210                 .subtype = IFM_5000_KR1,
 211                 .baudrate = IF_Mbps(5000),
 212         },
 213         [MLX5E_5GBASE_R][MLX5E_KR_S] = {
 214                 .subtype = IFM_5000_KR_S,
 215                 .baudrate = IF_Mbps(5000),
 216         },
 217         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
 218                 .subtype = IFM_10G_ER,
 219                 .baudrate = IF_Gbps(10ULL),
 220         },
 221         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
 222                 .subtype = IFM_10G_KR,
 223                 .baudrate = IF_Gbps(10ULL),
 224         },
 225         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
 226                 .subtype = IFM_10G_LR,
 227                 .baudrate = IF_Gbps(10ULL),
 228         },
 229         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
 230                 .subtype = IFM_10G_SR,
 231                 .baudrate = IF_Gbps(10ULL),
 232         },
 233         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
 234                 .subtype = IFM_10G_T,
 235                 .baudrate = IF_Gbps(10ULL),
 236         },
 237         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
 238                 .subtype = IFM_10G_AOC,
 239                 .baudrate = IF_Gbps(10ULL),
 240         },
 241         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
 242                 .subtype = IFM_10G_CR1,
 243                 .baudrate = IF_Gbps(10ULL),
 244         },
 245         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
 246                 .subtype = IFM_40G_CR4,
 247                 .baudrate = IF_Gbps(40ULL),
 248         },
 249         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
 250                 .subtype = IFM_40G_KR4,
 251                 .baudrate = IF_Gbps(40ULL),
 252         },
 253         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
 254                 .subtype = IFM_40G_LR4,
 255                 .baudrate = IF_Gbps(40ULL),
 256         },
 257         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
 258                 .subtype = IFM_40G_SR4,
 259                 .baudrate = IF_Gbps(40ULL),
 260         },
 261         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
 262                 .subtype = IFM_40G_ER4,
 263                 .baudrate = IF_Gbps(40ULL),
 264         },
 265
 266         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
 267                 .subtype = IFM_25G_CR,
 268                 .baudrate = IF_Gbps(25ULL),
 269         },
 270         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
 271                 .subtype = IFM_25G_KR,
 272                 .baudrate = IF_Gbps(25ULL),
 273         },
 274         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
 275                 .subtype = IFM_25G_SR,
 276                 .baudrate = IF_Gbps(25ULL),
 277         },
 278         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
 279                 .subtype = IFM_25G_ACC,
 280                 .baudrate = IF_Gbps(25ULL),
 281         },
 282         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
 283                 .subtype = IFM_25G_AOC,
 284                 .baudrate = IF_Gbps(25ULL),
 285         },
 286         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
 287                 .subtype = IFM_25G_CR1,
 288                 .baudrate = IF_Gbps(25ULL),
 289         },
 290         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
 291                 .subtype = IFM_25G_CR_S,
 292                 .baudrate = IF_Gbps(25ULL),
 293         },
 294         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
 295                 .subtype = IFM_5000_KR1,
 296                 .baudrate = IF_Gbps(25ULL),
 297         },
 298         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
 299                 .subtype = IFM_25G_KR_S,
 300                 .baudrate = IF_Gbps(25ULL),
 301         },
 302         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
 303                 .subtype = IFM_25G_LR,
 304                 .baudrate = IF_Gbps(25ULL),
 305         },
 306         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
 307                 .subtype = IFM_25G_T,
 308                 .baudrate = IF_Gbps(25ULL),
 309         },
 310         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
 311                 .subtype = IFM_50G_CR2,
 312                 .baudrate = IF_Gbps(50ULL),
 313         },
 314         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
 315                 .subtype = IFM_50G_KR2,
 316                 .baudrate = IF_Gbps(50ULL),
 317         },
 318         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
 319                 .subtype = IFM_50G_SR2,
 320                 .baudrate = IF_Gbps(50ULL),
 321         },
 322         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
 323                 .subtype = IFM_50G_LR2,
 324                 .baudrate = IF_Gbps(50ULL),
 325         },
 326         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
 327                 .subtype = IFM_50G_LR,
 328                 .baudrate = IF_Gbps(50ULL),
 329         },
 330         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
 331                 .subtype = IFM_50G_SR,
 332                 .baudrate = IF_Gbps(50ULL),
 333         },
 334         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
 335                 .subtype = IFM_50G_CP,
 336                 .baudrate = IF_Gbps(50ULL),
 337         },
 338         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
 339                 .subtype = IFM_50G_FR,
 340                 .baudrate = IF_Gbps(50ULL),
 341         },
 342         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
 343                 .subtype = IFM_50G_KR_PAM4,
 344                 .baudrate = IF_Gbps(50ULL),
 345         },
 346         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
 347                 .subtype = IFM_100G_CR4,
 348                 .baudrate = IF_Gbps(100ULL),
 349         },
 350         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
 351                 .subtype = IFM_100G_KR4,
 352                 .baudrate = IF_Gbps(100ULL),
 353         },
 354         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
 355                 .subtype = IFM_100G_LR4,
 356                 .baudrate = IF_Gbps(100ULL),
 357         },
 358         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
 359                 .subtype = IFM_100G_SR4,
 360                 .baudrate = IF_Gbps(100ULL),
 361         },
 362         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
 363                 .subtype = IFM_100G_SR2,
 364                 .baudrate = IF_Gbps(100ULL),
 365         },
 366         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
 367                 .subtype = IFM_100G_CP2,
 368                 .baudrate = IF_Gbps(100ULL),
 369         },
 370         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
 371                 .subtype = IFM_100G_KR2_PAM4,
 372                 .baudrate = IF_Gbps(100ULL),
 373         },
 374         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
 375                 .subtype = IFM_200G_DR4,
 376                 .baudrate = IF_Gbps(200ULL),
 377         },
 378         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
 379                 .subtype = IFM_200G_LR4,
 380                 .baudrate = IF_Gbps(200ULL),
 381         },
 382         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
 383                 .subtype = IFM_200G_SR4,
 384                 .baudrate = IF_Gbps(200ULL),
 385         },
 386         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
 387                 .subtype = IFM_200G_FR4,
 388                 .baudrate = IF_Gbps(200ULL),
 389         },
 390         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
 391                 .subtype = IFM_200G_CR4_PAM4,
 392                 .baudrate = IF_Gbps(200ULL),
 393         },
 394         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
 395                 .subtype = IFM_200G_KR4_PAM4,
 396                 .baudrate = IF_Gbps(200ULL),
 397         },
 398 };
 399
 400 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 401
 402 static void
 403 mlx5e_update_carrier(struct mlx5e_priv *priv)
 404 {
 405         struct mlx5_core_dev *mdev = priv->mdev;
 406         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 407         u32 eth_proto_oper;
 408         int error;
 409         u8 port_state;
 410         u8 is_er_type;
 411         u8 i, j;
 412         bool ext;
 413         struct media media_entry = {};
 414
 415         port_state = mlx5_query_vport_state(mdev,
 416             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 417
 418         if (port_state == VPORT_STATE_UP) {
 419                 priv->media_status_last |= IFM_ACTIVE;
 420         } else {
 421                 priv->media_status_last &= ~IFM_ACTIVE;
 422                 priv->media_active_last = IFM_ETHER;
 423                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 424                 return;
 425         }
 426
 427         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 428             MLX5_PTYS_EN, 1);
 429         if (error) {
 430                 priv->media_active_last = IFM_ETHER;
 431                 priv->ifp->if_baudrate = 1;
 432                 if_printf(priv->ifp, "%s: query port ptys failed: "
 433                     "0x%x\n", __func__, error);
 434                 return;
 435         }
 436
 437         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 438         eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 439             eth_proto_oper);
 440
 441         i = ilog2(eth_proto_oper);
 442
 443         for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
 444                 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 445                     mlx5e_mode_table[i][j];
 446                 if (media_entry.baudrate != 0)
 447                         break;
 448         }
 449
 450         if (media_entry.subtype == 0) {
 451                 if_printf(priv->ifp, "%s: Could not find operational "
 452                     "media subtype\n", __func__);
 453                 return;
 454         }
 455
 456         switch (media_entry.subtype) {
 457         case IFM_10G_ER:
 458                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 459                 if (error != 0) {
 460                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 461                                   __func__, error);
 462                 }
 463                 if (error != 0 || is_er_type == 0)
 464                         media_entry.subtype = IFM_10G_LR;
 465                 break;
 466         case IFM_40G_LR4:
 467                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 468                 if (error != 0) {
 469                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 470                                   __func__, error);
 471                 }
 472                 if (error == 0 && is_er_type != 0)
 473                         media_entry.subtype = IFM_40G_ER4;
 474                 break;
 475         }
 476         priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
 477         priv->ifp->if_baudrate = media_entry.baudrate;
 478
 479         if_link_state_change(priv->ifp, LINK_STATE_UP);
 480 }
 481
 482 static void
 483 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 484 {
 485         struct mlx5e_priv *priv = dev->if_softc;
 486
 487         ifmr->ifm_status = priv->media_status_last;
 488         ifmr->ifm_active = priv->media_active_last |
 489             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 490             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 491
 492 }
 493
 494 static u32
 495 mlx5e_find_link_mode(u32 subtype, bool ext)
 496 {
 497         u32 i;
 498         u32 j;
 499         u32 link_mode = 0;
 500         u32 speeds_num = 0;
 501         struct media media_entry = {};
 502
 503         switch (subtype) {
 504         case IFM_10G_LR:
 505                 subtype = IFM_10G_ER;
 506                 break;
 507         case IFM_40G_ER4:
 508                 subtype = IFM_40G_LR4;
 509                 break;
 510         }
 511
 512         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
 513             MLX5E_LINK_SPEEDS_NUMBER;
 514
 515         for (i = 0; i != speeds_num; i++) {
 516                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
 517                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 518                             mlx5e_mode_table[i][j];
 519                         if (media_entry.baudrate == 0)
 520                                 continue;
 521                         if (media_entry.subtype == subtype) {
 522                                 link_mode |= MLX5E_PROT_MASK(i);
 523                         }
 524                 }
 525         }
 526
 527         return (link_mode);
 528 }
 529
 530 static int
 531 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 532 {
 533         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 534             priv->params.rx_pauseframe_control,
 535             priv->params.tx_pauseframe_control,
 536             priv->params.rx_priority_flow_control,
 537             priv->params.tx_priority_flow_control));
 538 }
 539
 540 static int
 541 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 542 {
 543         int error;
 544
 545         if (priv->gone != 0) {
 546                 error = -ENXIO;
 547         } else if (priv->params.rx_pauseframe_control ||
 548             priv->params.tx_pauseframe_control) {
 549                 if_printf(priv->ifp,
 550                     "Global pauseframes must be disabled before "
 551                     "enabling PFC.\n");
 552                 error = -EINVAL;
 553         } else {
 554                 error = mlx5e_set_port_pause_and_pfc(priv);
 555         }
 556         return (error);
 557 }
 558
 559 static int
 560 mlx5e_media_change(struct ifnet *dev)
 561 {
 562         struct mlx5e_priv *priv = dev->if_softc;
 563         struct mlx5_core_dev *mdev = priv->mdev;
 564         u32 eth_proto_cap;
 565         u32 link_mode;
 566         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 567         int was_opened;
 568         int locked;
 569         int error;
 570         bool ext;
 571
 572         locked = PRIV_LOCKED(priv);
 573         if (!locked)
 574                 PRIV_LOCK(priv);
 575
 576         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 577                 error = EINVAL;
 578                 goto done;
 579         }
 580
 581         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 582             MLX5_PTYS_EN, 1);
 583         if (error != 0) {
 584                 if_printf(dev, "Query port media capability failed\n");
 585                 goto done;
 586         }
 587
 588         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 589         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
 590
 591         /* query supported capabilities */
 592         eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 593             eth_proto_capability);
 594
 595         /* check for autoselect */
 596         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 597                 link_mode = eth_proto_cap;
 598                 if (link_mode == 0) {
 599                         if_printf(dev, "Port media capability is zero\n");
 600                         error = EINVAL;
 601                         goto done;
 602                 }
 603         } else {
 604                 link_mode = link_mode & eth_proto_cap;
 605                 if (link_mode == 0) {
 606                         if_printf(dev, "Not supported link mode requested\n");
 607                         error = EINVAL;
 608                         goto done;
 609                 }
 610         }
 611         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 612                 /* check if PFC is enabled */
 613                 if (priv->params.rx_priority_flow_control ||
 614                     priv->params.tx_priority_flow_control) {
 615                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 616                         error = EINVAL;
 617                         goto done;
 618                 }
 619         }
 620         /* update pauseframe control bits */
 621         priv->params.rx_pauseframe_control =
 622             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 623         priv->params.tx_pauseframe_control =
 624             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 625
 626         /* check if device is opened */
 627         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 628
 629         /* reconfigure the hardware */
 630         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 631         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
 632         error = -mlx5e_set_port_pause_and_pfc(priv);
 633         if (was_opened)
 634                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 635
 636 done:
 637         if (!locked)
 638                 PRIV_UNLOCK(priv);
 639         return (error);
 640 }
 641
 642 static void
 643 mlx5e_update_carrier_work(struct work_struct *work)
 644 {
 645         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 646             update_carrier_work);
 647
 648         PRIV_LOCK(priv);
 649         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 650                 mlx5e_update_carrier(priv);
 651         PRIV_UNLOCK(priv);
 652 }
 653
 654 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f)    \
 655         s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
 656
 657 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f)    \
 658         s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
 659
 660 static void
 661 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 662 {
 663         struct mlx5_core_dev *mdev = priv->mdev;
 664         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 665         const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 666         void *out;
 667         void *in;
 668         int err;
 669
 670         /* allocate firmware request structures */
 671         in = mlx5_vzalloc(sz);
 672         out = mlx5_vzalloc(sz);
 673         if (in == NULL || out == NULL)
 674                 goto free_out;
 675
 676         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 677         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 678         if (err != 0)
 679                 goto free_out;
 680
 681         MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
 682         MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 683
 684         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
 685         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 686         if (err != 0)
 687                 goto free_out;
 688
 689         MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 690
 691         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
 692         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 693         if (err != 0)
 694                 goto free_out;
 695
 696         MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 697
 698 free_out:
 699         /* free firmware request structures */
 700         kvfree(in);
 701         kvfree(out);
 702 }
 703
 704 /*
 705  * This function reads the physical port counters from the firmware
 706  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 707  * macros. The output is converted from big-endian 64-bit values into
 708  * host endian ones and stored in the "priv->stats.pport" structure.
 709  */
 710 static void
 711 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 712 {
 713         struct mlx5_core_dev *mdev = priv->mdev;
 714         struct mlx5e_pport_stats *s = &priv->stats.pport;
 715         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 716         u32 *in;
 717         u32 *out;
 718         const u64 *ptr;
 719         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 720         unsigned x;
 721         unsigned y;
 722         unsigned z;
 723
 724         /* allocate firmware request structures */
 725         in = mlx5_vzalloc(sz);
 726         out = mlx5_vzalloc(sz);
 727         if (in == NULL || out == NULL)
 728                 goto free_out;
 729
 730         /*
 731          * Get pointer to the 64-bit counter set which is located at a
 732          * fixed offset in the output firmware request structure:
 733          */
 734         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 735
 736         MLX5_SET(ppcnt_reg, in, local_port, 1);
 737
 738         /* read IEEE802_3 counter group using predefined counter layout */
 739         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 740         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 741         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 742              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 743                 s->arg[y] = be64toh(ptr[x]);
 744
 745         /* read RFC2819 counter group using predefined counter layout */
 746         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 747         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 748         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 749                 s->arg[y] = be64toh(ptr[x]);
 750
 751         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 752             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 753                 s_debug->arg[y] = be64toh(ptr[x]);
 754
 755         /* read RFC2863 counter group using predefined counter layout */
 756         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 757         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 758         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 759                 s_debug->arg[y] = be64toh(ptr[x]);
 760
 761         /* read physical layer stats counter group using predefined counter layout */
 762         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 763         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 764         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 765                 s_debug->arg[y] = be64toh(ptr[x]);
 766
 767         /* read Extended Ethernet counter group using predefined counter layout */
 768         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 769         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 770         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 771                 s_debug->arg[y] = be64toh(ptr[x]);
 772
 773         /* read Extended Statistical Group */
 774         if (MLX5_CAP_GEN(mdev, pcam_reg) &&
 775             MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
 776             MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
 777                 /* read Extended Statistical counter group using predefined counter layout */
 778                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 779                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 780
 781                 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
 782                         s_debug->arg[y] = be64toh(ptr[x]);
 783         }
 784
 785         /* read PCIE counters */
 786         mlx5e_update_pcie_counters(priv);
 787
 788         /* read per-priority counters */
 789         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 790
 791         /* iterate all the priorities */
 792         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 793                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 794                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 795
 796                 /* read per priority stats counter group using predefined counter layout */
 797                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 798                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 799                         s->arg[y] = be64toh(ptr[x]);
 800         }
 801
 802 free_out:
 803         /* free firmware request structures */
 804         kvfree(in);
 805         kvfree(out);
 806 }
 807
 808 static void
 809 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
 810 {
 811         u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
 812         u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
 813
 814         if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
 815                 return;
 816
 817         MLX5_SET(query_vnic_env_in, in, opcode,
 818             MLX5_CMD_OP_QUERY_VNIC_ENV);
 819         MLX5_SET(query_vnic_env_in, in, op_mod, 0);
 820         MLX5_SET(query_vnic_env_in, in, other_vport, 0);
 821
 822         if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
 823                 return;
 824
 825         priv->stats.vport.rx_steer_missed_packets =
 826             MLX5_GET64(query_vnic_env_out, out,
 827             vport_env.nic_receive_steering_discard);
 828 }
 829
 830 /*
 831  * This function is called regularly to collect all statistics
 832  * counters from the firmware. The values can be viewed through the
 833  * sysctl interface. Execution is serialized using the priv's global
 834  * configuration lock.
 835  */
 836 static void
 837 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 838 {
 839         struct mlx5_core_dev *mdev = priv->mdev;
 840         struct mlx5e_vport_stats *s = &priv->stats.vport;
 841         struct mlx5e_sq_stats *sq_stats;
 842         struct buf_ring *sq_br;
 843 #if (__FreeBSD_version < 1100000)
 844         struct ifnet *ifp = priv->ifp;
 845 #endif
 846
 847         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 848         u32 *out;
 849         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 850         u64 tso_packets = 0;
 851         u64 tso_bytes = 0;
 852         u64 tx_queue_dropped = 0;
 853         u64 tx_defragged = 0;
 854         u64 tx_offload_none = 0;
 855         u64 lro_packets = 0;
 856         u64 lro_bytes = 0;
 857         u64 sw_lro_queued = 0;
 858         u64 sw_lro_flushed = 0;
 859         u64 rx_csum_none = 0;
 860         u64 rx_wqe_err = 0;
 861         u64 rx_packets = 0;
 862         u64 rx_bytes = 0;
 863         u32 rx_out_of_buffer = 0;
 864         int i;
 865         int j;
 866
 867         out = mlx5_vzalloc(outlen);
 868         if (out == NULL)
 869                 goto free_out;
 870
 871         /* Collect firts the SW counters and then HW for consistency */
 872         for (i = 0; i < priv->params.num_channels; i++) {
 873                 struct mlx5e_channel *pch = priv->channel + i;
 874                 struct mlx5e_rq *rq = &pch->rq;
 875                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 876
 877                 /* collect stats from LRO */
 878                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 879                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 880                 sw_lro_queued += rq_stats->sw_lro_queued;
 881                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 882                 lro_packets += rq_stats->lro_packets;
 883                 lro_bytes += rq_stats->lro_bytes;
 884                 rx_csum_none += rq_stats->csum_none;
 885                 rx_wqe_err += rq_stats->wqe_err;
 886                 rx_packets += rq_stats->packets;
 887                 rx_bytes += rq_stats->bytes;
 888
 889                 for (j = 0; j < priv->num_tc; j++) {
 890                         sq_stats = &pch->sq[j].stats;
 891                         sq_br = pch->sq[j].br;
 892
 893                         tso_packets += sq_stats->tso_packets;
 894                         tso_bytes += sq_stats->tso_bytes;
 895                         tx_queue_dropped += sq_stats->dropped;
 896                         if (sq_br != NULL)
 897                                 tx_queue_dropped += sq_br->br_drops;
 898                         tx_defragged += sq_stats->defragged;
 899                         tx_offload_none += sq_stats->csum_offload_none;
 900                 }
 901         }
 902
 903         /* update counters */
 904         s->tso_packets = tso_packets;
 905         s->tso_bytes = tso_bytes;
 906         s->tx_queue_dropped = tx_queue_dropped;
 907         s->tx_defragged = tx_defragged;
 908         s->lro_packets = lro_packets;
 909         s->lro_bytes = lro_bytes;
 910         s->sw_lro_queued = sw_lro_queued;
 911         s->sw_lro_flushed = sw_lro_flushed;
 912         s->rx_csum_none = rx_csum_none;
 913         s->rx_wqe_err = rx_wqe_err;
 914         s->rx_packets = rx_packets;
 915         s->rx_bytes = rx_bytes;
 916
 917         mlx5e_grp_vnic_env_update_stats(priv);
 918
 919         /* HW counters */
 920         memset(in, 0, sizeof(in));
 921
 922         MLX5_SET(query_vport_counter_in, in, opcode,
 923             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 924         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 925         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 926
 927         memset(out, 0, outlen);
 928
 929         /* get number of out-of-buffer drops first */
 930         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 931             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 932             &rx_out_of_buffer) == 0) {
 933                 s->rx_out_of_buffer = rx_out_of_buffer;
 934         }
 935
 936         /* get port statistics */
 937         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 938 #define MLX5_GET_CTR(out, x) \
 939         MLX5_GET64(query_vport_counter_out, out, x)
 940
 941                 s->rx_error_packets =
 942                     MLX5_GET_CTR(out, received_errors.packets);
 943                 s->rx_error_bytes =
 944                     MLX5_GET_CTR(out, received_errors.octets);
 945                 s->tx_error_packets =
 946                     MLX5_GET_CTR(out, transmit_errors.packets);
 947                 s->tx_error_bytes =
 948                     MLX5_GET_CTR(out, transmit_errors.octets);
 949
 950                 s->rx_unicast_packets =
 951                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 952                 s->rx_unicast_bytes =
 953                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 954                 s->tx_unicast_packets =
 955                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 956                 s->tx_unicast_bytes =
 957                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 958
 959                 s->rx_multicast_packets =
 960                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 961                 s->rx_multicast_bytes =
 962                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 963                 s->tx_multicast_packets =
 964                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 965                 s->tx_multicast_bytes =
 966                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 967
 968                 s->rx_broadcast_packets =
 969                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 970                 s->rx_broadcast_bytes =
 971                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 972                 s->tx_broadcast_packets =
 973                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 974                 s->tx_broadcast_bytes =
 975                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 976
 977                 s->tx_packets = s->tx_unicast_packets +
 978                     s->tx_multicast_packets + s->tx_broadcast_packets;
 979                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 980                     s->tx_broadcast_bytes;
 981
 982                 /* Update calculated offload counters */
 983                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 984                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 985         }
 986
 987         /* Get physical port counters */
 988         mlx5e_update_pport_counters(priv);
 989
 990         s->tx_jumbo_packets =
 991             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 992             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 993             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 994             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 995
 996 #if (__FreeBSD_version < 1100000)
 997         /* no get_counters interface in fbsd 10 */
 998         ifp->if_ipackets = s->rx_packets;
 999         ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
1000             priv->stats.pport.out_of_range_len +
1001             priv->stats.pport.too_long_errors +
1002             priv->stats.pport.check_seq_err +
1003             priv->stats.pport.alignment_err;
1004         ifp->if_iqdrops = s->rx_out_of_buffer;
1005         ifp->if_opackets = s->tx_packets;
1006         ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1007         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1008         ifp->if_ibytes = s->rx_bytes;
1009         ifp->if_obytes = s->tx_bytes;
1010         ifp->if_collisions =
1011             priv->stats.pport.collisions;
1012 #endif
1013
1014 free_out:
1015         kvfree(out);
1016
1017         /* Update diagnostics, if any */
1018         if (priv->params_ethtool.diag_pci_enable ||
1019             priv->params_ethtool.diag_general_enable) {
1020                 int error = mlx5_core_get_diagnostics_full(mdev,
1021                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1022                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1023                 if (error != 0)
1024                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
1025         }
1026 }
1027
1028 static void
1029 mlx5e_update_stats_work(struct work_struct *work)
1030 {
1031         struct mlx5e_priv *priv;
1032
1033         priv  = container_of(work, struct mlx5e_priv, update_stats_work);
1034         PRIV_LOCK(priv);
1035         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
1036                 mlx5e_update_stats_locked(priv);
1037         PRIV_UNLOCK(priv);
1038 }
1039
1040 static void
1041 mlx5e_update_stats(void *arg)
1042 {
1043         struct mlx5e_priv *priv = arg;
1044
1045         queue_work(priv->wq, &priv->update_stats_work);
1046
1047         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
1048 }
1049
1050 static void
1051 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1052     enum mlx5_dev_event event)
1053 {
1054         switch (event) {
1055         case MLX5_DEV_EVENT_PORT_UP:
1056         case MLX5_DEV_EVENT_PORT_DOWN:
1057                 queue_work(priv->wq, &priv->update_carrier_work);
1058                 break;
1059
1060         default:
1061                 break;
1062         }
1063 }
1064
1065 static void
1066 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1067     enum mlx5_dev_event event, unsigned long param)
1068 {
1069         struct mlx5e_priv *priv = vpriv;
1070
1071         mtx_lock(&priv->async_events_mtx);
1072         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1073                 mlx5e_async_event_sub(priv, event);
1074         mtx_unlock(&priv->async_events_mtx);
1075 }
1076
1077 static void
1078 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1079 {
1080         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1081 }
1082
1083 static void
1084 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1085 {
1086         mtx_lock(&priv->async_events_mtx);
1087         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1088         mtx_unlock(&priv->async_events_mtx);
1089 }
1090
1091 static void mlx5e_calibration_callout(void *arg);
1092 static int mlx5e_calibration_duration = 20;
1093 static int mlx5e_fast_calibration = 1;
1094 static int mlx5e_normal_calibration = 30;
1095
1096 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
1097     "MLX5 timestamp calibration parameteres");
1098
1099 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1100     &mlx5e_calibration_duration, 0,
1101     "Duration of initial calibration");
1102 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1103     &mlx5e_fast_calibration, 0,
1104     "Recalibration interval during initial calibration");
1105 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1106     &mlx5e_normal_calibration, 0,
1107     "Recalibration interval during normal operations");
1108
1109 /*
1110  * Ignites the calibration process.
1111  */
1112 static void
1113 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1114 {
1115
1116         if (priv->clbr_done == 0)
1117                 mlx5e_calibration_callout(priv);
1118         else
1119                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1120                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
1121                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
1122                     priv);
1123 }
1124
1125 static uint64_t
1126 mlx5e_timespec2usec(const struct timespec *ts)
1127 {
1128
1129         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1130 }
1131
1132 static uint64_t
1133 mlx5e_hw_clock(struct mlx5e_priv *priv)
1134 {
1135         struct mlx5_init_seg *iseg;
1136         uint32_t hw_h, hw_h1, hw_l;
1137
1138         iseg = priv->mdev->iseg;
1139         do {
1140                 hw_h = ioread32be(&iseg->internal_timer_h);
1141                 hw_l = ioread32be(&iseg->internal_timer_l);
1142                 hw_h1 = ioread32be(&iseg->internal_timer_h);
1143         } while (hw_h1 != hw_h);
1144         return (((uint64_t)hw_h << 32) | hw_l);
1145 }
1146
1147 /*
1148  * The calibration callout, it runs either in the context of the
1149  * thread which enables calibration, or in callout.  It takes the
1150  * snapshot of system and adapter clocks, then advances the pointers to
1151  * the calibration point to allow rx path to read the consistent data
1152  * lockless.
1153  */
1154 static void
1155 mlx5e_calibration_callout(void *arg)
1156 {
1157         struct mlx5e_priv *priv;
1158         struct mlx5e_clbr_point *next, *curr;
1159         struct timespec ts;
1160         int clbr_curr_next;
1161
1162         priv = arg;
1163         curr = &priv->clbr_points[priv->clbr_curr];
1164         clbr_curr_next = priv->clbr_curr + 1;
1165         if (clbr_curr_next >= nitems(priv->clbr_points))
1166                 clbr_curr_next = 0;
1167         next = &priv->clbr_points[clbr_curr_next];
1168
1169         next->base_prev = curr->base_curr;
1170         next->clbr_hw_prev = curr->clbr_hw_curr;
1171
1172         next->clbr_hw_curr = mlx5e_hw_clock(priv);
1173         if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1174             0) {
1175                 if (priv->clbr_done != 0) {
1176                         if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
1177                             "disabling\n",
1178                              next->clbr_hw_curr, curr->clbr_hw_prev);
1179                         priv->clbr_done = 0;
1180                 }
1181                 atomic_store_rel_int(&curr->clbr_gen, 0);
1182                 return;
1183         }
1184
1185         nanouptime(&ts);
1186         next->base_curr = mlx5e_timespec2usec(&ts);
1187
1188         curr->clbr_gen = 0;
1189         atomic_thread_fence_rel();
1190         priv->clbr_curr = clbr_curr_next;
1191         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1192
1193         if (priv->clbr_done < mlx5e_calibration_duration)
1194                 priv->clbr_done++;
1195         mlx5e_reset_calibration_callout(priv);
1196 }
1197
1198 static const char *mlx5e_rq_stats_desc[] = {
1199         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1200 };
1201
1202 static int
1203 mlx5e_create_rq(struct mlx5e_channel *c,
1204     struct mlx5e_rq_param *param,
1205     struct mlx5e_rq *rq)
1206 {
1207         struct mlx5e_priv *priv = c->priv;
1208         struct mlx5_core_dev *mdev = priv->mdev;
1209         char buffer[16];
1210         void *rqc = param->rqc;
1211         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1212         int wq_sz;
1213         int err;
1214         int i;
1215         u32 nsegs, wqe_sz;
1216
1217         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1218         if (err != 0)
1219                 goto done;
1220
1221         /* Create DMA descriptor TAG */
1222         if ((err = -bus_dma_tag_create(
1223             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1224             1,                          /* any alignment */
1225             0,                          /* no boundary */
1226             BUS_SPACE_MAXADDR,          /* lowaddr */
1227             BUS_SPACE_MAXADDR,          /* highaddr */
1228             NULL, NULL,                 /* filter, filterarg */
1229             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1230             nsegs,                      /* nsegments */
1231             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1232             0,                          /* flags */
1233             NULL, NULL,                 /* lockfunc, lockfuncarg */
1234             &rq->dma_tag)))
1235                 goto done;
1236
1237         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1238             &rq->wq_ctrl);
1239         if (err)
1240                 goto err_free_dma_tag;
1241
1242         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1243
1244         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1245         if (err != 0)
1246                 goto err_rq_wq_destroy;
1247
1248         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1249
1250         err = -tcp_lro_init_args(&rq->lro, c->tag.m_snd_tag.ifp, TCP_LRO_ENTRIES, wq_sz);
1251         if (err)
1252                 goto err_rq_wq_destroy;
1253
1254         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1255         for (i = 0; i != wq_sz; i++) {
1256                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1257                 int j;
1258
1259                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1260                 if (err != 0) {
1261                         while (i--)
1262                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1263                         goto err_rq_mbuf_free;
1264                 }
1265
1266                 /* set value for constant fields */
1267                 for (j = 0; j < rq->nsegs; j++)
1268                         wqe->data[j].lkey = c->mkey_be;
1269         }
1270
1271         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1272         if (priv->params.rx_cq_moderation_mode < 2) {
1273                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1274         } else {
1275                 void *cqc = container_of(param,
1276                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
1277
1278                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1279                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1280                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1281                         break;
1282                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1283                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1284                         break;
1285                 default:
1286                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1287                         break;
1288                 }
1289         }
1290
1291         rq->ifp = c->tag.m_snd_tag.ifp;
1292         rq->channel = c;
1293         rq->ix = c->ix;
1294
1295         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1296         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1297             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1298             rq->stats.arg);
1299         return (0);
1300
1301 err_rq_mbuf_free:
1302         free(rq->mbuf, M_MLX5EN);
1303         tcp_lro_free(&rq->lro);
1304 err_rq_wq_destroy:
1305         mlx5_wq_destroy(&rq->wq_ctrl);
1306 err_free_dma_tag:
1307         bus_dma_tag_destroy(rq->dma_tag);
1308 done:
1309         return (err);
1310 }
1311
1312 static void
1313 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1314 {
1315         int wq_sz;
1316         int i;
1317
1318         /* destroy all sysctl nodes */
1319         sysctl_ctx_free(&rq->stats.ctx);
1320
1321         /* free leftover LRO packets, if any */
1322         tcp_lro_free(&rq->lro);
1323
1324         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1325         for (i = 0; i != wq_sz; i++) {
1326                 if (rq->mbuf[i].mbuf != NULL) {
1327                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1328                         m_freem(rq->mbuf[i].mbuf);
1329                 }
1330                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1331         }
1332         free(rq->mbuf, M_MLX5EN);
1333         mlx5_wq_destroy(&rq->wq_ctrl);
1334 }
1335
1336 static int
1337 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1338 {
1339         struct mlx5e_channel *c = rq->channel;
1340         struct mlx5e_priv *priv = c->priv;
1341         struct mlx5_core_dev *mdev = priv->mdev;
1342
1343         void *in;
1344         void *rqc;
1345         void *wq;
1346         int inlen;
1347         int err;
1348
1349         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1350             sizeof(u64) * rq->wq_ctrl.buf.npages;
1351         in = mlx5_vzalloc(inlen);
1352         if (in == NULL)
1353                 return (-ENOMEM);
1354
1355         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1356         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1357
1358         memcpy(rqc, param->rqc, sizeof(param->rqc));
1359
1360         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1361         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1362         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1363         if (priv->counter_set_id >= 0)
1364                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1365         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1366             PAGE_SHIFT);
1367         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1368
1369         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1370             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1371
1372         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1373
1374         kvfree(in);
1375
1376         return (err);
1377 }
1378
1379 static int
1380 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1381 {
1382         struct mlx5e_channel *c = rq->channel;
1383         struct mlx5e_priv *priv = c->priv;
1384         struct mlx5_core_dev *mdev = priv->mdev;
1385
1386         void *in;
1387         void *rqc;
1388         int inlen;
1389         int err;
1390
1391         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1392         in = mlx5_vzalloc(inlen);
1393         if (in == NULL)
1394                 return (-ENOMEM);
1395
1396         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1397
1398         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1399         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1400         MLX5_SET(rqc, rqc, state, next_state);
1401
1402         err = mlx5_core_modify_rq(mdev, in, inlen);
1403
1404         kvfree(in);
1405
1406         return (err);
1407 }
1408
1409 static void
1410 mlx5e_disable_rq(struct mlx5e_rq *rq)
1411 {
1412         struct mlx5e_channel *c = rq->channel;
1413         struct mlx5e_priv *priv = c->priv;
1414         struct mlx5_core_dev *mdev = priv->mdev;
1415
1416         mlx5_core_destroy_rq(mdev, rq->rqn);
1417 }
1418
1419 static int
1420 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1421 {
1422         struct mlx5e_channel *c = rq->channel;
1423         struct mlx5e_priv *priv = c->priv;
1424         struct mlx5_wq_ll *wq = &rq->wq;
1425         int i;
1426
1427         for (i = 0; i < 1000; i++) {
1428                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1429                         return (0);
1430
1431                 msleep(4);
1432         }
1433         return (-ETIMEDOUT);
1434 }
1435
1436 static int
1437 mlx5e_open_rq(struct mlx5e_channel *c,
1438     struct mlx5e_rq_param *param,
1439     struct mlx5e_rq *rq)
1440 {
1441         int err;
1442
1443         err = mlx5e_create_rq(c, param, rq);
1444         if (err)
1445                 return (err);
1446
1447         err = mlx5e_enable_rq(rq, param);
1448         if (err)
1449                 goto err_destroy_rq;
1450
1451         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1452         if (err)
1453                 goto err_disable_rq;
1454
1455         c->rq.enabled = 1;
1456
1457         return (0);
1458
1459 err_disable_rq:
1460         mlx5e_disable_rq(rq);
1461 err_destroy_rq:
1462         mlx5e_destroy_rq(rq);
1463
1464         return (err);
1465 }
1466
1467 static void
1468 mlx5e_close_rq(struct mlx5e_rq *rq)
1469 {
1470         mtx_lock(&rq->mtx);
1471         rq->enabled = 0;
1472         callout_stop(&rq->watchdog);
1473         mtx_unlock(&rq->mtx);
1474
1475         callout_drain(&rq->watchdog);
1476
1477         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1478 }
1479
1480 static void
1481 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1482 {
1483
1484         mlx5e_disable_rq(rq);
1485         mlx5e_close_cq(&rq->cq);
1486         cancel_work_sync(&rq->dim.work);
1487         mlx5e_destroy_rq(rq);
1488 }
1489
1490 void
1491 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1492 {
1493         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1494         int x;
1495
1496         for (x = 0; x != wq_sz; x++) {
1497                 if (sq->mbuf[x].mbuf != NULL) {
1498                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1499                         m_freem(sq->mbuf[x].mbuf);
1500                 }
1501                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1502         }
1503         free(sq->mbuf, M_MLX5EN);
1504 }
1505
1506 int
1507 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1508 {
1509         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1510         int err;
1511         int x;
1512
1513         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1514
1515         /* Create DMA descriptor MAPs */
1516         for (x = 0; x != wq_sz; x++) {
1517                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1518                 if (err != 0) {
1519                         while (x--)
1520                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1521                         free(sq->mbuf, M_MLX5EN);
1522                         return (err);
1523                 }
1524         }
1525         return (0);
1526 }
1527
1528 static const char *mlx5e_sq_stats_desc[] = {
1529         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1530 };
1531
1532 void
1533 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1534 {
1535         sq->max_inline = sq->priv->params.tx_max_inline;
1536         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1537
1538         /*
1539          * Check if trust state is DSCP or if inline mode is NONE which
1540          * indicates CX-5 or newer hardware.
1541          */
1542         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1543             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1544                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1545                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1546                 else
1547                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1548         } else {
1549                 sq->min_insert_caps = 0;
1550         }
1551 }
1552
1553 static void
1554 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1555 {
1556         int i;
1557
1558         for (i = 0; i != c->num_tc; i++) {
1559                 mtx_lock(&c->sq[i].lock);
1560                 mlx5e_update_sq_inline(&c->sq[i]);
1561                 mtx_unlock(&c->sq[i].lock);
1562         }
1563 }
1564
1565 void
1566 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1567 {
1568         int i;
1569
1570         /* check if channels are closed */
1571         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1572                 return;
1573
1574         for (i = 0; i < priv->params.num_channels; i++)
1575                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1576 }
1577
1578 static int
1579 mlx5e_create_sq(struct mlx5e_channel *c,
1580     int tc,
1581     struct mlx5e_sq_param *param,
1582     struct mlx5e_sq *sq)
1583 {
1584         struct mlx5e_priv *priv = c->priv;
1585         struct mlx5_core_dev *mdev = priv->mdev;
1586         char buffer[16];
1587         void *sqc = param->sqc;
1588         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1589         int err;
1590
1591         /* Create DMA descriptor TAG */
1592         if ((err = -bus_dma_tag_create(
1593             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1594             1,                          /* any alignment */
1595             0,                          /* no boundary */
1596             BUS_SPACE_MAXADDR,          /* lowaddr */
1597             BUS_SPACE_MAXADDR,          /* highaddr */
1598             NULL, NULL,                 /* filter, filterarg */
1599             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1600             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1601             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1602             0,                          /* flags */
1603             NULL, NULL,                 /* lockfunc, lockfuncarg */
1604             &sq->dma_tag)))
1605                 goto done;
1606
1607         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1608         if (err)
1609                 goto err_free_dma_tag;
1610
1611         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1612             &sq->wq_ctrl);
1613         if (err)
1614                 goto err_unmap_free_uar;
1615
1616         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1617         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1618
1619         err = mlx5e_alloc_sq_db(sq);
1620         if (err)
1621                 goto err_sq_wq_destroy;
1622
1623         sq->mkey_be = c->mkey_be;
1624         sq->ifp = priv->ifp;
1625         sq->priv = priv;
1626         sq->tc = tc;
1627
1628         mlx5e_update_sq_inline(sq);
1629
1630         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1631         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1632             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1633             sq->stats.arg);
1634
1635         return (0);
1636
1637 err_sq_wq_destroy:
1638         mlx5_wq_destroy(&sq->wq_ctrl);
1639
1640 err_unmap_free_uar:
1641         mlx5_unmap_free_uar(mdev, &sq->uar);
1642
1643 err_free_dma_tag:
1644         bus_dma_tag_destroy(sq->dma_tag);
1645 done:
1646         return (err);
1647 }
1648
1649 static void
1650 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1651 {
1652         /* destroy all sysctl nodes */
1653         sysctl_ctx_free(&sq->stats.ctx);
1654
1655         mlx5e_free_sq_db(sq);
1656         mlx5_wq_destroy(&sq->wq_ctrl);
1657         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1658 }
1659
1660 int
1661 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1662     int tis_num)
1663 {
1664         void *in;
1665         void *sqc;
1666         void *wq;
1667         int inlen;
1668         int err;
1669
1670         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1671             sizeof(u64) * sq->wq_ctrl.buf.npages;
1672         in = mlx5_vzalloc(inlen);
1673         if (in == NULL)
1674                 return (-ENOMEM);
1675
1676         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1677         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1678
1679         memcpy(sqc, param->sqc, sizeof(param->sqc));
1680
1681         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1682         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1683         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1684         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1685         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1686
1687         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1688         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1689         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1690             PAGE_SHIFT);
1691         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1692
1693         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1694             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1695
1696         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1697
1698         kvfree(in);
1699
1700         return (err);
1701 }
1702
1703 int
1704 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1705 {
1706         void *in;
1707         void *sqc;
1708         int inlen;
1709         int err;
1710
1711         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1712         in = mlx5_vzalloc(inlen);
1713         if (in == NULL)
1714                 return (-ENOMEM);
1715
1716         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1717
1718         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1719         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1720         MLX5_SET(sqc, sqc, state, next_state);
1721
1722         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1723
1724         kvfree(in);
1725
1726         return (err);
1727 }
1728
1729 void
1730 mlx5e_disable_sq(struct mlx5e_sq *sq)
1731 {
1732
1733         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1734 }
1735
1736 static int
1737 mlx5e_open_sq(struct mlx5e_channel *c,
1738     int tc,
1739     struct mlx5e_sq_param *param,
1740     struct mlx5e_sq *sq)
1741 {
1742         int err;
1743
1744         err = mlx5e_create_sq(c, tc, param, sq);
1745         if (err)
1746                 return (err);
1747
1748         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1749         if (err)
1750                 goto err_destroy_sq;
1751
1752         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1753         if (err)
1754                 goto err_disable_sq;
1755
1756         WRITE_ONCE(sq->running, 1);
1757
1758         return (0);
1759
1760 err_disable_sq:
1761         mlx5e_disable_sq(sq);
1762 err_destroy_sq:
1763         mlx5e_destroy_sq(sq);
1764
1765         return (err);
1766 }
1767
1768 static void
1769 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1770 {
1771         /* fill up remainder with NOPs */
1772         while (sq->cev_counter != 0) {
1773                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1774                         if (can_sleep != 0) {
1775                                 mtx_unlock(&sq->lock);
1776                                 msleep(4);
1777                                 mtx_lock(&sq->lock);
1778                         } else {
1779                                 goto done;
1780                         }
1781                 }
1782                 /* send a single NOP */
1783                 mlx5e_send_nop(sq, 1);
1784                 atomic_thread_fence_rel();
1785         }
1786 done:
1787         /* Check if we need to write the doorbell */
1788         if (likely(sq->doorbell.d64 != 0)) {
1789                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1790                 sq->doorbell.d64 = 0;
1791         }
1792 }
1793
1794 void
1795 mlx5e_sq_cev_timeout(void *arg)
1796 {
1797         struct mlx5e_sq *sq = arg;
1798
1799         mtx_assert(&sq->lock, MA_OWNED);
1800
1801         /* check next state */
1802         switch (sq->cev_next_state) {
1803         case MLX5E_CEV_STATE_SEND_NOPS:
1804                 /* fill TX ring with NOPs, if any */
1805                 mlx5e_sq_send_nops_locked(sq, 0);
1806
1807                 /* check if completed */
1808                 if (sq->cev_counter == 0) {
1809                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1810                         return;
1811                 }
1812                 break;
1813         default:
1814                 /* send NOPs on next timeout */
1815                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1816                 break;
1817         }
1818
1819         /* restart timer */
1820         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1821 }
1822
1823 void
1824 mlx5e_drain_sq(struct mlx5e_sq *sq)
1825 {
1826         int error;
1827         struct mlx5_core_dev *mdev= sq->priv->mdev;
1828
1829         /*
1830          * Check if already stopped.
1831          *
1832          * NOTE: Serialization of this function is managed by the
1833          * caller ensuring the priv's state lock is locked or in case
1834          * of rate limit support, a single thread manages drain and
1835          * resume of SQs. The "running" variable can therefore safely
1836          * be read without any locks.
1837          */
1838         if (READ_ONCE(sq->running) == 0)
1839                 return;
1840
1841         /* don't put more packets into the SQ */
1842         WRITE_ONCE(sq->running, 0);
1843
1844         /* serialize access to DMA rings */
1845         mtx_lock(&sq->lock);
1846
1847         /* teardown event factor timer, if any */
1848         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1849         callout_stop(&sq->cev_callout);
1850
1851         /* send dummy NOPs in order to flush the transmit ring */
1852         mlx5e_sq_send_nops_locked(sq, 1);
1853         mtx_unlock(&sq->lock);
1854
1855         /* make sure it is safe to free the callout */
1856         callout_drain(&sq->cev_callout);
1857
1858         /* wait till SQ is empty or link is down */
1859         mtx_lock(&sq->lock);
1860         while (sq->cc != sq->pc &&
1861             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1862             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1863                 mtx_unlock(&sq->lock);
1864                 msleep(1);
1865                 sq->cq.mcq.comp(&sq->cq.mcq);
1866                 mtx_lock(&sq->lock);
1867         }
1868         mtx_unlock(&sq->lock);
1869
1870         /* error out remaining requests */
1871         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1872         if (error != 0) {
1873                 if_printf(sq->ifp,
1874                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1875         }
1876
1877         /* wait till SQ is empty */
1878         mtx_lock(&sq->lock);
1879         while (sq->cc != sq->pc &&
1880                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1881                 mtx_unlock(&sq->lock);
1882                 msleep(1);
1883                 sq->cq.mcq.comp(&sq->cq.mcq);
1884                 mtx_lock(&sq->lock);
1885         }
1886         mtx_unlock(&sq->lock);
1887 }
1888
1889 static void
1890 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1891 {
1892
1893         mlx5e_drain_sq(sq);
1894         mlx5e_disable_sq(sq);
1895         mlx5e_destroy_sq(sq);
1896 }
1897
1898 static int
1899 mlx5e_create_cq(struct mlx5e_priv *priv,
1900     struct mlx5e_cq_param *param,
1901     struct mlx5e_cq *cq,
1902     mlx5e_cq_comp_t *comp,
1903     int eq_ix)
1904 {
1905         struct mlx5_core_dev *mdev = priv->mdev;
1906         struct mlx5_core_cq *mcq = &cq->mcq;
1907         int eqn_not_used;
1908         int irqn;
1909         int err;
1910         u32 i;
1911
1912         param->wq.buf_numa_node = 0;
1913         param->wq.db_numa_node = 0;
1914
1915         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1916             &cq->wq_ctrl);
1917         if (err)
1918                 return (err);
1919
1920         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1921
1922         mcq->cqe_sz = 64;
1923         mcq->set_ci_db = cq->wq_ctrl.db.db;
1924         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1925         *mcq->set_ci_db = 0;
1926         *mcq->arm_db = 0;
1927         mcq->vector = eq_ix;
1928         mcq->comp = comp;
1929         mcq->event = mlx5e_cq_error_event;
1930         mcq->irqn = irqn;
1931         mcq->uar = &priv->cq_uar;
1932
1933         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1934                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1935
1936                 cqe->op_own = 0xf1;
1937         }
1938
1939         cq->priv = priv;
1940
1941         return (0);
1942 }
1943
1944 static void
1945 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1946 {
1947         mlx5_wq_destroy(&cq->wq_ctrl);
1948 }
1949
1950 static int
1951 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1952 {
1953         struct mlx5_core_cq *mcq = &cq->mcq;
1954         void *in;
1955         void *cqc;
1956         int inlen;
1957         int irqn_not_used;
1958         int eqn;
1959         int err;
1960
1961         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1962             sizeof(u64) * cq->wq_ctrl.buf.npages;
1963         in = mlx5_vzalloc(inlen);
1964         if (in == NULL)
1965                 return (-ENOMEM);
1966
1967         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1968
1969         memcpy(cqc, param->cqc, sizeof(param->cqc));
1970
1971         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1972             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1973
1974         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1975
1976         MLX5_SET(cqc, cqc, c_eqn, eqn);
1977         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1978         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1979             PAGE_SHIFT);
1980         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1981
1982         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1983
1984         kvfree(in);
1985
1986         if (err)
1987                 return (err);
1988
1989         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1990
1991         return (0);
1992 }
1993
1994 static void
1995 mlx5e_disable_cq(struct mlx5e_cq *cq)
1996 {
1997
1998         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1999 }
2000
2001 int
2002 mlx5e_open_cq(struct mlx5e_priv *priv,
2003     struct mlx5e_cq_param *param,
2004     struct mlx5e_cq *cq,
2005     mlx5e_cq_comp_t *comp,
2006     int eq_ix)
2007 {
2008         int err;
2009
2010         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2011         if (err)
2012                 return (err);
2013
2014         err = mlx5e_enable_cq(cq, param, eq_ix);
2015         if (err)
2016                 goto err_destroy_cq;
2017
2018         return (0);
2019
2020 err_destroy_cq:
2021         mlx5e_destroy_cq(cq);
2022
2023         return (err);
2024 }
2025
2026 void
2027 mlx5e_close_cq(struct mlx5e_cq *cq)
2028 {
2029         mlx5e_disable_cq(cq);
2030         mlx5e_destroy_cq(cq);
2031 }
2032
2033 static int
2034 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2035     struct mlx5e_channel_param *cparam)
2036 {
2037         int err;
2038         int tc;
2039
2040         for (tc = 0; tc < c->num_tc; tc++) {
2041                 /* open completion queue */
2042                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2043                     &mlx5e_tx_cq_comp, c->ix);
2044                 if (err)
2045                         goto err_close_tx_cqs;
2046         }
2047         return (0);
2048
2049 err_close_tx_cqs:
2050         for (tc--; tc >= 0; tc--)
2051                 mlx5e_close_cq(&c->sq[tc].cq);
2052
2053         return (err);
2054 }
2055
2056 static void
2057 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2058 {
2059         int tc;
2060
2061         for (tc = 0; tc < c->num_tc; tc++)
2062                 mlx5e_close_cq(&c->sq[tc].cq);
2063 }
2064
2065 static int
2066 mlx5e_open_sqs(struct mlx5e_channel *c,
2067     struct mlx5e_channel_param *cparam)
2068 {
2069         int err;
2070         int tc;
2071
2072         for (tc = 0; tc < c->num_tc; tc++) {
2073                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2074                 if (err)
2075                         goto err_close_sqs;
2076         }
2077
2078         return (0);
2079
2080 err_close_sqs:
2081         for (tc--; tc >= 0; tc--)
2082                 mlx5e_close_sq_wait(&c->sq[tc]);
2083
2084         return (err);
2085 }
2086
2087 static void
2088 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2089 {
2090         int tc;
2091
2092         for (tc = 0; tc < c->num_tc; tc++)
2093                 mlx5e_close_sq_wait(&c->sq[tc]);
2094 }
2095
2096 static void
2097 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
2098 {
2099         int tc;
2100
2101         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2102
2103         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2104
2105         for (tc = 0; tc < c->num_tc; tc++) {
2106                 struct mlx5e_sq *sq = c->sq + tc;
2107
2108                 mtx_init(&sq->lock, "mlx5tx",
2109                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2110                 mtx_init(&sq->comp_lock, "mlx5comp",
2111                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2112
2113                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2114
2115                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
2116
2117                 /* ensure the TX completion event factor is not zero */
2118                 if (sq->cev_factor == 0)
2119                         sq->cev_factor = 1;
2120         }
2121 }
2122
2123 static void
2124 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
2125 {
2126         int tc;
2127
2128         mtx_destroy(&c->rq.mtx);
2129
2130         for (tc = 0; tc < c->num_tc; tc++) {
2131                 mtx_destroy(&c->sq[tc].lock);
2132                 mtx_destroy(&c->sq[tc].comp_lock);
2133         }
2134 }
2135
2136 static int
2137 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2138     struct mlx5e_channel_param *cparam,
2139     struct mlx5e_channel *c)
2140 {
2141         int err;
2142
2143         memset(c, 0, sizeof(*c));
2144
2145         c->priv = priv;
2146         c->ix = ix;
2147         /* setup send tag */
2148         c->tag.m_snd_tag.ifp = priv->ifp;
2149         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
2150         c->mkey_be = cpu_to_be32(priv->mr.key);
2151         c->num_tc = priv->num_tc;
2152
2153         /* init mutexes */
2154         mlx5e_chan_mtx_init(c);
2155
2156         /* open transmit completion queue */
2157         err = mlx5e_open_tx_cqs(c, cparam);
2158         if (err)
2159                 goto err_free;
2160
2161         /* open receive completion queue */
2162         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2163             &mlx5e_rx_cq_comp, c->ix);
2164         if (err)
2165                 goto err_close_tx_cqs;
2166
2167         err = mlx5e_open_sqs(c, cparam);
2168         if (err)
2169                 goto err_close_rx_cq;
2170
2171         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2172         if (err)
2173                 goto err_close_sqs;
2174
2175         /* poll receive queue initially */
2176         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2177
2178         return (0);
2179
2180 err_close_sqs:
2181         mlx5e_close_sqs_wait(c);
2182
2183 err_close_rx_cq:
2184         mlx5e_close_cq(&c->rq.cq);
2185
2186 err_close_tx_cqs:
2187         mlx5e_close_tx_cqs(c);
2188
2189 err_free:
2190         /* destroy mutexes */
2191         mlx5e_chan_mtx_destroy(c);
2192         return (err);
2193 }
2194
2195 static void
2196 mlx5e_close_channel(struct mlx5e_channel *c)
2197 {
2198         mlx5e_close_rq(&c->rq);
2199 }
2200
2201 static void
2202 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2203 {
2204         mlx5e_close_rq_wait(&c->rq);
2205         mlx5e_close_sqs_wait(c);
2206         mlx5e_close_tx_cqs(c);
2207         /* destroy mutexes */
2208         mlx5e_chan_mtx_destroy(c);
2209 }
2210
2211 static int
2212 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2213 {
2214         u32 r, n;
2215
2216         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2217             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2218         if (r > MJUM16BYTES)
2219                 return (-ENOMEM);
2220
2221         if (r > MJUM9BYTES)
2222                 r = MJUM16BYTES;
2223         else if (r > MJUMPAGESIZE)
2224                 r = MJUM9BYTES;
2225         else if (r > MCLBYTES)
2226                 r = MJUMPAGESIZE;
2227         else
2228                 r = MCLBYTES;
2229
2230         /*
2231          * n + 1 must be a power of two, because stride size must be.
2232          * Stride size is 16 * (n + 1), as the first segment is
2233          * control.
2234          */
2235         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2236                 ;
2237
2238         if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2239                 return (-ENOMEM);
2240
2241         *wqe_sz = r;
2242         *nsegs = n;
2243         return (0);
2244 }
2245
2246 static void
2247 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2248     struct mlx5e_rq_param *param)
2249 {
2250         void *rqc = param->rqc;
2251         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2252         u32 wqe_sz, nsegs;
2253
2254         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2255         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2256         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2257         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2258             nsegs * sizeof(struct mlx5_wqe_data_seg)));
2259         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2260         MLX5_SET(wq, wq, pd, priv->pdn);
2261
2262         param->wq.buf_numa_node = 0;
2263         param->wq.db_numa_node = 0;
2264         param->wq.linear = 1;
2265 }
2266
2267 static void
2268 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2269     struct mlx5e_sq_param *param)
2270 {
2271         void *sqc = param->sqc;
2272         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2273
2274         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2275         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2276         MLX5_SET(wq, wq, pd, priv->pdn);
2277
2278         param->wq.buf_numa_node = 0;
2279         param->wq.db_numa_node = 0;
2280         param->wq.linear = 1;
2281 }
2282
2283 static void
2284 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2285     struct mlx5e_cq_param *param)
2286 {
2287         void *cqc = param->cqc;
2288
2289         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2290 }
2291
2292 static void
2293 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2294 {
2295
2296         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2297
2298         /* apply LRO restrictions */
2299         if (priv->params.hw_lro_en &&
2300             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2301                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2302         }
2303 }
2304
2305 static void
2306 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2307     struct mlx5e_cq_param *param)
2308 {
2309         struct net_dim_cq_moder curr;
2310         void *cqc = param->cqc;
2311
2312         /*
2313          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2314          * format is more beneficial for FreeBSD use case.
2315          *
2316          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2317          * in mlx5e_decompress_cqe.
2318          */
2319         if (priv->params.cqe_zipping_en) {
2320                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2321                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2322         }
2323
2324         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2325
2326         switch (priv->params.rx_cq_moderation_mode) {
2327         case 0:
2328                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2329                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2330                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2331                 break;
2332         case 1:
2333                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2334                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2335                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2336                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2337                 else
2338                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2339                 break;
2340         case 2:
2341                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2342                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2343                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2344                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2345                 break;
2346         case 3:
2347                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2348                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2349                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2350                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2351                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2352                 else
2353                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2354                 break;
2355         default:
2356                 break;
2357         }
2358
2359         mlx5e_dim_build_cq_param(priv, param);
2360
2361         mlx5e_build_common_cq_param(priv, param);
2362 }
2363
2364 static void
2365 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2366     struct mlx5e_cq_param *param)
2367 {
2368         void *cqc = param->cqc;
2369
2370         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2371         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2372         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2373
2374         switch (priv->params.tx_cq_moderation_mode) {
2375         case 0:
2376                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2377                 break;
2378         default:
2379                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2380                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2381                 else
2382                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2383                 break;
2384         }
2385
2386         mlx5e_build_common_cq_param(priv, param);
2387 }
2388
2389 static void
2390 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2391     struct mlx5e_channel_param *cparam)
2392 {
2393         memset(cparam, 0, sizeof(*cparam));
2394
2395         mlx5e_build_rq_param(priv, &cparam->rq);
2396         mlx5e_build_sq_param(priv, &cparam->sq);
2397         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2398         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2399 }
2400
2401 static int
2402 mlx5e_open_channels(struct mlx5e_priv *priv)
2403 {
2404         struct mlx5e_channel_param cparam;
2405         int err;
2406         int i;
2407         int j;
2408
2409         mlx5e_build_channel_param(priv, &cparam);
2410         for (i = 0; i < priv->params.num_channels; i++) {
2411                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
2412                 if (err)
2413                         goto err_close_channels;
2414         }
2415
2416         for (j = 0; j < priv->params.num_channels; j++) {
2417                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2418                 if (err)
2419                         goto err_close_channels;
2420         }
2421         return (0);
2422
2423 err_close_channels:
2424         while (i--) {
2425                 mlx5e_close_channel(&priv->channel[i]);
2426                 mlx5e_close_channel_wait(&priv->channel[i]);
2427         }
2428         return (err);
2429 }
2430
2431 static void
2432 mlx5e_close_channels(struct mlx5e_priv *priv)
2433 {
2434         int i;
2435
2436         for (i = 0; i < priv->params.num_channels; i++)
2437                 mlx5e_close_channel(&priv->channel[i]);
2438         for (i = 0; i < priv->params.num_channels; i++)
2439                 mlx5e_close_channel_wait(&priv->channel[i]);
2440 }
2441
2442 static int
2443 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2444 {
2445
2446         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2447                 uint8_t cq_mode;
2448
2449                 switch (priv->params.tx_cq_moderation_mode) {
2450                 case 0:
2451                 case 2:
2452                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2453                         break;
2454                 default:
2455                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2456                         break;
2457                 }
2458
2459                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2460                     priv->params.tx_cq_moderation_usec,
2461                     priv->params.tx_cq_moderation_pkts,
2462                     cq_mode));
2463         }
2464
2465         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2466             priv->params.tx_cq_moderation_usec,
2467             priv->params.tx_cq_moderation_pkts));
2468 }
2469
2470 static int
2471 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2472 {
2473
2474         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2475                 uint8_t cq_mode;
2476                 uint8_t dim_mode;
2477                 int retval;
2478
2479                 switch (priv->params.rx_cq_moderation_mode) {
2480                 case 0:
2481                 case 2:
2482                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2483                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2484                         break;
2485                 default:
2486                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2487                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2488                         break;
2489                 }
2490
2491                 /* tear down dynamic interrupt moderation */
2492                 mtx_lock(&rq->mtx);
2493                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2494                 mtx_unlock(&rq->mtx);
2495
2496                 /* wait for dynamic interrupt moderation work task, if any */
2497                 cancel_work_sync(&rq->dim.work);
2498
2499                 if (priv->params.rx_cq_moderation_mode >= 2) {
2500                         struct net_dim_cq_moder curr;
2501
2502                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2503
2504                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2505                             curr.usec, curr.pkts, cq_mode);
2506
2507                         /* set dynamic interrupt moderation mode and zero defaults */
2508                         mtx_lock(&rq->mtx);
2509                         rq->dim.mode = dim_mode;
2510                         rq->dim.state = 0;
2511                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2512                         mtx_unlock(&rq->mtx);
2513                 } else {
2514                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2515                             priv->params.rx_cq_moderation_usec,
2516                             priv->params.rx_cq_moderation_pkts,
2517                             cq_mode);
2518                 }
2519                 return (retval);
2520         }
2521
2522         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2523             priv->params.rx_cq_moderation_usec,
2524             priv->params.rx_cq_moderation_pkts));
2525 }
2526
2527 static int
2528 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2529 {
2530         int err;
2531         int i;
2532
2533         err = mlx5e_refresh_rq_params(priv, &c->rq);
2534         if (err)
2535                 goto done;
2536
2537         for (i = 0; i != c->num_tc; i++) {
2538                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2539                 if (err)
2540                         goto done;
2541         }
2542 done:
2543         return (err);
2544 }
2545
2546 int
2547 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2548 {
2549         int i;
2550
2551         /* check if channels are closed */
2552         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2553                 return (EINVAL);
2554
2555         for (i = 0; i < priv->params.num_channels; i++) {
2556                 int err;
2557
2558                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2559                 if (err)
2560                         return (err);
2561         }
2562         return (0);
2563 }
2564
2565 static int
2566 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2567 {
2568         struct mlx5_core_dev *mdev = priv->mdev;
2569         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2570         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2571
2572         memset(in, 0, sizeof(in));
2573
2574         MLX5_SET(tisc, tisc, prio, tc);
2575         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2576
2577         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2578 }
2579
2580 static void
2581 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2582 {
2583         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2584 }
2585
2586 static int
2587 mlx5e_open_tises(struct mlx5e_priv *priv)
2588 {
2589         int num_tc = priv->num_tc;
2590         int err;
2591         int tc;
2592
2593         for (tc = 0; tc < num_tc; tc++) {
2594                 err = mlx5e_open_tis(priv, tc);
2595                 if (err)
2596                         goto err_close_tises;
2597         }
2598
2599         return (0);
2600
2601 err_close_tises:
2602         for (tc--; tc >= 0; tc--)
2603                 mlx5e_close_tis(priv, tc);
2604
2605         return (err);
2606 }
2607
2608 static void
2609 mlx5e_close_tises(struct mlx5e_priv *priv)
2610 {
2611         int num_tc = priv->num_tc;
2612         int tc;
2613
2614         for (tc = 0; tc < num_tc; tc++)
2615                 mlx5e_close_tis(priv, tc);
2616 }
2617
2618 static int
2619 mlx5e_open_rqt(struct mlx5e_priv *priv)
2620 {
2621         struct mlx5_core_dev *mdev = priv->mdev;
2622         u32 *in;
2623         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2624         void *rqtc;
2625         int inlen;
2626         int err;
2627         int sz;
2628         int i;
2629
2630         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2631
2632         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2633         in = mlx5_vzalloc(inlen);
2634         if (in == NULL)
2635                 return (-ENOMEM);
2636         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2637
2638         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2639         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2640
2641         for (i = 0; i < sz; i++) {
2642                 int ix = i;
2643 #ifdef RSS
2644                 ix = rss_get_indirection_to_bucket(ix);
2645 #endif
2646                 /* ensure we don't overflow */
2647                 ix %= priv->params.num_channels;
2648
2649                 /* apply receive side scaling stride, if any */
2650                 ix -= ix % (int)priv->params.channels_rsss;
2651
2652                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2653         }
2654
2655         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2656
2657         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2658         if (!err)
2659                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2660
2661         kvfree(in);
2662
2663         return (err);
2664 }
2665
2666 static void
2667 mlx5e_close_rqt(struct mlx5e_priv *priv)
2668 {
2669         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2670         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2671
2672         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2673         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2674
2675         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2676 }
2677
2678 static void
2679 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2680 {
2681         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2682         __be32 *hkey;
2683
2684         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2685
2686 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2687
2688 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2689                           MLX5_HASH_FIELD_SEL_DST_IP)
2690
2691 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2692                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2693                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2694                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2695
2696 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2697                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2698                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2699
2700         if (priv->params.hw_lro_en) {
2701                 MLX5_SET(tirc, tirc, lro_enable_mask,
2702                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2703                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2704                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2705                     (priv->params.lro_wqe_sz -
2706                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2707                 /* TODO: add the option to choose timer value dynamically */
2708                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2709                     MLX5_CAP_ETH(priv->mdev,
2710                     lro_timer_supported_periods[2]));
2711         }
2712
2713         /* setup parameters for hashing TIR type, if any */
2714         switch (tt) {
2715         case MLX5E_TT_ANY:
2716                 MLX5_SET(tirc, tirc, disp_type,
2717                     MLX5_TIRC_DISP_TYPE_DIRECT);
2718                 MLX5_SET(tirc, tirc, inline_rqn,
2719                     priv->channel[0].rq.rqn);
2720                 break;
2721         default:
2722                 MLX5_SET(tirc, tirc, disp_type,
2723                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2724                 MLX5_SET(tirc, tirc, indirect_table,
2725                     priv->rqtn);
2726                 MLX5_SET(tirc, tirc, rx_hash_fn,
2727                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2728                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2729 #ifdef RSS
2730                 /*
2731                  * The FreeBSD RSS implementation does currently not
2732                  * support symmetric Toeplitz hashes:
2733                  */
2734                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2735                 rss_getkey((uint8_t *)hkey);
2736 #else
2737                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2738                 hkey[0] = cpu_to_be32(0xD181C62C);
2739                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2740                 hkey[2] = cpu_to_be32(0x1983A2FC);
2741                 hkey[3] = cpu_to_be32(0x943E1ADB);
2742                 hkey[4] = cpu_to_be32(0xD9389E6B);
2743                 hkey[5] = cpu_to_be32(0xD1039C2C);
2744                 hkey[6] = cpu_to_be32(0xA74499AD);
2745                 hkey[7] = cpu_to_be32(0x593D56D9);
2746                 hkey[8] = cpu_to_be32(0xF3253C06);
2747                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2748 #endif
2749                 break;
2750         }
2751
2752         switch (tt) {
2753         case MLX5E_TT_IPV4_TCP:
2754                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2755                     MLX5_L3_PROT_TYPE_IPV4);
2756                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2757                     MLX5_L4_PROT_TYPE_TCP);
2758 #ifdef RSS
2759                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2760                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2761                             MLX5_HASH_IP);
2762                 } else
2763 #endif
2764                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2765                     MLX5_HASH_ALL);
2766                 break;
2767
2768         case MLX5E_TT_IPV6_TCP:
2769                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2770                     MLX5_L3_PROT_TYPE_IPV6);
2771                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2772                     MLX5_L4_PROT_TYPE_TCP);
2773 #ifdef RSS
2774                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2775                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2776                             MLX5_HASH_IP);
2777                 } else
2778 #endif
2779                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2780                     MLX5_HASH_ALL);
2781                 break;
2782
2783         case MLX5E_TT_IPV4_UDP:
2784                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2785                     MLX5_L3_PROT_TYPE_IPV4);
2786                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2787                     MLX5_L4_PROT_TYPE_UDP);
2788 #ifdef RSS
2789                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2790                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2791                             MLX5_HASH_IP);
2792                 } else
2793 #endif
2794                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2795                     MLX5_HASH_ALL);
2796                 break;
2797
2798         case MLX5E_TT_IPV6_UDP:
2799                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2800                     MLX5_L3_PROT_TYPE_IPV6);
2801                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2802                     MLX5_L4_PROT_TYPE_UDP);
2803 #ifdef RSS
2804                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2805                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2806                             MLX5_HASH_IP);
2807                 } else
2808 #endif
2809                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2810                     MLX5_HASH_ALL);
2811                 break;
2812
2813         case MLX5E_TT_IPV4_IPSEC_AH:
2814                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2815                     MLX5_L3_PROT_TYPE_IPV4);
2816                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2817                     MLX5_HASH_IP_IPSEC_SPI);
2818                 break;
2819
2820         case MLX5E_TT_IPV6_IPSEC_AH:
2821                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2822                     MLX5_L3_PROT_TYPE_IPV6);
2823                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2824                     MLX5_HASH_IP_IPSEC_SPI);
2825                 break;
2826
2827         case MLX5E_TT_IPV4_IPSEC_ESP:
2828                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2829                     MLX5_L3_PROT_TYPE_IPV4);
2830                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2831                     MLX5_HASH_IP_IPSEC_SPI);
2832                 break;
2833
2834         case MLX5E_TT_IPV6_IPSEC_ESP:
2835                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2836                     MLX5_L3_PROT_TYPE_IPV6);
2837                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2838                     MLX5_HASH_IP_IPSEC_SPI);
2839                 break;
2840
2841         case MLX5E_TT_IPV4:
2842                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2843                     MLX5_L3_PROT_TYPE_IPV4);
2844                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2845                     MLX5_HASH_IP);
2846                 break;
2847
2848         case MLX5E_TT_IPV6:
2849                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2850                     MLX5_L3_PROT_TYPE_IPV6);
2851                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2852                     MLX5_HASH_IP);
2853                 break;
2854
2855         default:
2856                 break;
2857         }
2858 }
2859
2860 static int
2861 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2862 {
2863         struct mlx5_core_dev *mdev = priv->mdev;
2864         u32 *in;
2865         void *tirc;
2866         int inlen;
2867         int err;
2868
2869         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2870         in = mlx5_vzalloc(inlen);
2871         if (in == NULL)
2872                 return (-ENOMEM);
2873         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2874
2875         mlx5e_build_tir_ctx(priv, tirc, tt);
2876
2877         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2878
2879         kvfree(in);
2880
2881         return (err);
2882 }
2883
2884 static void
2885 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2886 {
2887         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2888 }
2889
2890 static int
2891 mlx5e_open_tirs(struct mlx5e_priv *priv)
2892 {
2893         int err;
2894         int i;
2895
2896         for (i = 0; i < MLX5E_NUM_TT; i++) {
2897                 err = mlx5e_open_tir(priv, i);
2898                 if (err)
2899                         goto err_close_tirs;
2900         }
2901
2902         return (0);
2903
2904 err_close_tirs:
2905         for (i--; i >= 0; i--)
2906                 mlx5e_close_tir(priv, i);
2907
2908         return (err);
2909 }
2910
2911 static void
2912 mlx5e_close_tirs(struct mlx5e_priv *priv)
2913 {
2914         int i;
2915
2916         for (i = 0; i < MLX5E_NUM_TT; i++)
2917                 mlx5e_close_tir(priv, i);
2918 }
2919
2920 /*
2921  * SW MTU does not include headers,
2922  * HW MTU includes all headers and checksums.
2923  */
2924 static int
2925 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2926 {
2927         struct mlx5e_priv *priv = ifp->if_softc;
2928         struct mlx5_core_dev *mdev = priv->mdev;
2929         int hw_mtu;
2930         int err;
2931
2932         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2933
2934         err = mlx5_set_port_mtu(mdev, hw_mtu);
2935         if (err) {
2936                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2937                     __func__, sw_mtu, err);
2938                 return (err);
2939         }
2940
2941         /* Update vport context MTU */
2942         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2943         if (err) {
2944                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2945                     __func__, err);
2946         }
2947
2948         ifp->if_mtu = sw_mtu;
2949
2950         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2951         if (err || !hw_mtu) {
2952                 /* fallback to port oper mtu */
2953                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2954         }
2955         if (err) {
2956                 if_printf(ifp, "Query port MTU, after setting new "
2957                     "MTU value, failed\n");
2958                 return (err);
2959         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2960                 err = -E2BIG,
2961                 if_printf(ifp, "Port MTU %d is smaller than "
2962                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2963         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2964                 err = -EINVAL;
2965                 if_printf(ifp, "Port MTU %d is bigger than "
2966                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2967         }
2968         priv->params_ethtool.hw_mtu = hw_mtu;
2969
2970         return (err);
2971 }
2972
2973 int
2974 mlx5e_open_locked(struct ifnet *ifp)
2975 {
2976         struct mlx5e_priv *priv = ifp->if_softc;
2977         int err;
2978         u16 set_id;
2979
2980         /* check if already opened */
2981         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2982                 return (0);
2983
2984 #ifdef RSS
2985         if (rss_getnumbuckets() > priv->params.num_channels) {
2986                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2987                     "channels(%u) available\n", rss_getnumbuckets(),
2988                     priv->params.num_channels);
2989         }
2990 #endif
2991         err = mlx5e_open_tises(priv);
2992         if (err) {
2993                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2994                     __func__, err);
2995                 return (err);
2996         }
2997         err = mlx5_vport_alloc_q_counter(priv->mdev,
2998             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2999         if (err) {
3000                 if_printf(priv->ifp,
3001                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
3002                     __func__, err);
3003                 goto err_close_tises;
3004         }
3005         /* store counter set ID */
3006         priv->counter_set_id = set_id;
3007
3008         err = mlx5e_open_channels(priv);
3009         if (err) {
3010                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
3011                     __func__, err);
3012                 goto err_dalloc_q_counter;
3013         }
3014         err = mlx5e_open_rqt(priv);
3015         if (err) {
3016                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
3017                     __func__, err);
3018                 goto err_close_channels;
3019         }
3020         err = mlx5e_open_tirs(priv);
3021         if (err) {
3022                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
3023                     __func__, err);
3024                 goto err_close_rqls;
3025         }
3026         err = mlx5e_open_flow_table(priv);
3027         if (err) {
3028                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
3029                     __func__, err);
3030                 goto err_close_tirs;
3031         }
3032         err = mlx5e_add_all_vlan_rules(priv);
3033         if (err) {
3034                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
3035                     __func__, err);
3036                 goto err_close_flow_table;
3037         }
3038         set_bit(MLX5E_STATE_OPENED, &priv->state);
3039
3040         mlx5e_update_carrier(priv);
3041         mlx5e_set_rx_mode_core(priv);
3042
3043         return (0);
3044
3045 err_close_flow_table:
3046         mlx5e_close_flow_table(priv);
3047
3048 err_close_tirs:
3049         mlx5e_close_tirs(priv);
3050
3051 err_close_rqls:
3052         mlx5e_close_rqt(priv);
3053
3054 err_close_channels:
3055         mlx5e_close_channels(priv);
3056
3057 err_dalloc_q_counter:
3058         mlx5_vport_dealloc_q_counter(priv->mdev,
3059             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3060
3061 err_close_tises:
3062         mlx5e_close_tises(priv);
3063
3064         return (err);
3065 }
3066
3067 static void
3068 mlx5e_open(void *arg)
3069 {
3070         struct mlx5e_priv *priv = arg;
3071
3072         PRIV_LOCK(priv);
3073         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3074                 if_printf(priv->ifp,
3075                     "%s: Setting port status to up failed\n",
3076                     __func__);
3077
3078         mlx5e_open_locked(priv->ifp);
3079         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3080         PRIV_UNLOCK(priv);
3081 }
3082
3083 int
3084 mlx5e_close_locked(struct ifnet *ifp)
3085 {
3086         struct mlx5e_priv *priv = ifp->if_softc;
3087
3088         /* check if already closed */
3089         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3090                 return (0);
3091
3092         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3093
3094         mlx5e_set_rx_mode_core(priv);
3095         mlx5e_del_all_vlan_rules(priv);
3096         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3097         mlx5e_close_flow_table(priv);
3098         mlx5e_close_tirs(priv);
3099         mlx5e_close_rqt(priv);
3100         mlx5e_close_channels(priv);
3101         mlx5_vport_dealloc_q_counter(priv->mdev,
3102             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3103         mlx5e_close_tises(priv);
3104
3105         return (0);
3106 }
3107
3108 #if (__FreeBSD_version >= 1100000)
3109 static uint64_t
3110 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3111 {
3112         struct mlx5e_priv *priv = ifp->if_softc;
3113         u64 retval;
3114
3115         /* PRIV_LOCK(priv); XXX not allowed */
3116         switch (cnt) {
3117         case IFCOUNTER_IPACKETS:
3118                 retval = priv->stats.vport.rx_packets;
3119                 break;
3120         case IFCOUNTER_IERRORS:
3121                 retval = priv->stats.pport.in_range_len_errors +
3122                     priv->stats.pport.out_of_range_len +
3123                     priv->stats.pport.too_long_errors +
3124                     priv->stats.pport.check_seq_err +
3125                     priv->stats.pport.alignment_err;
3126                 break;
3127         case IFCOUNTER_IQDROPS:
3128                 retval = priv->stats.vport.rx_out_of_buffer;
3129                 break;
3130         case IFCOUNTER_OPACKETS:
3131                 retval = priv->stats.vport.tx_packets;
3132                 break;
3133         case IFCOUNTER_OERRORS:
3134                 retval = priv->stats.port_stats_debug.out_discards;
3135                 break;
3136         case IFCOUNTER_IBYTES:
3137                 retval = priv->stats.vport.rx_bytes;
3138                 break;
3139         case IFCOUNTER_OBYTES:
3140                 retval = priv->stats.vport.tx_bytes;
3141                 break;
3142         case IFCOUNTER_IMCASTS:
3143                 retval = priv->stats.vport.rx_multicast_packets;
3144                 break;
3145         case IFCOUNTER_OMCASTS:
3146                 retval = priv->stats.vport.tx_multicast_packets;
3147                 break;
3148         case IFCOUNTER_OQDROPS:
3149                 retval = priv->stats.vport.tx_queue_dropped;
3150                 break;
3151         case IFCOUNTER_COLLISIONS:
3152                 retval = priv->stats.pport.collisions;
3153                 break;
3154         default:
3155                 retval = if_get_counter_default(ifp, cnt);
3156                 break;
3157         }
3158         /* PRIV_UNLOCK(priv); XXX not allowed */
3159         return (retval);
3160 }
3161 #endif
3162
3163 static void
3164 mlx5e_set_rx_mode(struct ifnet *ifp)
3165 {
3166         struct mlx5e_priv *priv = ifp->if_softc;
3167
3168         queue_work(priv->wq, &priv->set_rx_mode_work);
3169 }
3170
3171 static int
3172 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3173 {
3174         struct mlx5e_priv *priv;
3175         struct ifreq *ifr;
3176         struct ifi2creq i2c;
3177         int error = 0;
3178         int mask = 0;
3179         int size_read = 0;
3180         int module_status;
3181         int module_num;
3182         int max_mtu;
3183         uint8_t read_addr;
3184
3185         priv = ifp->if_softc;
3186
3187         /* check if detaching */
3188         if (priv == NULL || priv->gone != 0)
3189                 return (ENXIO);
3190
3191         switch (command) {
3192         case SIOCSIFMTU:
3193                 ifr = (struct ifreq *)data;
3194
3195                 PRIV_LOCK(priv);
3196                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3197
3198                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3199                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3200                         int was_opened;
3201
3202                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3203                         if (was_opened)
3204                                 mlx5e_close_locked(ifp);
3205
3206                         /* set new MTU */
3207                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3208
3209                         if (was_opened)
3210                                 mlx5e_open_locked(ifp);
3211                 } else {
3212                         error = EINVAL;
3213                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
3214                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3215                 }
3216                 PRIV_UNLOCK(priv);
3217                 break;
3218         case SIOCSIFFLAGS:
3219                 if ((ifp->if_flags & IFF_UP) &&
3220                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3221                         mlx5e_set_rx_mode(ifp);
3222                         break;
3223                 }
3224                 PRIV_LOCK(priv);
3225                 if (ifp->if_flags & IFF_UP) {
3226                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3227                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3228                                         mlx5e_open_locked(ifp);
3229                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3230                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3231                         }
3232                 } else {
3233                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3234                                 mlx5_set_port_status(priv->mdev,
3235                                     MLX5_PORT_DOWN);
3236                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3237                                         mlx5e_close_locked(ifp);
3238                                 mlx5e_update_carrier(priv);
3239                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3240                         }
3241                 }
3242                 PRIV_UNLOCK(priv);
3243                 break;
3244         case SIOCADDMULTI:
3245         case SIOCDELMULTI:
3246                 mlx5e_set_rx_mode(ifp);
3247                 break;
3248         case SIOCSIFMEDIA:
3249         case SIOCGIFMEDIA:
3250         case SIOCGIFXMEDIA:
3251                 ifr = (struct ifreq *)data;
3252                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3253                 break;
3254         case SIOCSIFCAP:
3255                 ifr = (struct ifreq *)data;
3256                 PRIV_LOCK(priv);
3257                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3258
3259                 if (mask & IFCAP_TXCSUM) {
3260                         ifp->if_capenable ^= IFCAP_TXCSUM;
3261                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3262
3263                         if (IFCAP_TSO4 & ifp->if_capenable &&
3264                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3265                                 ifp->if_capenable &= ~IFCAP_TSO4;
3266                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
3267                                 if_printf(ifp,
3268                                     "tso4 disabled due to -txcsum.\n");
3269                         }
3270                 }
3271                 if (mask & IFCAP_TXCSUM_IPV6) {
3272                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3273                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3274
3275                         if (IFCAP_TSO6 & ifp->if_capenable &&
3276                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3277                                 ifp->if_capenable &= ~IFCAP_TSO6;
3278                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3279                                 if_printf(ifp,
3280                                     "tso6 disabled due to -txcsum6.\n");
3281                         }
3282                 }
3283                 if (mask & IFCAP_RXCSUM)
3284                         ifp->if_capenable ^= IFCAP_RXCSUM;
3285                 if (mask & IFCAP_RXCSUM_IPV6)
3286                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3287                 if (mask & IFCAP_TSO4) {
3288                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3289                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3290                                 if_printf(ifp, "enable txcsum first.\n");
3291                                 error = EAGAIN;
3292                                 goto out;
3293                         }
3294                         ifp->if_capenable ^= IFCAP_TSO4;
3295                         ifp->if_hwassist ^= CSUM_IP_TSO;
3296                 }
3297                 if (mask & IFCAP_TSO6) {
3298                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3299                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3300                                 if_printf(ifp, "enable txcsum6 first.\n");
3301                                 error = EAGAIN;
3302                                 goto out;
3303                         }
3304                         ifp->if_capenable ^= IFCAP_TSO6;
3305                         ifp->if_hwassist ^= CSUM_IP6_TSO;
3306                 }
3307                 if (mask & IFCAP_VLAN_HWFILTER) {
3308                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3309                                 mlx5e_disable_vlan_filter(priv);
3310                         else
3311                                 mlx5e_enable_vlan_filter(priv);
3312
3313                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3314                 }
3315                 if (mask & IFCAP_VLAN_HWTAGGING)
3316                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3317                 if (mask & IFCAP_WOL_MAGIC)
3318                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3319
3320                 VLAN_CAPABILITIES(ifp);
3321                 /* turn off LRO means also turn of HW LRO - if it's on */
3322                 if (mask & IFCAP_LRO) {
3323                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3324                         bool need_restart = false;
3325
3326                         ifp->if_capenable ^= IFCAP_LRO;
3327
3328                         /* figure out if updating HW LRO is needed */
3329                         if (!(ifp->if_capenable & IFCAP_LRO)) {
3330                                 if (priv->params.hw_lro_en) {
3331                                         priv->params.hw_lro_en = false;
3332                                         need_restart = true;
3333                                 }
3334                         } else {
3335                                 if (priv->params.hw_lro_en == false &&
3336                                     priv->params_ethtool.hw_lro != 0) {
3337                                         priv->params.hw_lro_en = true;
3338                                         need_restart = true;
3339                                 }
3340                         }
3341                         if (was_opened && need_restart) {
3342                                 mlx5e_close_locked(ifp);
3343                                 mlx5e_open_locked(ifp);
3344                         }
3345                 }
3346                 if (mask & IFCAP_HWRXTSTMP) {
3347                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3348                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3349                                 if (priv->clbr_done == 0)
3350                                         mlx5e_reset_calibration_callout(priv);
3351                         } else {
3352                                 callout_drain(&priv->tstmp_clbr);
3353                                 priv->clbr_done = 0;
3354                         }
3355                 }
3356 out:
3357                 PRIV_UNLOCK(priv);
3358                 break;
3359
3360         case SIOCGI2C:
3361                 ifr = (struct ifreq *)data;
3362
3363                 /*
3364                  * Copy from the user-space address ifr_data to the
3365                  * kernel-space address i2c
3366                  */
3367                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3368                 if (error)
3369                         break;
3370
3371                 if (i2c.len > sizeof(i2c.data)) {
3372                         error = EINVAL;
3373                         break;
3374                 }
3375
3376                 PRIV_LOCK(priv);
3377                 /* Get module_num which is required for the query_eeprom */
3378                 error = mlx5_query_module_num(priv->mdev, &module_num);
3379                 if (error) {
3380                         if_printf(ifp, "Query module num failed, eeprom "
3381                             "reading is not supported\n");
3382                         error = EINVAL;
3383                         goto err_i2c;
3384                 }
3385                 /* Check if module is present before doing an access */
3386                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3387                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
3388                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
3389                         error = EINVAL;
3390                         goto err_i2c;
3391                 }
3392                 /*
3393                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3394                  * The internal conversion is as follows:
3395                  */
3396                 if (i2c.dev_addr == 0xA0)
3397                         read_addr = MLX5E_I2C_ADDR_LOW;
3398                 else if (i2c.dev_addr == 0xA2)
3399                         read_addr = MLX5E_I2C_ADDR_HIGH;
3400                 else {
3401                         if_printf(ifp, "Query eeprom failed, "
3402                             "Invalid Address: %X\n", i2c.dev_addr);
3403                         error = EINVAL;
3404                         goto err_i2c;
3405                 }
3406                 error = mlx5_query_eeprom(priv->mdev,
3407                     read_addr, MLX5E_EEPROM_LOW_PAGE,
3408                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3409                     (uint32_t *)i2c.data, &size_read);
3410                 if (error) {
3411                         if_printf(ifp, "Query eeprom failed, eeprom "
3412                             "reading is not supported\n");
3413                         error = EINVAL;
3414                         goto err_i2c;
3415                 }
3416
3417                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3418                         error = mlx5_query_eeprom(priv->mdev,
3419                             read_addr, MLX5E_EEPROM_LOW_PAGE,
3420                             (uint32_t)(i2c.offset + size_read),
3421                             (uint32_t)(i2c.len - size_read), module_num,
3422                             (uint32_t *)(i2c.data + size_read), &size_read);
3423                 }
3424                 if (error) {
3425                         if_printf(ifp, "Query eeprom failed, eeprom "
3426                             "reading is not supported\n");
3427                         error = EINVAL;
3428                         goto err_i2c;
3429                 }
3430
3431                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3432 err_i2c:
3433                 PRIV_UNLOCK(priv);
3434                 break;
3435
3436         default:
3437                 error = ether_ioctl(ifp, command, data);
3438                 break;
3439         }
3440         return (error);
3441 }
3442
3443 static int
3444 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3445 {
3446         /*
3447          * TODO: uncoment once FW really sets all these bits if
3448          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3449          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3450          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3451          * -ENOTSUPP;
3452          */
3453
3454         /* TODO: add more must-to-have features */
3455
3456         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3457                 return (-ENODEV);
3458
3459         return (0);
3460 }
3461
3462 static u16
3463 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3464 {
3465         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3466
3467         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3468
3469         /* verify against driver hardware limit */
3470         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3471                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3472
3473         return (bf_buf_size);
3474 }
3475
3476 static int
3477 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3478     struct mlx5e_priv *priv,
3479     int num_comp_vectors)
3480 {
3481         int err;
3482
3483         /*
3484          * TODO: Consider link speed for setting "log_sq_size",
3485          * "log_rq_size" and "cq_moderation_xxx":
3486          */
3487         priv->params.log_sq_size =
3488             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3489         priv->params.log_rq_size =
3490             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3491         priv->params.rx_cq_moderation_usec =
3492             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3493             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3494             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3495         priv->params.rx_cq_moderation_mode =
3496             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3497         priv->params.rx_cq_moderation_pkts =
3498             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3499         priv->params.tx_cq_moderation_usec =
3500             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3501         priv->params.tx_cq_moderation_pkts =
3502             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3503         priv->params.min_rx_wqes =
3504             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3505         priv->params.rx_hash_log_tbl_sz =
3506             (order_base_2(num_comp_vectors) >
3507             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3508             order_base_2(num_comp_vectors) :
3509             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3510         priv->params.num_tc = 1;
3511         priv->params.default_vlan_prio = 0;
3512         priv->counter_set_id = -1;
3513         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3514
3515         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3516         if (err)
3517                 return (err);
3518
3519         /*
3520          * hw lro is currently defaulted to off. when it won't anymore we
3521          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3522          */
3523         priv->params.hw_lro_en = false;
3524         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3525
3526         /*
3527          * CQE zipping is currently defaulted to off. when it won't
3528          * anymore we will consider the HW capability:
3529          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3530          */
3531         priv->params.cqe_zipping_en = false;
3532
3533         priv->mdev = mdev;
3534         priv->params.num_channels = num_comp_vectors;
3535         priv->params.channels_rsss = 1;
3536         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3537         priv->queue_mapping_channel_mask =
3538             roundup_pow_of_two(num_comp_vectors) - 1;
3539         priv->num_tc = priv->params.num_tc;
3540         priv->default_vlan_prio = priv->params.default_vlan_prio;
3541
3542         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3543         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3544         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3545
3546         return (0);
3547 }
3548
3549 static int
3550 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3551                   struct mlx5_core_mr *mkey)
3552 {
3553         struct ifnet *ifp = priv->ifp;
3554         struct mlx5_core_dev *mdev = priv->mdev;
3555         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3556         void *mkc;
3557         u32 *in;
3558         int err;
3559
3560         in = mlx5_vzalloc(inlen);
3561         if (in == NULL) {
3562                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3563                 return (-ENOMEM);
3564         }
3565
3566         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3567         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3568         MLX5_SET(mkc, mkc, lw, 1);
3569         MLX5_SET(mkc, mkc, lr, 1);
3570
3571         MLX5_SET(mkc, mkc, pd, pdn);
3572         MLX5_SET(mkc, mkc, length64, 1);
3573         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3574
3575         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3576         if (err)
3577                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3578                     __func__, err);
3579
3580         kvfree(in);
3581         return (err);
3582 }
3583
3584 static const char *mlx5e_vport_stats_desc[] = {
3585         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3586 };
3587
3588 static const char *mlx5e_pport_stats_desc[] = {
3589         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3590 };
3591
3592 static void
3593 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3594 {
3595         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3596         sx_init(&priv->state_lock, "mlx5state");
3597         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3598         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3599 }
3600
3601 static void
3602 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3603 {
3604         mtx_destroy(&priv->async_events_mtx);
3605         sx_destroy(&priv->state_lock);
3606 }
3607
3608 static int
3609 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3610 {
3611         /*
3612          * %d.%d%.d the string format.
3613          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3614          * We need at most 5 chars to store that.
3615          * It also has: two "." and NULL at the end, which means we need 18
3616          * (5*3 + 3) chars at most.
3617          */
3618         char fw[18];
3619         struct mlx5e_priv *priv = arg1;
3620         int error;
3621
3622         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3623             fw_rev_sub(priv->mdev));
3624         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3625         return (error);
3626 }
3627
3628 static void
3629 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3630 {
3631         int i;
3632
3633         for (i = 0; i < ch->num_tc; i++)
3634                 mlx5e_drain_sq(&ch->sq[i]);
3635 }
3636
3637 static void
3638 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3639 {
3640
3641         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3642         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3643         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3644         sq->doorbell.d64 = 0;
3645 }
3646
3647 void
3648 mlx5e_resume_sq(struct mlx5e_sq *sq)
3649 {
3650         int err;
3651
3652         /* check if already enabled */
3653         if (READ_ONCE(sq->running) != 0)
3654                 return;
3655
3656         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3657             MLX5_SQC_STATE_RST);
3658         if (err != 0) {
3659                 if_printf(sq->ifp,
3660                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3661         }
3662
3663         sq->cc = 0;
3664         sq->pc = 0;
3665
3666         /* reset doorbell prior to moving from RST to RDY */
3667         mlx5e_reset_sq_doorbell_record(sq);
3668
3669         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3670             MLX5_SQC_STATE_RDY);
3671         if (err != 0) {
3672                 if_printf(sq->ifp,
3673                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3674         }
3675
3676         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3677         WRITE_ONCE(sq->running, 1);
3678 }
3679
3680 static void
3681 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3682 {
3683         int i;
3684
3685         for (i = 0; i < ch->num_tc; i++)
3686                 mlx5e_resume_sq(&ch->sq[i]);
3687 }
3688
3689 static void
3690 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3691 {
3692         struct mlx5e_rq *rq = &ch->rq;
3693         int err;
3694
3695         mtx_lock(&rq->mtx);
3696         rq->enabled = 0;
3697         callout_stop(&rq->watchdog);
3698         mtx_unlock(&rq->mtx);
3699
3700         callout_drain(&rq->watchdog);
3701
3702         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3703         if (err != 0) {
3704                 if_printf(rq->ifp,
3705                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3706         }
3707
3708         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3709                 msleep(1);
3710                 rq->cq.mcq.comp(&rq->cq.mcq);
3711         }
3712
3713         /*
3714          * Transitioning into RST state will allow the FW to track less ERR state queues,
3715          * thus reducing the recv queue flushing time
3716          */
3717         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3718         if (err != 0) {
3719                 if_printf(rq->ifp,
3720                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3721         }
3722 }
3723
3724 static void
3725 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3726 {
3727         struct mlx5e_rq *rq = &ch->rq;
3728         int err;
3729
3730         rq->wq.wqe_ctr = 0;
3731         mlx5_wq_ll_update_db_record(&rq->wq);
3732         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3733         if (err != 0) {
3734                 if_printf(rq->ifp,
3735                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3736         }
3737
3738         rq->enabled = 1;
3739
3740         rq->cq.mcq.comp(&rq->cq.mcq);
3741 }
3742
3743 void
3744 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3745 {
3746         int i;
3747
3748         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3749                 return;
3750
3751         for (i = 0; i < priv->params.num_channels; i++) {
3752                 if (value)
3753                         mlx5e_disable_tx_dma(&priv->channel[i]);
3754                 else
3755                         mlx5e_enable_tx_dma(&priv->channel[i]);
3756         }
3757 }
3758
3759 void
3760 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3761 {
3762         int i;
3763
3764         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3765                 return;
3766
3767         for (i = 0; i < priv->params.num_channels; i++) {
3768                 if (value)
3769                         mlx5e_disable_rx_dma(&priv->channel[i]);
3770                 else
3771                         mlx5e_enable_rx_dma(&priv->channel[i]);
3772         }
3773 }
3774
3775 static void
3776 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3777 {
3778         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3779             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3780             sysctl_firmware, "A", "HCA firmware version");
3781
3782         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3783             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3784             "Board ID");
3785 }
3786
3787 static int
3788 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3789 {
3790         struct mlx5e_priv *priv = arg1;
3791         uint8_t temp[MLX5E_MAX_PRIORITY];
3792         uint32_t tx_pfc;
3793         int err;
3794         int i;
3795
3796         PRIV_LOCK(priv);
3797
3798         tx_pfc = priv->params.tx_priority_flow_control;
3799
3800         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3801                 temp[i] = (tx_pfc >> i) & 1;
3802
3803         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3804         if (err || !req->newptr)
3805                 goto done;
3806         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3807         if (err)
3808                 goto done;
3809
3810         priv->params.tx_priority_flow_control = 0;
3811
3812         /* range check input value */
3813         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3814                 if (temp[i] > 1) {
3815                         err = ERANGE;
3816                         goto done;
3817                 }
3818                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3819         }
3820
3821         /* check if update is required */
3822         if (tx_pfc != priv->params.tx_priority_flow_control)
3823                 err = -mlx5e_set_port_pfc(priv);
3824 done:
3825         if (err != 0)
3826                 priv->params.tx_priority_flow_control= tx_pfc;
3827         PRIV_UNLOCK(priv);
3828
3829         return (err);
3830 }
3831
3832 static int
3833 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3834 {
3835         struct mlx5e_priv *priv = arg1;
3836         uint8_t temp[MLX5E_MAX_PRIORITY];
3837         uint32_t rx_pfc;
3838         int err;
3839         int i;
3840
3841         PRIV_LOCK(priv);
3842
3843         rx_pfc = priv->params.rx_priority_flow_control;
3844
3845         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3846                 temp[i] = (rx_pfc >> i) & 1;
3847
3848         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3849         if (err || !req->newptr)
3850                 goto done;
3851         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3852         if (err)
3853                 goto done;
3854
3855         priv->params.rx_priority_flow_control = 0;
3856
3857         /* range check input value */
3858         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3859                 if (temp[i] > 1) {
3860                         err = ERANGE;
3861                         goto done;
3862                 }
3863                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3864         }
3865
3866         /* check if update is required */
3867         if (rx_pfc != priv->params.rx_priority_flow_control)
3868                 err = -mlx5e_set_port_pfc(priv);
3869 done:
3870         if (err != 0)
3871                 priv->params.rx_priority_flow_control= rx_pfc;
3872         PRIV_UNLOCK(priv);
3873
3874         return (err);
3875 }
3876
3877 static void
3878 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3879 {
3880 #if (__FreeBSD_version < 1100000)
3881         char path[96];
3882 #endif
3883         int error;
3884
3885         /* enable pauseframes by default */
3886         priv->params.tx_pauseframe_control = 1;
3887         priv->params.rx_pauseframe_control = 1;
3888
3889         /* disable ports flow control, PFC, by default */
3890         priv->params.tx_priority_flow_control = 0;
3891         priv->params.rx_priority_flow_control = 0;
3892
3893 #if (__FreeBSD_version < 1100000)
3894         /* compute path for sysctl */
3895         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3896             device_get_unit(priv->mdev->pdev->dev.bsddev));
3897
3898         /* try to fetch tunable, if any */
3899         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3900
3901         /* compute path for sysctl */
3902         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3903             device_get_unit(priv->mdev->pdev->dev.bsddev));
3904
3905         /* try to fetch tunable, if any */
3906         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3907 #endif
3908
3909         /* register pauseframe SYSCTLs */
3910         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3911             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3912             &priv->params.tx_pauseframe_control, 0,
3913             "Set to enable TX pause frames. Clear to disable.");
3914
3915         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3916             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3917             &priv->params.rx_pauseframe_control, 0,
3918             "Set to enable RX pause frames. Clear to disable.");
3919
3920         /* register priority flow control, PFC, SYSCTLs */
3921         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3922             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3923             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3924             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3925
3926         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3927             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3928             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3929             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3930
3931         PRIV_LOCK(priv);
3932
3933         /* range check */
3934         priv->params.tx_pauseframe_control =
3935             priv->params.tx_pauseframe_control ? 1 : 0;
3936         priv->params.rx_pauseframe_control =
3937             priv->params.rx_pauseframe_control ? 1 : 0;
3938
3939         /* update firmware */
3940         error = mlx5e_set_port_pause_and_pfc(priv);
3941         if (error == -EINVAL) {
3942                 if_printf(priv->ifp,
3943                     "Global pauseframes must be disabled before enabling PFC.\n");
3944                 priv->params.rx_priority_flow_control = 0;
3945                 priv->params.tx_priority_flow_control = 0;
3946
3947                 /* update firmware */
3948                 (void) mlx5e_set_port_pause_and_pfc(priv);
3949         }
3950         PRIV_UNLOCK(priv);
3951 }
3952
3953 static int
3954 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
3955     union if_snd_tag_alloc_params *params,
3956     struct m_snd_tag **ppmt)
3957 {
3958         struct mlx5e_priv *priv;
3959         struct mlx5e_channel *pch;
3960
3961         priv = ifp->if_softc;
3962
3963         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
3964                 return (EOPNOTSUPP);
3965         } else {
3966                 /* keep this code synced with mlx5e_select_queue() */
3967                 u32 ch = priv->params.num_channels;
3968 #ifdef RSS
3969                 u32 temp;
3970
3971                 if (rss_hash2bucket(params->hdr.flowid,
3972                     params->hdr.flowtype, &temp) == 0)
3973                         ch = temp % ch;
3974                 else
3975 #endif
3976                         ch = (params->hdr.flowid % 128) % ch;
3977
3978                 /*
3979                  * NOTE: The channels array is only freed at detach
3980                  * and it safe to return a pointer to the send tag
3981                  * inside the channels structure as long as we
3982                  * reference the priv.
3983                  */
3984                 pch = priv->channel + ch;
3985
3986                 /* check if send queue is not running */
3987                 if (unlikely(pch->sq[0].running == 0))
3988                         return (ENXIO);
3989                 mlx5e_ref_channel(priv);
3990                 *ppmt = &pch->tag.m_snd_tag;
3991                 return (0);
3992         }
3993 }
3994
3995 static int
3996 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3997 {
3998         struct mlx5e_channel *pch =
3999             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4000
4001         params->unlimited.max_rate = -1ULL;
4002         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4003         return (0);
4004 }
4005
4006 static void
4007 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4008 {
4009         struct mlx5e_channel *pch =
4010             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4011
4012         mlx5e_unref_channel(pch->priv);
4013 }
4014
4015 static int
4016 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4017     union if_snd_tag_alloc_params *params,
4018     struct m_snd_tag **ppmt)
4019 {
4020
4021         switch (params->hdr.type) {
4022 #ifdef RATELIMIT
4023         case IF_SND_TAG_TYPE_RATE_LIMIT:
4024                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4025 #endif
4026         case IF_SND_TAG_TYPE_UNLIMITED:
4027                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4028         default:
4029                 return (EOPNOTSUPP);
4030         }
4031 }
4032
4033 static int
4034 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4035 {
4036         struct mlx5e_snd_tag *tag =
4037             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4038
4039         switch (tag->type) {
4040 #ifdef RATELIMIT
4041         case IF_SND_TAG_TYPE_RATE_LIMIT:
4042                 return (mlx5e_rl_snd_tag_modify(pmt, params));
4043 #endif
4044         case IF_SND_TAG_TYPE_UNLIMITED:
4045         default:
4046                 return (EOPNOTSUPP);
4047         }
4048 }
4049
4050 static int
4051 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4052 {
4053         struct mlx5e_snd_tag *tag =
4054             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4055
4056         switch (tag->type) {
4057 #ifdef RATELIMIT
4058         case IF_SND_TAG_TYPE_RATE_LIMIT:
4059                 return (mlx5e_rl_snd_tag_query(pmt, params));
4060 #endif
4061         case IF_SND_TAG_TYPE_UNLIMITED:
4062                 return (mlx5e_ul_snd_tag_query(pmt, params));
4063         default:
4064                 return (EOPNOTSUPP);
4065         }
4066 }
4067
4068 static void
4069 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4070 {
4071         struct mlx5e_snd_tag *tag =
4072             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4073
4074         switch (tag->type) {
4075 #ifdef RATELIMIT
4076         case IF_SND_TAG_TYPE_RATE_LIMIT:
4077                 mlx5e_rl_snd_tag_free(pmt);
4078                 break;
4079 #endif
4080         case IF_SND_TAG_TYPE_UNLIMITED:
4081                 mlx5e_ul_snd_tag_free(pmt);
4082                 break;
4083         default:
4084                 break;
4085         }
4086 }
4087
4088 static void *
4089 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4090 {
4091         struct ifnet *ifp;
4092         struct mlx5e_priv *priv;
4093         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4094         u8 connector_type;
4095         struct sysctl_oid_list *child;
4096         int ncv = mdev->priv.eq_table.num_comp_vectors;
4097         char unit[16];
4098         struct pfil_head_args pa;
4099         int err;
4100         int i,j;
4101         u32 eth_proto_cap;
4102         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4103         bool ext = 0;
4104         u32 speeds_num;
4105         struct media media_entry = {};
4106
4107         if (mlx5e_check_required_hca_cap(mdev)) {
4108                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4109                 return (NULL);
4110         }
4111         /*
4112          * Try to allocate the priv and make room for worst-case
4113          * number of channel structures:
4114          */
4115         priv = malloc(sizeof(*priv) +
4116             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4117             M_MLX5EN, M_WAITOK | M_ZERO);
4118         mlx5e_priv_mtx_init(priv);
4119
4120         ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4121         if (ifp == NULL) {
4122                 mlx5_core_err(mdev, "if_alloc() failed\n");
4123                 goto err_free_priv;
4124         }
4125         ifp->if_softc = priv;
4126         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4127         ifp->if_mtu = ETHERMTU;
4128         ifp->if_init = mlx5e_open;
4129         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
4130         ifp->if_ioctl = mlx5e_ioctl;
4131         ifp->if_transmit = mlx5e_xmit;
4132         ifp->if_qflush = if_qflush;
4133 #if (__FreeBSD_version >= 1100000)
4134         ifp->if_get_counter = mlx5e_get_counter;
4135 #endif
4136         ifp->if_snd.ifq_maxlen = ifqmaxlen;
4137         /*
4138          * Set driver features
4139          */
4140         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4141         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4142         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4143         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4144         ifp->if_capabilities |= IFCAP_LRO;
4145         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4146         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4147         ifp->if_capabilities |= IFCAP_TXRTLMT;
4148         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4149         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4150         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4151         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4152
4153         /* set TSO limits so that we don't have to drop TX packets */
4154         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4155         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4156         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4157
4158         ifp->if_capenable = ifp->if_capabilities;
4159         ifp->if_hwassist = 0;
4160         if (ifp->if_capenable & IFCAP_TSO)
4161                 ifp->if_hwassist |= CSUM_TSO;
4162         if (ifp->if_capenable & IFCAP_TXCSUM)
4163                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4164         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4165                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4166
4167         /* ifnet sysctl tree */
4168         sysctl_ctx_init(&priv->sysctl_ctx);
4169         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4170             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
4171         if (priv->sysctl_ifnet == NULL) {
4172                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4173                 goto err_free_sysctl;
4174         }
4175         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4176         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4177             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
4178         if (priv->sysctl_ifnet == NULL) {
4179                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4180                 goto err_free_sysctl;
4181         }
4182
4183         /* HW sysctl tree */
4184         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4185         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4186             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
4187         if (priv->sysctl_hw == NULL) {
4188                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4189                 goto err_free_sysctl;
4190         }
4191
4192         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4193         if (err) {
4194                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4195                 goto err_free_sysctl;
4196         }
4197
4198         /* reuse mlx5core's watchdog workqueue */
4199         priv->wq = mdev->priv.health.wq_watchdog;
4200
4201         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4202         if (err) {
4203                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
4204                     __func__, err);
4205                 goto err_free_wq;
4206         }
4207         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4208         if (err) {
4209                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
4210                     __func__, err);
4211                 goto err_unmap_free_uar;
4212         }
4213         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4214         if (err) {
4215                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
4216                     __func__, err);
4217                 goto err_dealloc_pd;
4218         }
4219         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4220         if (err) {
4221                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
4222                     __func__, err);
4223                 goto err_dealloc_transport_domain;
4224         }
4225         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4226
4227         /* check if we should generate a random MAC address */
4228         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4229             is_zero_ether_addr(dev_addr)) {
4230                 random_ether_addr(dev_addr);
4231                 if_printf(ifp, "Assigned random MAC address\n");
4232         }
4233 #ifdef RATELIMIT
4234         err = mlx5e_rl_init(priv);
4235         if (err) {
4236                 if_printf(ifp, "%s: mlx5e_rl_init failed, %d\n",
4237                     __func__, err);
4238                 goto err_create_mkey;
4239         }
4240 #endif
4241
4242         /* set default MTU */
4243         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4244
4245         /* Set default media status */
4246         priv->media_status_last = IFM_AVALID;
4247         priv->media_active_last = IFM_ETHER | IFM_AUTO |
4248             IFM_ETH_RXPAUSE | IFM_FDX;
4249
4250         /* setup default pauseframes configuration */
4251         mlx5e_setup_pauseframes(priv);
4252
4253         /* Setup supported medias */
4254         //TODO: If we failed to query ptys is it ok to proceed??
4255         if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4256                 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4257                     ptys_extended_ethernet);
4258                 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4259                     eth_proto_capability);
4260                 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4261                         connector_type = MLX5_GET(ptys_reg, out,
4262                             connector_type);
4263         } else {
4264                 eth_proto_cap = 0;
4265                 if_printf(ifp, "%s: Query port media capability failed,"
4266                     " %d\n", __func__, err);
4267         }
4268
4269         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4270             mlx5e_media_change, mlx5e_media_status);
4271
4272         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4273         for (i = 0; i != speeds_num; i++) {
4274                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4275                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4276                             mlx5e_mode_table[i][j];
4277                         if (media_entry.baudrate == 0)
4278                                 continue;
4279                         if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4280                                 ifmedia_add(&priv->media,
4281                                     media_entry.subtype |
4282                                     IFM_ETHER, 0, NULL);
4283                                 ifmedia_add(&priv->media,
4284                                     media_entry.subtype |
4285                                     IFM_ETHER | IFM_FDX |
4286                                     IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4287                         }
4288                 }
4289         }
4290
4291         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4292         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4293             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4294
4295         /* Set autoselect by default */
4296         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4297             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4298         ether_ifattach(ifp, dev_addr);
4299
4300         /* Register for VLAN events */
4301         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4302             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4303         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4304             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4305
4306         /* Link is down by default */
4307         if_link_state_change(ifp, LINK_STATE_DOWN);
4308
4309         mlx5e_enable_async_events(priv);
4310
4311         mlx5e_add_hw_stats(priv);
4312
4313         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4314             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4315             priv->stats.vport.arg);
4316
4317         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4318             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4319             priv->stats.pport.arg);
4320
4321         mlx5e_create_ethtool(priv);
4322
4323         mtx_lock(&priv->async_events_mtx);
4324         mlx5e_update_stats(priv);
4325         mtx_unlock(&priv->async_events_mtx);
4326
4327         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4328             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4329             &priv->clbr_done, 0,
4330             "RX timestamps calibration state");
4331         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
4332         mlx5e_reset_calibration_callout(priv);
4333
4334         pa.pa_version = PFIL_VERSION;
4335         pa.pa_flags = PFIL_IN;
4336         pa.pa_type = PFIL_TYPE_ETHERNET;
4337         pa.pa_headname = ifp->if_xname;
4338         priv->pfil = pfil_head_register(&pa);
4339
4340         return (priv);
4341
4342 #ifdef RATELIMIT
4343 err_create_mkey:
4344         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4345 #endif
4346 err_dealloc_transport_domain:
4347         mlx5_dealloc_transport_domain(mdev, priv->tdn);
4348
4349 err_dealloc_pd:
4350         mlx5_core_dealloc_pd(mdev, priv->pdn);
4351
4352 err_unmap_free_uar:
4353         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4354
4355 err_free_wq:
4356         flush_workqueue(priv->wq);
4357
4358 err_free_sysctl:
4359         sysctl_ctx_free(&priv->sysctl_ctx);
4360         if (priv->sysctl_debug)
4361                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4362         if_free(ifp);
4363
4364 err_free_priv:
4365         mlx5e_priv_mtx_destroy(priv);
4366         free(priv, M_MLX5EN);
4367         return (NULL);
4368 }
4369
4370 static void
4371 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4372 {
4373         struct mlx5e_priv *priv = vpriv;
4374         struct ifnet *ifp = priv->ifp;
4375
4376         /* don't allow more IOCTLs */
4377         priv->gone = 1;
4378
4379         /* XXX wait a bit to allow IOCTL handlers to complete */
4380         pause("W", hz);
4381
4382 #ifdef RATELIMIT
4383         /*
4384          * The kernel can have reference(s) via the m_snd_tag's into
4385          * the ratelimit channels, and these must go away before
4386          * detaching:
4387          */
4388         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4389                 if_printf(priv->ifp, "Waiting for all ratelimit connections "
4390                     "to terminate\n");
4391                 pause("W", hz);
4392         }
4393 #endif
4394         /* stop watchdog timer */
4395         callout_drain(&priv->watchdog);
4396
4397         callout_drain(&priv->tstmp_clbr);
4398
4399         if (priv->vlan_attach != NULL)
4400                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4401         if (priv->vlan_detach != NULL)
4402                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4403
4404         /* make sure device gets closed */
4405         PRIV_LOCK(priv);
4406         mlx5e_close_locked(ifp);
4407         PRIV_UNLOCK(priv);
4408
4409         /* wait for all unlimited send tags to go away */
4410         while (priv->channel_refs != 0) {
4411                 if_printf(priv->ifp, "Waiting for all unlimited connections "
4412                     "to terminate\n");
4413                 pause("W", hz);
4414         }
4415
4416         /* deregister pfil */
4417         if (priv->pfil != NULL) {
4418                 pfil_head_unregister(priv->pfil);
4419                 priv->pfil = NULL;
4420         }
4421
4422         /* unregister device */
4423         ifmedia_removeall(&priv->media);
4424         ether_ifdetach(ifp);
4425         if_free(ifp);
4426
4427 #ifdef RATELIMIT
4428         mlx5e_rl_cleanup(priv);
4429 #endif
4430         /* destroy all remaining sysctl nodes */
4431         sysctl_ctx_free(&priv->stats.vport.ctx);
4432         sysctl_ctx_free(&priv->stats.pport.ctx);
4433         if (priv->sysctl_debug)
4434                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4435         sysctl_ctx_free(&priv->sysctl_ctx);
4436
4437         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4438         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4439         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4440         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4441         mlx5e_disable_async_events(priv);
4442         flush_workqueue(priv->wq);
4443         mlx5e_priv_mtx_destroy(priv);
4444         free(priv, M_MLX5EN);
4445 }
4446
4447 static void *
4448 mlx5e_get_ifp(void *vpriv)
4449 {
4450         struct mlx5e_priv *priv = vpriv;
4451
4452         return (priv->ifp);
4453 }
4454
4455 static struct mlx5_interface mlx5e_interface = {
4456         .add = mlx5e_create_ifp,
4457         .remove = mlx5e_destroy_ifp,
4458         .event = mlx5e_async_event,
4459         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4460         .get_dev = mlx5e_get_ifp,
4461 };
4462
4463 void
4464 mlx5e_init(void)
4465 {
4466         mlx5_register_interface(&mlx5e_interface);
4467 }
4468
4469 void
4470 mlx5e_cleanup(void)
4471 {
4472         mlx5_unregister_interface(&mlx5e_interface);
4473 }
4474
4475 static void
4476 mlx5e_show_version(void __unused *arg)
4477 {
4478
4479         printf("%s", mlx5e_version);
4480 }
4481 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4482
4483 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4484 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4485
4486 #if (__FreeBSD_version >= 1100000)
4487 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4488 #endif
4489 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4490 MODULE_VERSION(mlx5en, 1);