sys/mips/cavium/octeon_wdog.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
   5  * Copyright (c) 2010-2011, Juli Mallett <jmallett@FreeBSD.org>
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice unmodified, this list of conditions, and the following
  13  *    disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  */
  30
  31 /*
  32  * Watchdog driver for Cavium Octeon
  33  */
  34
  35 #include <sys/cdefs.h>
  36 __FBSDID("$FreeBSD$");
  37
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40 #include <sys/watchdog.h>
  41 #include <sys/bus.h>
  42 #include <sys/eventhandler.h>
  43 #include <sys/kernel.h>
  44 #include <sys/module.h>
  45 #include <sys/sysctl.h>
  46 #include <sys/rman.h>
  47 #include <sys/smp.h>
  48
  49 #include <contrib/octeon-sdk/cvmx.h>
  50 #include <mips/cavium/octeon_irq.h>
  51
  52 #define DEFAULT_TIMER_VAL       65535
  53
  54 struct octeon_wdog_softc {
  55         device_t sc_dev;
  56         struct octeon_wdog_core_softc {
  57                 int csc_core;
  58                 struct resource *csc_intr;
  59                 void *csc_intr_cookie;
  60         } sc_cores[MAXCPU];
  61         int sc_armed;
  62         int sc_debug;
  63 };
  64
  65 extern void octeon_wdog_nmi_handler(void);
  66 void octeon_wdog_nmi(void);
  67
  68 static void octeon_watchdog_arm_core(int);
  69 static void octeon_watchdog_disarm_core(int);
  70 static int octeon_wdog_attach(device_t);
  71 static void octeon_wdog_identify(driver_t *, device_t);
  72 static int octeon_wdog_intr(void *);
  73 static int octeon_wdog_probe(device_t);
  74 static void octeon_wdog_setup(struct octeon_wdog_softc *, int);
  75 static void octeon_wdog_sysctl(device_t);
  76 static void octeon_wdog_watchdog_fn(void *, u_int, int *);
  77
  78 void
  79 octeon_wdog_nmi(void)
  80 {
  81         int core;
  82
  83         core = cvmx_get_core_num();
  84
  85         printf("cpu%u: NMI detected\n", core);
  86         printf("cpu%u: Exception PC: %p\n", core, (void *)mips_rd_excpc());
  87         printf("cpu%u: status %#x cause %#x\n", core, mips_rd_status(), mips_rd_cause());
  88
  89         /*
  90          * This is the end
  91          * Beautiful friend
  92          *
  93          * Just wait for Soft Reset to come and take us
  94          */
  95         for (;;)
  96                 continue;
  97 }
  98
  99 static void
 100 octeon_watchdog_arm_core(int core)
 101 {
 102         cvmx_ciu_wdogx_t ciu_wdog;
 103
 104         /* Poke it! */
 105         cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
 106
 107         /*
 108          * XXX
 109          * Perhaps if KDB is enabled, we should use mode=2 and drop into the
 110          * debugger on NMI?
 111          *
 112          * XXX
 113          * Timer should be calculated based on CPU frquency
 114          */
 115         ciu_wdog.u64 = 0;
 116         ciu_wdog.s.len = DEFAULT_TIMER_VAL;
 117         ciu_wdog.s.mode = 3;
 118         cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
 119 }
 120
 121 static void
 122 octeon_watchdog_disarm_core(int core)
 123 {
 124
 125         cvmx_write_csr(CVMX_CIU_WDOGX(core), 0);
 126 }
 127
 128 static void
 129 octeon_wdog_watchdog_fn(void *private, u_int cmd, int *error)
 130 {
 131         struct octeon_wdog_softc *sc = private;
 132         int core;
 133
 134         cmd &= WD_INTERVAL;
 135         if (sc->sc_debug)
 136                 device_printf(sc->sc_dev, "%s: cmd: %x\n", __func__, cmd);
 137         if (cmd > 0) {
 138                 CPU_FOREACH(core)
 139                         octeon_watchdog_arm_core(core);
 140                 sc->sc_armed = 1;
 141                 *error = 0;
 142         } else {
 143                 if (sc->sc_armed) {
 144                         CPU_FOREACH(core)
 145                                 octeon_watchdog_disarm_core(core);
 146                         sc->sc_armed = 0;
 147                 }
 148         }
 149 }
 150
 151 static void
 152 octeon_wdog_sysctl(device_t dev)
 153 {
 154         struct octeon_wdog_softc *sc = device_get_softc(dev);
 155
 156         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
 157         struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
 158
 159         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 160                 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
 161                 "enable watchdog debugging");
 162         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 163                 "armed", CTLFLAG_RD, &sc->sc_armed, 0,
 164                 "whether the watchdog is armed");
 165 }
 166
 167 static void
 168 octeon_wdog_setup(struct octeon_wdog_softc *sc, int core)
 169 {
 170         struct octeon_wdog_core_softc *csc;
 171         int rid, error;
 172
 173         csc = &sc->sc_cores[core];
 174
 175         csc->csc_core = core;
 176
 177         /* Interrupt part */
 178         rid = 0;
 179         csc->csc_intr = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ, &rid,
 180             OCTEON_IRQ_WDOG0 + core, OCTEON_IRQ_WDOG0 + core, 1, RF_ACTIVE);
 181         if (csc->csc_intr == NULL)
 182                 panic("%s: bus_alloc_resource for core %u failed",
 183                     __func__, core);
 184
 185         error = bus_setup_intr(sc->sc_dev, csc->csc_intr, INTR_TYPE_MISC,
 186             octeon_wdog_intr, NULL, csc, &csc->csc_intr_cookie);
 187         if (error != 0)
 188                 panic("%s: bus_setup_intr for core %u: %d", __func__, core,
 189                     error);
 190
 191         bus_bind_intr(sc->sc_dev, csc->csc_intr, core);
 192         bus_describe_intr(sc->sc_dev, csc->csc_intr, csc->csc_intr_cookie,
 193             "cpu%u", core);
 194
 195         if (sc->sc_armed) {
 196                 /* Armed by default.  */
 197                 octeon_watchdog_arm_core(core);
 198         } else {
 199                 /* Disarmed by default.  */
 200                 octeon_watchdog_disarm_core(core);
 201         }
 202 }
 203
 204 static int
 205 octeon_wdog_intr(void *arg)
 206 {
 207         struct octeon_wdog_core_softc *csc = arg;
 208
 209         KASSERT(csc->csc_core == cvmx_get_core_num(),
 210             ("got watchdog interrupt for core %u on core %u.",
 211              csc->csc_core, cvmx_get_core_num()));
 212
 213         (void)csc;
 214
 215         /* Poke it! */
 216         cvmx_write_csr(CVMX_CIU_PP_POKEX(cvmx_get_core_num()), 1);
 217
 218         return (FILTER_HANDLED);
 219 }
 220
 221 static int
 222 octeon_wdog_probe(device_t dev)
 223 {
 224
 225         device_set_desc(dev, "Cavium Octeon watchdog timer");
 226         return (0);
 227 }
 228
 229 static int
 230 octeon_wdog_attach(device_t dev)
 231 {
 232         struct octeon_wdog_softc *sc = device_get_softc(dev);
 233         uint64_t *nmi_handler = (uint64_t*)octeon_wdog_nmi_handler;
 234         int core, i;
 235
 236         /* Initialise */
 237         sc->sc_armed = 0; /* XXX Ought to be a tunable / config option.  */
 238         sc->sc_debug = 0;
 239
 240         sc->sc_dev = dev;
 241         EVENTHANDLER_REGISTER(watchdog_list, octeon_wdog_watchdog_fn, sc, 0);
 242         octeon_wdog_sysctl(dev);
 243
 244         for (i = 0; i < 16; i++) {
 245                 cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
 246                 cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, nmi_handler[i]);
 247         }
 248
 249         cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
 250
 251         CPU_FOREACH(core)
 252                 octeon_wdog_setup(sc, core);
 253         return (0);
 254 }
 255
 256 static void
 257 octeon_wdog_identify(driver_t *drv, device_t parent)
 258 {
 259
 260         BUS_ADD_CHILD(parent, 0, "owdog", 0);
 261 }
 262
 263 static device_method_t octeon_wdog_methods[] = {
 264         DEVMETHOD(device_identify, octeon_wdog_identify),
 265
 266         DEVMETHOD(device_probe, octeon_wdog_probe),
 267         DEVMETHOD(device_attach, octeon_wdog_attach),
 268         {0, 0},
 269 };
 270
 271 static driver_t octeon_wdog_driver = {
 272         "owdog",
 273         octeon_wdog_methods,
 274         sizeof(struct octeon_wdog_softc),
 275 };
 276 static devclass_t octeon_wdog_devclass;
 277
 278 DRIVER_MODULE(owdog, ciu, octeon_wdog_driver, octeon_wdog_devclass, 0, 0);